xref: /openbmc/u-boot/include/configs/adp-ag101p.h (revision ee7bb5be)
1 /*
2  * Copyright (C) 2011 Andes Technology Corporation
3  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 #include <asm/arch-ag101/ag101.h>
13 
14 /*
15  * CPU and Board Configuration Options
16  */
17 #define CONFIG_ADP_AG101P
18 
19 #define CONFIG_USE_INTERRUPT
20 
21 #define CONFIG_SKIP_LOWLEVEL_INIT
22 
23 #define CONFIG_SYS_GENERIC_GLOBAL_DATA
24 
25 /*
26  * Definitions related to passing arguments to kernel.
27  */
28 #define CONFIG_CMDLINE_TAG			/* send commandline to Kernel */
29 #define CONFIG_SETUP_MEMORY_TAGS	/* send memory definition to kernel */
30 #define CONFIG_INITRD_TAG			/* send initrd params */
31 #define CONFIG_NEEDS_MANUAL_RELOC
32 
33 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
34 #define CONFIG_MEM_REMAP
35 #endif
36 
37 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
38 #define CONFIG_SYS_TEXT_BASE	0x00500000
39 #else
40 #ifdef CONFIG_MEM_REMAP
41 #define CONFIG_SYS_TEXT_BASE	0x80000000
42 #else
43 #define CONFIG_SYS_TEXT_BASE	0x00000000
44 #endif
45 #endif
46 
47 /*
48  * Timer
49  */
50 #define CONFIG_SYS_CLK_FREQ	39062500
51 #define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
52 
53 /*
54  * Use Externel CLOCK or PCLK
55  */
56 #undef CONFIG_FTRTC010_EXTCLK
57 
58 #ifndef CONFIG_FTRTC010_EXTCLK
59 #define CONFIG_FTRTC010_PCLK
60 #endif
61 
62 #ifdef CONFIG_FTRTC010_EXTCLK
63 #define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
64 #else
65 #define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
66 #endif
67 
68 #define TIMER_LOAD_VAL	0xffffffff
69 
70 /*
71  * Real Time Clock
72  */
73 #define CONFIG_RTC_FTRTC010
74 
75 /*
76  * Real Time Clock Divider
77  * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
78  */
79 #define OSC_5MHZ			(5*1000000)
80 #define OSC_CLK				(4*OSC_5MHZ)
81 #define RTC_DIV_COUNT			(0.5)	/* Why?? */
82 
83 /*
84  * Serial console configuration
85  */
86 
87 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
88 #define CONFIG_BAUDRATE			38400
89 #define CONFIG_CONS_INDEX		1
90 #define CONFIG_SYS_NS16550_SERIAL
91 #define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
92 #define CONFIG_SYS_NS16550_REG_SIZE	-4
93 #define CONFIG_SYS_NS16550_CLK		((18432000 * 20) / 25)	/* AG101P */
94 
95 /*
96  * Ethernet
97  */
98 #define CONFIG_FTMAC100
99 
100 #define CONFIG_BOOTDELAY	3
101 
102 /*
103  * SD (MMC) controller
104  */
105 #define CONFIG_MMC
106 #define CONFIG_GENERIC_MMC
107 #define CONFIG_DOS_PARTITION
108 #define CONFIG_FTSDC010
109 #define CONFIG_FTSDC010_NUMBER		1
110 #define CONFIG_FTSDC010_SDIO
111 
112 /*
113  * Command line configuration.
114  */
115 #define CONFIG_CMD_DATE
116 
117 /*
118  * Miscellaneous configurable options
119  */
120 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
121 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
122 
123 /* Print Buffer Size */
124 #define CONFIG_SYS_PBSIZE	\
125 	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
126 
127 /* max number of command args */
128 #define CONFIG_SYS_MAXARGS	16
129 
130 /* Boot Argument Buffer Size */
131 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
132 
133 /*
134  * Size of malloc() pool
135  */
136 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
137 #define CONFIG_SYS_MALLOC_LEN		(512 << 10)
138 
139 /*
140  * AHB Controller configuration
141  */
142 #define CONFIG_FTAHBC020S
143 
144 #ifdef CONFIG_FTAHBC020S
145 #include <faraday/ftahbc020s.h>
146 
147 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
148 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100
149 
150 /*
151  * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
152  * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
153  * in C language.
154  */
155 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
156 	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
157 					FTAHBC020S_SLAVE_BSR_SIZE(0xb))
158 #endif
159 
160 /*
161  * Watchdog
162  */
163 #define CONFIG_FTWDT010_WATCHDOG
164 
165 /*
166  * PMU Power controller configuration
167  */
168 #define CONFIG_PMU
169 #define CONFIG_FTPMU010_POWER
170 
171 #ifdef CONFIG_FTPMU010_POWER
172 #include <faraday/ftpmu010.h>
173 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS		0x0E
174 #define CONFIG_SYS_FTPMU010_SDRAMHTC	(FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
175 					 FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
176 					 FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
177 					 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
178 					 FTPMU010_SDRAMHTC_CKE_DCSR	 | \
179 					 FTPMU010_SDRAMHTC_DQM_DCSR	 | \
180 					 FTPMU010_SDRAMHTC_SDCLK_DCSR)
181 #endif
182 
183 /*
184  * SDRAM controller configuration
185  */
186 #define CONFIG_FTSDMC021
187 
188 #ifdef CONFIG_FTSDMC021
189 #include <faraday/ftsdmc021.h>
190 
191 #define CONFIG_SYS_FTSDMC021_TP1	(FTSDMC021_TP1_TRAS(2)	|	\
192 					 FTSDMC021_TP1_TRP(1)	|	\
193 					 FTSDMC021_TP1_TRCD(1)	|	\
194 					 FTSDMC021_TP1_TRF(3)	|	\
195 					 FTSDMC021_TP1_TWR(1)	|	\
196 					 FTSDMC021_TP1_TCL(2))
197 
198 #define CONFIG_SYS_FTSDMC021_TP2	(FTSDMC021_TP2_INI_PREC(4) |	\
199 					 FTSDMC021_TP2_INI_REFT(8) |	\
200 					 FTSDMC021_TP2_REF_INTV(0x180))
201 
202 /*
203  * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
204  * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
205  * C language.
206  */
207 #define CONFIG_SYS_FTSDMC021_CR1	(FTSDMC021_CR1_DDW(2)	 |	\
208 					 FTSDMC021_CR1_DSZ(3)	 |	\
209 					 FTSDMC021_CR1_MBW(2)	 |	\
210 					 FTSDMC021_CR1_BNKSIZE(6))
211 
212 #define CONFIG_SYS_FTSDMC021_CR2	(FTSDMC021_CR2_IPREC	 |	\
213 					 FTSDMC021_CR2_IREF	 |	\
214 					 FTSDMC021_CR2_ISMR)
215 
216 #define CONFIG_SYS_FTSDMC021_BANK0_BASE	CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
217 #define CONFIG_SYS_FTSDMC021_BANK0_BSR	(FTSDMC021_BANK_ENABLE	 |	\
218 					 CONFIG_SYS_FTSDMC021_BANK0_BASE)
219 
220 #define CONFIG_SYS_FTSDMC021_BANK1_BASE	\
221 	(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
222 #define CONFIG_SYS_FTSDMC021_BANK1_BSR	(FTSDMC021_BANK_ENABLE	 |	\
223 					 CONFIG_SYS_FTSDMC021_BANK1_BASE)
224 #endif
225 
226 /*
227  * Physical Memory Map
228  */
229 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
230 #define PHYS_SDRAM_0	0x00000000  /* SDRAM Bank #1 */
231 #else
232 #ifdef CONFIG_MEM_REMAP
233 #define PHYS_SDRAM_0	0x00000000	/* SDRAM Bank #1 */
234 #else
235 #define PHYS_SDRAM_0	0x80000000	/* SDRAM Bank #1 */
236 #endif
237 #endif
238 
239 #define PHYS_SDRAM_1 \
240 	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)	/* SDRAM Bank #2 */
241 
242 #define CONFIG_NR_DRAM_BANKS	2		/* we have 2 bank of DRAM */
243 
244 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
245 #define PHYS_SDRAM_0_SIZE	0x20000000	/* 512 MB */
246 #define PHYS_SDRAM_1_SIZE	0x20000000	/* 512 MB */
247 #else
248 #ifdef CONFIG_MEM_REMAP
249 #define PHYS_SDRAM_0_SIZE	0x20000000	/* 512 MB */
250 #define PHYS_SDRAM_1_SIZE	0x20000000	/* 512 MB */
251 #else
252 #define PHYS_SDRAM_0_SIZE	0x08000000	/* 128 MB */
253 #define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
254 #endif
255 #endif
256 
257 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
258 
259 #ifdef CONFIG_MEM_REMAP
260 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
261 					GENERATED_GBL_DATA_SIZE)
262 #else
263 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
264 					GENERATED_GBL_DATA_SIZE)
265 #endif /* CONFIG_MEM_REMAP */
266 
267 /*
268  * Load address and memory test area should agree with
269  * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
270  */
271 #define CONFIG_SYS_LOAD_ADDR		0x300000
272 
273 /* memtest works on 63 MB in DRAM */
274 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
275 #define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)
276 
277 /*
278  * Static memory controller configuration
279  */
280 #define CONFIG_FTSMC020
281 
282 #ifdef CONFIG_FTSMC020
283 #include <faraday/ftsmc020.h>
284 
285 #define CONFIG_SYS_FTSMC020_CONFIGS	{			\
286 	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
287 	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
288 }
289 
290 #ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
291 #define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
292 					 FTSMC020_BANK_SIZE_32M	|	\
293 					 FTSMC020_BANK_MBW_32)
294 
295 #define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
296 					 FTSMC020_TPR_AST(1)	|	\
297 					 FTSMC020_TPR_CTW(1)	|	\
298 					 FTSMC020_TPR_ATI(1)	|	\
299 					 FTSMC020_TPR_AT2(1)	|	\
300 					 FTSMC020_TPR_WTC(1)	|	\
301 					 FTSMC020_TPR_AHT(1)	|	\
302 					 FTSMC020_TPR_TRNA(1))
303 #endif
304 
305 /*
306  * FLASH on ADP_AG101P is connected to BANK0
307  * Just disalbe the other BANK to avoid detection error.
308  */
309 #define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_ENABLE             |	\
310 				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
311 				 FTSMC020_BANK_SIZE_32M           |	\
312 				 FTSMC020_BANK_MBW_32)
313 
314 #define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_AST(3)   |	\
315 				 FTSMC020_TPR_CTW(3)   |	\
316 				 FTSMC020_TPR_ATI(0xf) |	\
317 				 FTSMC020_TPR_AT2(3)   |	\
318 				 FTSMC020_TPR_WTC(3)   |	\
319 				 FTSMC020_TPR_AHT(3)   |	\
320 				 FTSMC020_TPR_TRNA(0xf))
321 
322 #define FTSMC020_BANK1_CONFIG	(0x00)
323 #define FTSMC020_BANK1_TIMING	(0x00)
324 #endif /* CONFIG_FTSMC020 */
325 
326 /*
327  * FLASH and environment organization
328  */
329 /* use CFI framework */
330 #define CONFIG_SYS_FLASH_CFI
331 #define CONFIG_FLASH_CFI_DRIVER
332 
333 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
334 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
335 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
336 
337 /* support JEDEC */
338 
339 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
340 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
341 #define PHYS_FLASH_1			0x80000000	/* BANK 0 */
342 #else
343 #ifdef CONFIG_MEM_REMAP
344 #define PHYS_FLASH_1			0x80000000	/* BANK 0 */
345 #else
346 #define PHYS_FLASH_1			0x00000000	/* BANK 0 */
347 #endif
348 #endif	/* CONFIG_MEM_REMAP */
349 
350 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
351 #define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
352 #define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
353 
354 #define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
355 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
356 
357 /* max number of memory banks */
358 /*
359  * There are 4 banks supported for this Controller,
360  * but we have only 1 bank connected to flash on board
361  */
362 #define CONFIG_SYS_MAX_FLASH_BANKS	1
363 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
364 
365 /* max number of sectors on one chip */
366 #define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2)
367 #define CONFIG_ENV_SECT_SIZE		CONFIG_FLASH_SECTOR_SIZE
368 #define CONFIG_SYS_MAX_FLASH_SECT	512
369 
370 /* environments */
371 #define CONFIG_ENV_IS_IN_FLASH
372 #define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + 0x140000)
373 #define CONFIG_ENV_SIZE			8192
374 #define CONFIG_ENV_OVERWRITE
375 
376 #endif	/* __CONFIG_H */
377