1 /* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 #ifndef __CONFIG_H 25 #define __CONFIG_H 26 27 #include <asm/arch/ag101.h> 28 29 /* 30 * CPU and Board Configuration Options 31 */ 32 #define CONFIG_ADP_AG101P 33 34 #define CONFIG_USE_INTERRUPT 35 36 #define CONFIG_SKIP_LOWLEVEL_INIT 37 38 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 39 #define CONFIG_MEM_REMAP 40 #endif 41 42 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 43 #define CONFIG_SYS_TEXT_BASE 0x03200000 44 #else 45 #define CONFIG_SYS_TEXT_BASE 0x00000000 46 #endif 47 48 /* 49 * Timer 50 */ 51 52 /* 53 * According to the discussion in u-boot mailing list before, 54 * CONFIG_SYS_HZ at 1000 is mandatory. 55 */ 56 #define CONFIG_SYS_HZ 1000 57 #define CONFIG_SYS_CLK_FREQ 39062500 58 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 59 60 /* 61 * Use Externel CLOCK or PCLK 62 */ 63 #undef CONFIG_FTRTC010_EXTCLK 64 65 #ifndef CONFIG_FTRTC010_EXTCLK 66 #define CONFIG_FTRTC010_PCLK 67 #endif 68 69 #ifdef CONFIG_FTRTC010_EXTCLK 70 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 71 #else 72 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 73 #endif 74 75 #define TIMER_LOAD_VAL 0xffffffff 76 77 /* 78 * Real Time Clock 79 */ 80 #define CONFIG_RTC_FTRTC010 81 82 /* 83 * Real Time Clock Divider 84 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 85 */ 86 #define OSC_5MHZ (5*1000000) 87 #define OSC_CLK (4*OSC_5MHZ) 88 #define RTC_DIV_COUNT (0.5) /* Why?? */ 89 90 /* 91 * Serial console configuration 92 */ 93 94 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 95 #define CONFIG_BAUDRATE 38400 96 #define CONFIG_CONS_INDEX 1 97 #define CONFIG_SYS_NS16550 98 #define CONFIG_SYS_NS16550_SERIAL 99 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 100 #define CONFIG_SYS_NS16550_REG_SIZE -4 101 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 102 103 /* 104 * Ethernet 105 */ 106 #define CONFIG_FTMAC100 107 108 #define CONFIG_BOOTDELAY 3 109 110 /* 111 * SD (MMC) controller 112 */ 113 #define CONFIG_MMC 114 #define CONFIG_CMD_MMC 115 #define CONFIG_GENERIC_MMC 116 #define CONFIG_DOS_PARTITION 117 #define CONFIG_FTSDC010 118 #define CONFIG_FTSDC010_NUMBER 1 119 #define CONFIG_CMD_FAT 120 121 /* 122 * Command line configuration. 123 */ 124 #include <config_cmd_default.h> 125 126 #define CONFIG_CMD_CACHE 127 #define CONFIG_CMD_DATE 128 #define CONFIG_CMD_PING 129 130 /* 131 * Miscellaneous configurable options 132 */ 133 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 134 #define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */ 135 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 136 137 /* Print Buffer Size */ 138 #define CONFIG_SYS_PBSIZE \ 139 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 140 141 /* max number of command args */ 142 #define CONFIG_SYS_MAXARGS 16 143 144 /* Boot Argument Buffer Size */ 145 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 146 147 /* 148 * Stack sizes 149 * 150 * The stack sizes are set up in start.S using the settings below 151 */ 152 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ 153 154 /* 155 * Size of malloc() pool 156 */ 157 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 158 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 159 160 /* 161 * size in bytes reserved for initial data 162 */ 163 #define CONFIG_SYS_GBL_DATA_SIZE 128 164 165 /* 166 * AHB Controller configuration 167 */ 168 #define CONFIG_FTAHBC020S 169 170 #ifdef CONFIG_FTAHBC020S 171 #include <faraday/ftahbc020s.h> 172 173 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 174 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 175 176 /* 177 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 178 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 179 * in C language. 180 */ 181 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 182 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 183 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 184 #endif 185 186 /* 187 * Watchdog 188 */ 189 #define CONFIG_FTWDT010_WATCHDOG 190 191 /* 192 * PMU Power controller configuration 193 */ 194 #define CONFIG_PMU 195 #define CONFIG_FTPMU010_POWER 196 197 #ifdef CONFIG_FTPMU010_POWER 198 #include <faraday/ftpmu010.h> 199 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 200 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 201 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 202 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 203 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 204 FTPMU010_SDRAMHTC_CKE_DCSR | \ 205 FTPMU010_SDRAMHTC_DQM_DCSR | \ 206 FTPMU010_SDRAMHTC_SDCLK_DCSR) 207 #endif 208 209 /* 210 * SDRAM controller configuration 211 */ 212 #define CONFIG_FTSDMC021 213 214 #ifdef CONFIG_FTSDMC021 215 #include <faraday/ftsdmc021.h> 216 217 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 218 FTSDMC021_TP1_TRP(1) | \ 219 FTSDMC021_TP1_TRCD(1) | \ 220 FTSDMC021_TP1_TRF(3) | \ 221 FTSDMC021_TP1_TWR(1) | \ 222 FTSDMC021_TP1_TCL(2)) 223 224 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 225 FTSDMC021_TP2_INI_REFT(8) | \ 226 FTSDMC021_TP2_REF_INTV(0x180)) 227 228 /* 229 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 230 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 231 * C language. 232 */ 233 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 234 FTSDMC021_CR1_DSZ(3) | \ 235 FTSDMC021_CR1_MBW(2) | \ 236 FTSDMC021_CR1_BNKSIZE(6)) 237 238 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 239 FTSDMC021_CR2_IREF | \ 240 FTSDMC021_CR2_ISMR) 241 242 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 243 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 244 CONFIG_SYS_FTSDMC021_BANK0_BASE) 245 246 #endif 247 248 /* 249 * Physical Memory Map 250 */ 251 #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT) 252 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 253 #if defined(CONFIG_MEM_REMAP) 254 #define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/ 255 #endif 256 #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ 257 #define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */ 258 #endif 259 260 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 261 #define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */ 262 263 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 264 265 #ifdef CONFIG_MEM_REMAP 266 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 267 GENERATED_GBL_DATA_SIZE) 268 #else 269 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 270 GENERATED_GBL_DATA_SIZE) 271 #endif /* CONFIG_MEM_REMAP */ 272 273 /* 274 * Load address and memory test area should agree with 275 * arch/nds32/config.mk. Be careful not to overwrite U-boot itself. 276 */ 277 #define CONFIG_SYS_LOAD_ADDR 0x300000 278 279 /* memtest works on 63 MB in DRAM */ 280 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 281 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 282 283 /* 284 * Static memory controller configuration 285 */ 286 #define CONFIG_FTSMC020 287 288 #ifdef CONFIG_FTSMC020 289 #include <faraday/ftsmc020.h> 290 291 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 292 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 293 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 294 } 295 296 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 297 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 298 FTSMC020_BANK_SIZE_32M | \ 299 FTSMC020_BANK_MBW_32) 300 301 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 302 FTSMC020_TPR_AST(1) | \ 303 FTSMC020_TPR_CTW(1) | \ 304 FTSMC020_TPR_ATI(1) | \ 305 FTSMC020_TPR_AT2(1) | \ 306 FTSMC020_TPR_WTC(1) | \ 307 FTSMC020_TPR_AHT(1) | \ 308 FTSMC020_TPR_TRNA(1)) 309 #endif 310 311 /* 312 * FLASH on ADP_AG101P is connected to BANK0 313 * Just disalbe the other BANK to avoid detection error. 314 */ 315 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 316 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 317 FTSMC020_BANK_SIZE_32M | \ 318 FTSMC020_BANK_MBW_32) 319 320 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 321 FTSMC020_TPR_CTW(3) | \ 322 FTSMC020_TPR_ATI(0xf) | \ 323 FTSMC020_TPR_AT2(3) | \ 324 FTSMC020_TPR_WTC(3) | \ 325 FTSMC020_TPR_AHT(3) | \ 326 FTSMC020_TPR_TRNA(0xf)) 327 328 #define FTSMC020_BANK1_CONFIG (0x00) 329 #define FTSMC020_BANK1_TIMING (0x00) 330 #endif /* CONFIG_FTSMC020 */ 331 332 /* 333 * FLASH and environment organization 334 */ 335 /* use CFI framework */ 336 #define CONFIG_SYS_FLASH_CFI 337 #define CONFIG_FLASH_CFI_DRIVER 338 339 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 340 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 341 342 /* support JEDEC */ 343 344 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 345 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 346 #define PHYS_FLASH_1 0x80400000 /* BANK 1 */ 347 #else /* !CONFIG_SKIP_LOWLEVEL_INIT */ 348 #ifdef CONFIG_MEM_REMAP 349 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 350 #else 351 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 352 #endif /* CONFIG_MEM_REMAP */ 353 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 354 355 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 356 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 357 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 358 359 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 360 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 361 362 /* max number of memory banks */ 363 /* 364 * There are 4 banks supported for this Controller, 365 * but we have only 1 bank connected to flash on board 366 */ 367 #define CONFIG_SYS_MAX_FLASH_BANKS 1 368 369 /* max number of sectors on one chip */ 370 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2) 371 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 372 #define CONFIG_SYS_MAX_FLASH_SECT 128 373 374 /* environments */ 375 #define CONFIG_ENV_IS_IN_FLASH 376 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 377 #define CONFIG_ENV_SIZE 8192 378 #define CONFIG_ENV_OVERWRITE 379 380 #endif /* __CONFIG_H */ 381