1 /* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch-ag101/ag101.h> 13 14 /* 15 * CPU and Board Configuration Options 16 */ 17 #define CONFIG_ADP_AG101P 18 19 #define CONFIG_USE_INTERRUPT 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 23 #define CONFIG_CMDLINE_EDITING 24 25 #define CONFIG_SYS_ICACHE_OFF 26 #define CONFIG_SYS_DCACHE_OFF 27 28 #define CONFIG_BOOTP_SEND_HOSTNAME 29 #define CONFIG_BOOTP_SERVERIP 30 31 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 32 #define CONFIG_MEM_REMAP 33 #endif 34 35 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 36 #define CONFIG_SYS_TEXT_BASE 0x00500000 37 #ifdef CONFIG_OF_CONTROL 38 #undef CONFIG_OF_SEPARATE 39 #define CONFIG_OF_EMBED 40 #endif 41 #else 42 #ifdef CONFIG_MEM_REMAP 43 #define CONFIG_SYS_TEXT_BASE 0x80000000 44 #else 45 #define CONFIG_SYS_TEXT_BASE 0x00000000 46 #endif 47 #endif 48 49 /* 50 * Timer 51 */ 52 #define CONFIG_SYS_CLK_FREQ 39062500 53 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 54 55 /* 56 * Use Externel CLOCK or PCLK 57 */ 58 #undef CONFIG_FTRTC010_EXTCLK 59 60 #ifndef CONFIG_FTRTC010_EXTCLK 61 #define CONFIG_FTRTC010_PCLK 62 #endif 63 64 #ifdef CONFIG_FTRTC010_EXTCLK 65 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 66 #else 67 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 68 #endif 69 70 #define TIMER_LOAD_VAL 0xffffffff 71 72 /* 73 * Real Time Clock 74 */ 75 #define CONFIG_RTC_FTRTC010 76 77 /* 78 * Real Time Clock Divider 79 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 80 */ 81 #define OSC_5MHZ (5*1000000) 82 #define OSC_CLK (4*OSC_5MHZ) 83 #define RTC_DIV_COUNT (0.5) /* Why?? */ 84 85 /* 86 * Serial console configuration 87 */ 88 89 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 90 #define CONFIG_CONS_INDEX 1 91 #define CONFIG_SYS_NS16550_SERIAL 92 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 93 #ifndef CONFIG_DM_SERIAL 94 #define CONFIG_SYS_NS16550_REG_SIZE -4 95 #endif 96 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 97 98 /* 99 * SD (MMC) controller 100 */ 101 #define CONFIG_FTSDC010 102 #define CONFIG_FTSDC010_NUMBER 1 103 #define CONFIG_FTSDC010_SDIO 104 105 /* 106 * Miscellaneous configurable options 107 */ 108 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 109 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 110 111 /* Print Buffer Size */ 112 #define CONFIG_SYS_PBSIZE \ 113 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 114 115 /* max number of command args */ 116 #define CONFIG_SYS_MAXARGS 16 117 118 /* Boot Argument Buffer Size */ 119 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 120 121 /* 122 * Size of malloc() pool 123 */ 124 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 125 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 126 127 /* 128 * AHB Controller configuration 129 */ 130 #define CONFIG_FTAHBC020S 131 132 #ifdef CONFIG_FTAHBC020S 133 #include <faraday/ftahbc020s.h> 134 135 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 136 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 137 138 /* 139 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 140 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 141 * in C language. 142 */ 143 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 144 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 145 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 146 #endif 147 148 /* 149 * Watchdog 150 */ 151 #define CONFIG_FTWDT010_WATCHDOG 152 153 /* 154 * PMU Power controller configuration 155 */ 156 #define CONFIG_PMU 157 #define CONFIG_FTPMU010_POWER 158 159 #ifdef CONFIG_FTPMU010_POWER 160 #include <faraday/ftpmu010.h> 161 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 162 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 163 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 164 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 165 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 166 FTPMU010_SDRAMHTC_CKE_DCSR | \ 167 FTPMU010_SDRAMHTC_DQM_DCSR | \ 168 FTPMU010_SDRAMHTC_SDCLK_DCSR) 169 #endif 170 171 /* 172 * SDRAM controller configuration 173 */ 174 #define CONFIG_FTSDMC021 175 176 #ifdef CONFIG_FTSDMC021 177 #include <faraday/ftsdmc021.h> 178 179 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 180 FTSDMC021_TP1_TRP(1) | \ 181 FTSDMC021_TP1_TRCD(1) | \ 182 FTSDMC021_TP1_TRF(3) | \ 183 FTSDMC021_TP1_TWR(1) | \ 184 FTSDMC021_TP1_TCL(2)) 185 186 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 187 FTSDMC021_TP2_INI_REFT(8) | \ 188 FTSDMC021_TP2_REF_INTV(0x180)) 189 190 /* 191 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 192 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 193 * C language. 194 */ 195 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 196 FTSDMC021_CR1_DSZ(3) | \ 197 FTSDMC021_CR1_MBW(2) | \ 198 FTSDMC021_CR1_BNKSIZE(6)) 199 200 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 201 FTSDMC021_CR2_IREF | \ 202 FTSDMC021_CR2_ISMR) 203 204 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 205 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 206 CONFIG_SYS_FTSDMC021_BANK0_BASE) 207 208 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 209 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 210 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 211 CONFIG_SYS_FTSDMC021_BANK1_BASE) 212 #endif 213 214 /* 215 * Physical Memory Map 216 */ 217 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 218 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 219 #else 220 #ifdef CONFIG_MEM_REMAP 221 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 222 #else 223 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ 224 #endif 225 #endif 226 227 #define PHYS_SDRAM_1 \ 228 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 229 230 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 231 232 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 233 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 234 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 235 #else 236 #ifdef CONFIG_MEM_REMAP 237 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 238 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 239 #else 240 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ 241 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 242 #endif 243 #endif 244 245 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 246 247 #ifdef CONFIG_MEM_REMAP 248 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 249 GENERATED_GBL_DATA_SIZE) 250 #else 251 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 252 GENERATED_GBL_DATA_SIZE) 253 #endif /* CONFIG_MEM_REMAP */ 254 255 /* 256 * Load address and memory test area should agree with 257 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 258 */ 259 #define CONFIG_SYS_LOAD_ADDR 0x300000 260 261 /* memtest works on 63 MB in DRAM */ 262 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 263 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 264 265 /* 266 * Static memory controller configuration 267 */ 268 #define CONFIG_FTSMC020 269 270 #ifdef CONFIG_FTSMC020 271 #include <faraday/ftsmc020.h> 272 273 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 274 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 275 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 276 } 277 278 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 279 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 280 FTSMC020_BANK_SIZE_32M | \ 281 FTSMC020_BANK_MBW_32) 282 283 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 284 FTSMC020_TPR_AST(1) | \ 285 FTSMC020_TPR_CTW(1) | \ 286 FTSMC020_TPR_ATI(1) | \ 287 FTSMC020_TPR_AT2(1) | \ 288 FTSMC020_TPR_WTC(1) | \ 289 FTSMC020_TPR_AHT(1) | \ 290 FTSMC020_TPR_TRNA(1)) 291 #endif 292 293 /* 294 * FLASH on ADP_AG101P is connected to BANK0 295 * Just disalbe the other BANK to avoid detection error. 296 */ 297 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 298 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 299 FTSMC020_BANK_SIZE_32M | \ 300 FTSMC020_BANK_MBW_32) 301 302 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 303 FTSMC020_TPR_CTW(3) | \ 304 FTSMC020_TPR_ATI(0xf) | \ 305 FTSMC020_TPR_AT2(3) | \ 306 FTSMC020_TPR_WTC(3) | \ 307 FTSMC020_TPR_AHT(3) | \ 308 FTSMC020_TPR_TRNA(0xf)) 309 310 #define FTSMC020_BANK1_CONFIG (0x00) 311 #define FTSMC020_BANK1_TIMING (0x00) 312 #endif /* CONFIG_FTSMC020 */ 313 314 /* 315 * FLASH and environment organization 316 */ 317 /* use CFI framework */ 318 #define CONFIG_SYS_FLASH_CFI 319 #define CONFIG_FLASH_CFI_DRIVER 320 321 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 322 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 323 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 324 325 /* support JEDEC */ 326 327 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 328 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 329 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 330 #else 331 #ifdef CONFIG_MEM_REMAP 332 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 333 #else 334 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 335 #endif 336 #endif /* CONFIG_MEM_REMAP */ 337 338 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 339 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 340 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 341 342 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 343 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 344 345 /* max number of memory banks */ 346 /* 347 * There are 4 banks supported for this Controller, 348 * but we have only 1 bank connected to flash on board 349 */ 350 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 351 #define CONFIG_SYS_MAX_FLASH_BANKS 1 352 #endif 353 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 354 355 /* max number of sectors on one chip */ 356 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 357 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 358 #define CONFIG_SYS_MAX_FLASH_SECT 512 359 360 /* environments */ 361 #define CONFIG_ENV_IS_IN_FLASH 362 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 363 #define CONFIG_ENV_SIZE 8192 364 #define CONFIG_ENV_OVERWRITE 365 366 /* 367 * For booting Linux, the board info and command line data 368 * have to be in the first 16 MB of memory, since this is 369 * the maximum mapped by the Linux kernel during initialization. 370 */ 371 372 /* Initial Memory map for Linux*/ 373 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) 374 /* Increase max gunzip size */ 375 #define CONFIG_SYS_BOOTM_LEN (64 << 20) 376 377 #endif /* __CONFIG_H */ 378