1 /* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch-ag101/ag101.h> 13 14 /* 15 * CPU and Board Configuration Options 16 */ 17 #define CONFIG_USE_INTERRUPT 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 21 #define CONFIG_ARCH_MAP_SYSMEM 22 23 #define CONFIG_BOOTP_SEND_HOSTNAME 24 #define CONFIG_BOOTP_SERVERIP 25 26 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 27 #define CONFIG_MEM_REMAP 28 #endif 29 30 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 31 #ifdef CONFIG_OF_CONTROL 32 #undef CONFIG_OF_SEPARATE 33 #define CONFIG_OF_EMBED 34 #endif 35 #endif 36 37 /* 38 * Timer 39 */ 40 #define CONFIG_SYS_CLK_FREQ 39062500 41 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 42 43 /* 44 * Use Externel CLOCK or PCLK 45 */ 46 #undef CONFIG_FTRTC010_EXTCLK 47 48 #ifndef CONFIG_FTRTC010_EXTCLK 49 #define CONFIG_FTRTC010_PCLK 50 #endif 51 52 #ifdef CONFIG_FTRTC010_EXTCLK 53 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 54 #else 55 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 56 #endif 57 58 #define TIMER_LOAD_VAL 0xffffffff 59 60 /* 61 * Real Time Clock 62 */ 63 #define CONFIG_RTC_FTRTC010 64 65 /* 66 * Real Time Clock Divider 67 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 68 */ 69 #define OSC_5MHZ (5*1000000) 70 #define OSC_CLK (4*OSC_5MHZ) 71 #define RTC_DIV_COUNT (0.5) /* Why?? */ 72 73 /* 74 * Serial console configuration 75 */ 76 77 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 78 #define CONFIG_SYS_NS16550_SERIAL 79 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 80 #ifndef CONFIG_DM_SERIAL 81 #define CONFIG_SYS_NS16550_REG_SIZE -4 82 #endif 83 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 84 85 /* 86 * SD (MMC) controller 87 */ 88 #define CONFIG_FTSDC010_NUMBER 1 89 #define CONFIG_FTSDC010_SDIO 90 91 /* 92 * Miscellaneous configurable options 93 */ 94 95 /* 96 * Size of malloc() pool 97 */ 98 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 99 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 100 101 /* 102 * AHB Controller configuration 103 */ 104 #define CONFIG_FTAHBC020S 105 106 #ifdef CONFIG_FTAHBC020S 107 #include <faraday/ftahbc020s.h> 108 109 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 110 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 111 112 /* 113 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 114 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 115 * in C language. 116 */ 117 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 118 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 119 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 120 #endif 121 122 /* 123 * Watchdog 124 */ 125 #define CONFIG_FTWDT010_WATCHDOG 126 127 /* 128 * PMU Power controller configuration 129 */ 130 #define CONFIG_PMU 131 #define CONFIG_FTPMU010_POWER 132 133 #ifdef CONFIG_FTPMU010_POWER 134 #include <faraday/ftpmu010.h> 135 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 136 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 137 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 138 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 139 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 140 FTPMU010_SDRAMHTC_CKE_DCSR | \ 141 FTPMU010_SDRAMHTC_DQM_DCSR | \ 142 FTPMU010_SDRAMHTC_SDCLK_DCSR) 143 #endif 144 145 /* 146 * SDRAM controller configuration 147 */ 148 #define CONFIG_FTSDMC021 149 150 #ifdef CONFIG_FTSDMC021 151 #include <faraday/ftsdmc021.h> 152 153 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 154 FTSDMC021_TP1_TRP(1) | \ 155 FTSDMC021_TP1_TRCD(1) | \ 156 FTSDMC021_TP1_TRF(3) | \ 157 FTSDMC021_TP1_TWR(1) | \ 158 FTSDMC021_TP1_TCL(2)) 159 160 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 161 FTSDMC021_TP2_INI_REFT(8) | \ 162 FTSDMC021_TP2_REF_INTV(0x180)) 163 164 /* 165 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 166 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 167 * C language. 168 */ 169 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 170 FTSDMC021_CR1_DSZ(3) | \ 171 FTSDMC021_CR1_MBW(2) | \ 172 FTSDMC021_CR1_BNKSIZE(6)) 173 174 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 175 FTSDMC021_CR2_IREF | \ 176 FTSDMC021_CR2_ISMR) 177 178 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 179 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 180 CONFIG_SYS_FTSDMC021_BANK0_BASE) 181 182 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 183 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 184 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 185 CONFIG_SYS_FTSDMC021_BANK1_BASE) 186 #endif 187 188 /* 189 * Physical Memory Map 190 */ 191 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 192 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 193 #else 194 #ifdef CONFIG_MEM_REMAP 195 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 196 #else 197 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ 198 #endif 199 #endif 200 201 #define PHYS_SDRAM_1 \ 202 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 203 204 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 205 206 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 207 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 208 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 209 #else 210 #ifdef CONFIG_MEM_REMAP 211 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 212 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 213 #else 214 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ 215 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 216 #endif 217 #endif 218 219 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 220 221 #ifdef CONFIG_MEM_REMAP 222 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 223 GENERATED_GBL_DATA_SIZE) 224 #else 225 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 226 GENERATED_GBL_DATA_SIZE) 227 #endif /* CONFIG_MEM_REMAP */ 228 229 /* 230 * Load address and memory test area should agree with 231 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 232 */ 233 #define CONFIG_SYS_LOAD_ADDR 0x300000 234 235 /* memtest works on 63 MB in DRAM */ 236 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 237 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 238 239 /* 240 * Static memory controller configuration 241 */ 242 #define CONFIG_FTSMC020 243 244 #ifdef CONFIG_FTSMC020 245 #include <faraday/ftsmc020.h> 246 247 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 248 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 249 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 250 } 251 252 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 253 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 254 FTSMC020_BANK_SIZE_32M | \ 255 FTSMC020_BANK_MBW_32) 256 257 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 258 FTSMC020_TPR_AST(1) | \ 259 FTSMC020_TPR_CTW(1) | \ 260 FTSMC020_TPR_ATI(1) | \ 261 FTSMC020_TPR_AT2(1) | \ 262 FTSMC020_TPR_WTC(1) | \ 263 FTSMC020_TPR_AHT(1) | \ 264 FTSMC020_TPR_TRNA(1)) 265 #endif 266 267 /* 268 * FLASH on ADP_AG101P is connected to BANK0 269 * Just disalbe the other BANK to avoid detection error. 270 */ 271 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 272 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 273 FTSMC020_BANK_SIZE_32M | \ 274 FTSMC020_BANK_MBW_32) 275 276 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 277 FTSMC020_TPR_CTW(3) | \ 278 FTSMC020_TPR_ATI(0xf) | \ 279 FTSMC020_TPR_AT2(3) | \ 280 FTSMC020_TPR_WTC(3) | \ 281 FTSMC020_TPR_AHT(3) | \ 282 FTSMC020_TPR_TRNA(0xf)) 283 284 #define FTSMC020_BANK1_CONFIG (0x00) 285 #define FTSMC020_BANK1_TIMING (0x00) 286 #endif /* CONFIG_FTSMC020 */ 287 288 /* 289 * FLASH and environment organization 290 */ 291 /* use CFI framework */ 292 #define CONFIG_SYS_FLASH_CFI 293 #define CONFIG_FLASH_CFI_DRIVER 294 295 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 296 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 297 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 298 299 /* support JEDEC */ 300 301 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 302 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 303 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 304 #else 305 #ifdef CONFIG_MEM_REMAP 306 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 307 #else 308 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 309 #endif 310 #endif /* CONFIG_MEM_REMAP */ 311 312 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 313 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 314 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 315 316 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 317 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 318 319 /* max number of memory banks */ 320 /* 321 * There are 4 banks supported for this Controller, 322 * but we have only 1 bank connected to flash on board 323 */ 324 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 325 #define CONFIG_SYS_MAX_FLASH_BANKS 1 326 #endif 327 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 328 329 /* max number of sectors on one chip */ 330 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 331 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 332 #define CONFIG_SYS_MAX_FLASH_SECT 512 333 334 /* environments */ 335 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 336 #define CONFIG_ENV_SIZE 8192 337 #define CONFIG_ENV_OVERWRITE 338 339 /* 340 * For booting Linux, the board info and command line data 341 * have to be in the first 16 MB of memory, since this is 342 * the maximum mapped by the Linux kernel during initialization. 343 */ 344 345 /* Initial Memory map for Linux*/ 346 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) 347 /* Increase max gunzip size */ 348 #define CONFIG_SYS_BOOTM_LEN (64 << 20) 349 350 #endif /* __CONFIG_H */ 351