1 /* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 #ifndef __CONFIG_H 25 #define __CONFIG_H 26 27 #include <asm/arch/ag101.h> 28 29 /* 30 * CPU and Board Configuration Options 31 */ 32 #define CONFIG_ADP_AG101P 33 34 #define CONFIG_USE_INTERRUPT 35 36 #define CONFIG_SKIP_LOWLEVEL_INIT 37 38 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 39 #define CONFIG_MEM_REMAP 40 #endif 41 42 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 43 #define CONFIG_SYS_TEXT_BASE 0x03200000 44 #else 45 #define CONFIG_SYS_TEXT_BASE 0x00000000 46 #endif 47 48 /* 49 * Timer 50 */ 51 52 /* 53 * According to the discussion in u-boot mailing list before, 54 * CONFIG_SYS_HZ at 1000 is mandatory. 55 */ 56 #define CONFIG_SYS_HZ 1000 57 #define CONFIG_SYS_CLK_FREQ 39062500 58 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 59 60 /* 61 * Use Externel CLOCK or PCLK 62 */ 63 #undef CONFIG_FTRTC010_EXTCLK 64 65 #ifndef CONFIG_FTRTC010_EXTCLK 66 #define CONFIG_FTRTC010_PCLK 67 #endif 68 69 #ifdef CONFIG_FTRTC010_EXTCLK 70 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 71 #else 72 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 73 #endif 74 75 #define TIMER_LOAD_VAL 0xffffffff 76 77 /* 78 * Real Time Clock 79 */ 80 #define CONFIG_RTC_FTRTC010 81 82 /* 83 * Real Time Clock Divider 84 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 85 */ 86 #define OSC_5MHZ (5*1000000) 87 #define OSC_CLK (4*OSC_5MHZ) 88 #define RTC_DIV_COUNT (0.5) /* Why?? */ 89 90 /* 91 * Serial console configuration 92 */ 93 94 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 95 #define CONFIG_BAUDRATE 38400 96 #define CONFIG_CONS_INDEX 1 97 #define CONFIG_SYS_NS16550 98 #define CONFIG_SYS_NS16550_SERIAL 99 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 100 #define CONFIG_SYS_NS16550_REG_SIZE -4 101 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 102 103 /* valid baudrates */ 104 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 105 106 /* 107 * Ethernet 108 */ 109 #define CONFIG_FTMAC100 110 111 #define CONFIG_BOOTDELAY 3 112 113 /* 114 * SD (MMC) controller 115 */ 116 #define CONFIG_MMC 117 #define CONFIG_CMD_MMC 118 #define CONFIG_GENERIC_MMC 119 #define CONFIG_DOS_PARTITION 120 #define CONFIG_FTSDC010 121 #define CONFIG_FTSDC010_NUMBER 1 122 #define CONFIG_CMD_FAT 123 124 /* 125 * Command line configuration. 126 */ 127 #include <config_cmd_default.h> 128 129 #define CONFIG_CMD_CACHE 130 #define CONFIG_CMD_DATE 131 #define CONFIG_CMD_PING 132 133 /* 134 * Miscellaneous configurable options 135 */ 136 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 137 #define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */ 138 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 139 140 /* Print Buffer Size */ 141 #define CONFIG_SYS_PBSIZE \ 142 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 143 144 /* max number of command args */ 145 #define CONFIG_SYS_MAXARGS 16 146 147 /* Boot Argument Buffer Size */ 148 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 149 150 /* 151 * Stack sizes 152 * 153 * The stack sizes are set up in start.S using the settings below 154 */ 155 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ 156 157 /* 158 * Size of malloc() pool 159 */ 160 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 161 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 162 163 /* 164 * size in bytes reserved for initial data 165 */ 166 #define CONFIG_SYS_GBL_DATA_SIZE 128 167 168 /* 169 * AHB Controller configuration 170 */ 171 #define CONFIG_FTAHBC020S 172 173 #ifdef CONFIG_FTAHBC020S 174 #include <faraday/ftahbc020s.h> 175 176 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 177 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 178 179 /* 180 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 181 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 182 * in C language. 183 */ 184 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 185 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 186 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 187 #endif 188 189 /* 190 * Watchdog 191 */ 192 #define CONFIG_FTWDT010_WATCHDOG 193 194 /* 195 * PMU Power controller configuration 196 */ 197 #define CONFIG_PMU 198 #define CONFIG_FTPMU010_POWER 199 200 #ifdef CONFIG_FTPMU010_POWER 201 #include <faraday/ftpmu010.h> 202 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 203 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 204 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 205 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 206 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 207 FTPMU010_SDRAMHTC_CKE_DCSR | \ 208 FTPMU010_SDRAMHTC_DQM_DCSR | \ 209 FTPMU010_SDRAMHTC_SDCLK_DCSR) 210 #endif 211 212 /* 213 * SDRAM controller configuration 214 */ 215 #define CONFIG_FTSDMC021 216 217 #ifdef CONFIG_FTSDMC021 218 #include <faraday/ftsdmc021.h> 219 220 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 221 FTSDMC021_TP1_TRP(1) | \ 222 FTSDMC021_TP1_TRCD(1) | \ 223 FTSDMC021_TP1_TRF(3) | \ 224 FTSDMC021_TP1_TWR(1) | \ 225 FTSDMC021_TP1_TCL(2)) 226 227 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 228 FTSDMC021_TP2_INI_REFT(8) | \ 229 FTSDMC021_TP2_REF_INTV(0x180)) 230 231 /* 232 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 233 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 234 * C language. 235 */ 236 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 237 FTSDMC021_CR1_DSZ(3) | \ 238 FTSDMC021_CR1_MBW(2) | \ 239 FTSDMC021_CR1_BNKSIZE(6)) 240 241 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 242 FTSDMC021_CR2_IREF | \ 243 FTSDMC021_CR2_ISMR) 244 245 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 246 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 247 CONFIG_SYS_FTSDMC021_BANK0_BASE) 248 249 #endif 250 251 /* 252 * Physical Memory Map 253 */ 254 #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT) 255 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 256 #if defined(CONFIG_MEM_REMAP) 257 #define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/ 258 #endif 259 #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ 260 #define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */ 261 #endif 262 263 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 264 #define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */ 265 266 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 267 268 #ifdef CONFIG_MEM_REMAP 269 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 270 GENERATED_GBL_DATA_SIZE) 271 #else 272 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 273 GENERATED_GBL_DATA_SIZE) 274 #endif /* CONFIG_MEM_REMAP */ 275 276 /* 277 * Load address and memory test area should agree with 278 * arch/nds32/config.mk. Be careful not to overwrite U-boot itself. 279 */ 280 #define CONFIG_SYS_LOAD_ADDR 0x300000 281 282 /* memtest works on 63 MB in DRAM */ 283 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 284 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 285 286 /* 287 * Static memory controller configuration 288 */ 289 #define CONFIG_FTSMC020 290 291 #ifdef CONFIG_FTSMC020 292 #include <faraday/ftsmc020.h> 293 294 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 295 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 296 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 297 } 298 299 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 300 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 301 FTSMC020_BANK_SIZE_32M | \ 302 FTSMC020_BANK_MBW_32) 303 304 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 305 FTSMC020_TPR_AST(1) | \ 306 FTSMC020_TPR_CTW(1) | \ 307 FTSMC020_TPR_ATI(1) | \ 308 FTSMC020_TPR_AT2(1) | \ 309 FTSMC020_TPR_WTC(1) | \ 310 FTSMC020_TPR_AHT(1) | \ 311 FTSMC020_TPR_TRNA(1)) 312 #endif 313 314 /* 315 * FLASH on ADP_AG101P is connected to BANK0 316 * Just disalbe the other BANK to avoid detection error. 317 */ 318 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 319 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 320 FTSMC020_BANK_SIZE_32M | \ 321 FTSMC020_BANK_MBW_32) 322 323 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 324 FTSMC020_TPR_CTW(3) | \ 325 FTSMC020_TPR_ATI(0xf) | \ 326 FTSMC020_TPR_AT2(3) | \ 327 FTSMC020_TPR_WTC(3) | \ 328 FTSMC020_TPR_AHT(3) | \ 329 FTSMC020_TPR_TRNA(0xf)) 330 331 #define FTSMC020_BANK1_CONFIG (0x00) 332 #define FTSMC020_BANK1_TIMING (0x00) 333 #endif /* CONFIG_FTSMC020 */ 334 335 /* 336 * FLASH and environment organization 337 */ 338 /* use CFI framework */ 339 #define CONFIG_SYS_FLASH_CFI 340 #define CONFIG_FLASH_CFI_DRIVER 341 342 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 343 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 344 345 /* support JEDEC */ 346 347 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 348 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 349 #define PHYS_FLASH_1 0x80400000 /* BANK 1 */ 350 #else /* !CONFIG_SKIP_LOWLEVEL_INIT */ 351 #ifdef CONFIG_MEM_REMAP 352 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 353 #else 354 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 355 #endif /* CONFIG_MEM_REMAP */ 356 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 357 358 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 359 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 360 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 361 362 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 363 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 364 365 /* max number of memory banks */ 366 /* 367 * There are 4 banks supported for this Controller, 368 * but we have only 1 bank connected to flash on board 369 */ 370 #define CONFIG_SYS_MAX_FLASH_BANKS 1 371 372 /* max number of sectors on one chip */ 373 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2) 374 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 375 #define CONFIG_SYS_MAX_FLASH_SECT 128 376 377 /* environments */ 378 #define CONFIG_ENV_IS_IN_FLASH 379 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 380 #define CONFIG_ENV_SIZE 8192 381 #define CONFIG_ENV_OVERWRITE 382 383 #endif /* __CONFIG_H */ 384