1 /* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch-ag101/ag101.h> 13 14 /* 15 * CPU and Board Configuration Options 16 */ 17 #define CONFIG_ADP_AG101P 18 19 #define CONFIG_USE_INTERRUPT 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 23 #define CONFIG_SYS_GENERIC_GLOBAL_DATA 24 25 /* 26 * Definitions related to passing arguments to kernel. 27 */ 28 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ 29 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ 30 #define CONFIG_INITRD_TAG /* send initrd params */ 31 32 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 33 #define CONFIG_MEM_REMAP 34 #endif 35 36 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 37 #define CONFIG_SYS_TEXT_BASE 0x00500000 38 #else 39 #ifdef CONFIG_MEM_REMAP 40 #define CONFIG_SYS_TEXT_BASE 0x80000000 41 #else 42 #define CONFIG_SYS_TEXT_BASE 0x00000000 43 #endif 44 #endif 45 46 /* 47 * Timer 48 */ 49 #define CONFIG_SYS_CLK_FREQ 39062500 50 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 51 52 /* 53 * Use Externel CLOCK or PCLK 54 */ 55 #undef CONFIG_FTRTC010_EXTCLK 56 57 #ifndef CONFIG_FTRTC010_EXTCLK 58 #define CONFIG_FTRTC010_PCLK 59 #endif 60 61 #ifdef CONFIG_FTRTC010_EXTCLK 62 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 63 #else 64 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 65 #endif 66 67 #define TIMER_LOAD_VAL 0xffffffff 68 69 /* 70 * Real Time Clock 71 */ 72 #define CONFIG_RTC_FTRTC010 73 74 /* 75 * Real Time Clock Divider 76 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 77 */ 78 #define OSC_5MHZ (5*1000000) 79 #define OSC_CLK (4*OSC_5MHZ) 80 #define RTC_DIV_COUNT (0.5) /* Why?? */ 81 82 /* 83 * Serial console configuration 84 */ 85 86 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 87 #define CONFIG_BAUDRATE 38400 88 #define CONFIG_CONS_INDEX 1 89 #define CONFIG_SYS_NS16550_SERIAL 90 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 91 #define CONFIG_SYS_NS16550_REG_SIZE -4 92 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 93 94 /* 95 * Ethernet 96 */ 97 #define CONFIG_FTMAC100 98 99 100 /* 101 * SD (MMC) controller 102 */ 103 #define CONFIG_FTSDC010 104 #define CONFIG_FTSDC010_NUMBER 1 105 #define CONFIG_FTSDC010_SDIO 106 107 /* 108 * Command line configuration. 109 */ 110 #define CONFIG_CMD_DATE 111 112 /* 113 * Miscellaneous configurable options 114 */ 115 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 116 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 117 118 /* Print Buffer Size */ 119 #define CONFIG_SYS_PBSIZE \ 120 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 121 122 /* max number of command args */ 123 #define CONFIG_SYS_MAXARGS 16 124 125 /* Boot Argument Buffer Size */ 126 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 127 128 /* 129 * Size of malloc() pool 130 */ 131 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 132 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 133 134 /* 135 * AHB Controller configuration 136 */ 137 #define CONFIG_FTAHBC020S 138 139 #ifdef CONFIG_FTAHBC020S 140 #include <faraday/ftahbc020s.h> 141 142 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 143 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 144 145 /* 146 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 147 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 148 * in C language. 149 */ 150 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 151 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 152 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 153 #endif 154 155 /* 156 * Watchdog 157 */ 158 #define CONFIG_FTWDT010_WATCHDOG 159 160 /* 161 * PMU Power controller configuration 162 */ 163 #define CONFIG_PMU 164 #define CONFIG_FTPMU010_POWER 165 166 #ifdef CONFIG_FTPMU010_POWER 167 #include <faraday/ftpmu010.h> 168 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 169 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 170 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 171 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 172 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 173 FTPMU010_SDRAMHTC_CKE_DCSR | \ 174 FTPMU010_SDRAMHTC_DQM_DCSR | \ 175 FTPMU010_SDRAMHTC_SDCLK_DCSR) 176 #endif 177 178 /* 179 * SDRAM controller configuration 180 */ 181 #define CONFIG_FTSDMC021 182 183 #ifdef CONFIG_FTSDMC021 184 #include <faraday/ftsdmc021.h> 185 186 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 187 FTSDMC021_TP1_TRP(1) | \ 188 FTSDMC021_TP1_TRCD(1) | \ 189 FTSDMC021_TP1_TRF(3) | \ 190 FTSDMC021_TP1_TWR(1) | \ 191 FTSDMC021_TP1_TCL(2)) 192 193 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 194 FTSDMC021_TP2_INI_REFT(8) | \ 195 FTSDMC021_TP2_REF_INTV(0x180)) 196 197 /* 198 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 199 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 200 * C language. 201 */ 202 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 203 FTSDMC021_CR1_DSZ(3) | \ 204 FTSDMC021_CR1_MBW(2) | \ 205 FTSDMC021_CR1_BNKSIZE(6)) 206 207 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 208 FTSDMC021_CR2_IREF | \ 209 FTSDMC021_CR2_ISMR) 210 211 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 212 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 213 CONFIG_SYS_FTSDMC021_BANK0_BASE) 214 215 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 216 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 217 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 218 CONFIG_SYS_FTSDMC021_BANK1_BASE) 219 #endif 220 221 /* 222 * Physical Memory Map 223 */ 224 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 225 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 226 #else 227 #ifdef CONFIG_MEM_REMAP 228 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 229 #else 230 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ 231 #endif 232 #endif 233 234 #define PHYS_SDRAM_1 \ 235 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 236 237 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 238 239 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 240 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 241 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 242 #else 243 #ifdef CONFIG_MEM_REMAP 244 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 245 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 246 #else 247 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ 248 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 249 #endif 250 #endif 251 252 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 253 254 #ifdef CONFIG_MEM_REMAP 255 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 256 GENERATED_GBL_DATA_SIZE) 257 #else 258 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 259 GENERATED_GBL_DATA_SIZE) 260 #endif /* CONFIG_MEM_REMAP */ 261 262 /* 263 * Load address and memory test area should agree with 264 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 265 */ 266 #define CONFIG_SYS_LOAD_ADDR 0x300000 267 268 /* memtest works on 63 MB in DRAM */ 269 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 270 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 271 272 /* 273 * Static memory controller configuration 274 */ 275 #define CONFIG_FTSMC020 276 277 #ifdef CONFIG_FTSMC020 278 #include <faraday/ftsmc020.h> 279 280 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 281 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 282 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 283 } 284 285 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 286 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 287 FTSMC020_BANK_SIZE_32M | \ 288 FTSMC020_BANK_MBW_32) 289 290 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 291 FTSMC020_TPR_AST(1) | \ 292 FTSMC020_TPR_CTW(1) | \ 293 FTSMC020_TPR_ATI(1) | \ 294 FTSMC020_TPR_AT2(1) | \ 295 FTSMC020_TPR_WTC(1) | \ 296 FTSMC020_TPR_AHT(1) | \ 297 FTSMC020_TPR_TRNA(1)) 298 #endif 299 300 /* 301 * FLASH on ADP_AG101P is connected to BANK0 302 * Just disalbe the other BANK to avoid detection error. 303 */ 304 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 305 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 306 FTSMC020_BANK_SIZE_32M | \ 307 FTSMC020_BANK_MBW_32) 308 309 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 310 FTSMC020_TPR_CTW(3) | \ 311 FTSMC020_TPR_ATI(0xf) | \ 312 FTSMC020_TPR_AT2(3) | \ 313 FTSMC020_TPR_WTC(3) | \ 314 FTSMC020_TPR_AHT(3) | \ 315 FTSMC020_TPR_TRNA(0xf)) 316 317 #define FTSMC020_BANK1_CONFIG (0x00) 318 #define FTSMC020_BANK1_TIMING (0x00) 319 #endif /* CONFIG_FTSMC020 */ 320 321 /* 322 * FLASH and environment organization 323 */ 324 /* use CFI framework */ 325 #define CONFIG_SYS_FLASH_CFI 326 #define CONFIG_FLASH_CFI_DRIVER 327 328 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 329 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 330 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 331 332 /* support JEDEC */ 333 334 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 335 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 336 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 337 #else 338 #ifdef CONFIG_MEM_REMAP 339 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 340 #else 341 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 342 #endif 343 #endif /* CONFIG_MEM_REMAP */ 344 345 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 346 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 347 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 348 349 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 350 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 351 352 /* max number of memory banks */ 353 /* 354 * There are 4 banks supported for this Controller, 355 * but we have only 1 bank connected to flash on board 356 */ 357 #define CONFIG_SYS_MAX_FLASH_BANKS 1 358 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 359 360 /* max number of sectors on one chip */ 361 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 362 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 363 #define CONFIG_SYS_MAX_FLASH_SECT 512 364 365 /* environments */ 366 #define CONFIG_ENV_IS_IN_FLASH 367 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 368 #define CONFIG_ENV_SIZE 8192 369 #define CONFIG_ENV_OVERWRITE 370 371 #endif /* __CONFIG_H */ 372