1 /* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch-ag101/ag101.h> 13 14 /* 15 * CPU and Board Configuration Options 16 */ 17 #define CONFIG_ADP_AG101P 18 19 #define CONFIG_USE_INTERRUPT 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 23 /* 24 * Definitions related to passing arguments to kernel. 25 */ 26 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ 27 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ 28 #define CONFIG_INITRD_TAG /* send initrd params */ 29 30 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 31 #define CONFIG_MEM_REMAP 32 #endif 33 34 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 35 #define CONFIG_SYS_TEXT_BASE 0x03200000 36 #else 37 #define CONFIG_SYS_TEXT_BASE 0x00000000 38 #endif 39 40 /* 41 * Timer 42 */ 43 #define CONFIG_SYS_CLK_FREQ 39062500 44 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 45 46 /* 47 * Use Externel CLOCK or PCLK 48 */ 49 #undef CONFIG_FTRTC010_EXTCLK 50 51 #ifndef CONFIG_FTRTC010_EXTCLK 52 #define CONFIG_FTRTC010_PCLK 53 #endif 54 55 #ifdef CONFIG_FTRTC010_EXTCLK 56 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 57 #else 58 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 59 #endif 60 61 #define TIMER_LOAD_VAL 0xffffffff 62 63 /* 64 * Real Time Clock 65 */ 66 #define CONFIG_RTC_FTRTC010 67 68 /* 69 * Real Time Clock Divider 70 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 71 */ 72 #define OSC_5MHZ (5*1000000) 73 #define OSC_CLK (4*OSC_5MHZ) 74 #define RTC_DIV_COUNT (0.5) /* Why?? */ 75 76 /* 77 * Serial console configuration 78 */ 79 80 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 81 #define CONFIG_BAUDRATE 38400 82 #define CONFIG_CONS_INDEX 1 83 #define CONFIG_SYS_NS16550 84 #define CONFIG_SYS_NS16550_SERIAL 85 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 86 #define CONFIG_SYS_NS16550_REG_SIZE -4 87 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 88 89 /* 90 * Ethernet 91 */ 92 #define CONFIG_FTMAC100 93 94 #define CONFIG_BOOTDELAY 3 95 96 /* 97 * SD (MMC) controller 98 */ 99 #define CONFIG_MMC 100 #define CONFIG_CMD_MMC 101 #define CONFIG_GENERIC_MMC 102 #define CONFIG_DOS_PARTITION 103 #define CONFIG_FTSDC010 104 #define CONFIG_FTSDC010_NUMBER 1 105 #define CONFIG_FTSDC010_SDIO 106 #define CONFIG_CMD_FAT 107 #define CONFIG_CMD_EXT2 108 109 /* 110 * Command line configuration. 111 */ 112 #define CONFIG_CMD_CACHE 113 #define CONFIG_CMD_DATE 114 #define CONFIG_CMD_PING 115 116 /* 117 * Miscellaneous configurable options 118 */ 119 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 120 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 121 122 /* Print Buffer Size */ 123 #define CONFIG_SYS_PBSIZE \ 124 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 125 126 /* max number of command args */ 127 #define CONFIG_SYS_MAXARGS 16 128 129 /* Boot Argument Buffer Size */ 130 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 131 132 /* 133 * Size of malloc() pool 134 */ 135 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 136 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 137 138 /* 139 * AHB Controller configuration 140 */ 141 #define CONFIG_FTAHBC020S 142 143 #ifdef CONFIG_FTAHBC020S 144 #include <faraday/ftahbc020s.h> 145 146 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 147 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 148 149 /* 150 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 151 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 152 * in C language. 153 */ 154 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 155 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 156 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 157 #endif 158 159 /* 160 * Watchdog 161 */ 162 #define CONFIG_FTWDT010_WATCHDOG 163 164 /* 165 * PMU Power controller configuration 166 */ 167 #define CONFIG_PMU 168 #define CONFIG_FTPMU010_POWER 169 170 #ifdef CONFIG_FTPMU010_POWER 171 #include <faraday/ftpmu010.h> 172 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 173 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 174 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 175 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 176 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 177 FTPMU010_SDRAMHTC_CKE_DCSR | \ 178 FTPMU010_SDRAMHTC_DQM_DCSR | \ 179 FTPMU010_SDRAMHTC_SDCLK_DCSR) 180 #endif 181 182 /* 183 * SDRAM controller configuration 184 */ 185 #define CONFIG_FTSDMC021 186 187 #ifdef CONFIG_FTSDMC021 188 #include <faraday/ftsdmc021.h> 189 190 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 191 FTSDMC021_TP1_TRP(1) | \ 192 FTSDMC021_TP1_TRCD(1) | \ 193 FTSDMC021_TP1_TRF(3) | \ 194 FTSDMC021_TP1_TWR(1) | \ 195 FTSDMC021_TP1_TCL(2)) 196 197 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 198 FTSDMC021_TP2_INI_REFT(8) | \ 199 FTSDMC021_TP2_REF_INTV(0x180)) 200 201 /* 202 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 203 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 204 * C language. 205 */ 206 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 207 FTSDMC021_CR1_DSZ(3) | \ 208 FTSDMC021_CR1_MBW(2) | \ 209 FTSDMC021_CR1_BNKSIZE(6)) 210 211 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 212 FTSDMC021_CR2_IREF | \ 213 FTSDMC021_CR2_ISMR) 214 215 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 216 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 217 CONFIG_SYS_FTSDMC021_BANK0_BASE) 218 219 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 220 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 221 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 222 CONFIG_SYS_FTSDMC021_BANK1_BASE) 223 #endif 224 225 /* 226 * Physical Memory Map 227 */ 228 #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT) 229 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 230 #if defined(CONFIG_MEM_REMAP) 231 #define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/ 232 #endif 233 #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ 234 #define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */ 235 #endif 236 #define PHYS_SDRAM_1 \ 237 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 238 239 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 240 #define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */ 241 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 242 243 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 244 245 #ifdef CONFIG_MEM_REMAP 246 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 247 GENERATED_GBL_DATA_SIZE) 248 #else 249 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 250 GENERATED_GBL_DATA_SIZE) 251 #endif /* CONFIG_MEM_REMAP */ 252 253 /* 254 * Load address and memory test area should agree with 255 * arch/nds32/config.mk. Be careful not to overwrite U-boot itself. 256 */ 257 #define CONFIG_SYS_LOAD_ADDR 0x300000 258 259 /* memtest works on 63 MB in DRAM */ 260 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 261 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 262 263 /* 264 * Static memory controller configuration 265 */ 266 #define CONFIG_FTSMC020 267 268 #ifdef CONFIG_FTSMC020 269 #include <faraday/ftsmc020.h> 270 271 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 272 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 273 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 274 } 275 276 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 277 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 278 FTSMC020_BANK_SIZE_32M | \ 279 FTSMC020_BANK_MBW_32) 280 281 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 282 FTSMC020_TPR_AST(1) | \ 283 FTSMC020_TPR_CTW(1) | \ 284 FTSMC020_TPR_ATI(1) | \ 285 FTSMC020_TPR_AT2(1) | \ 286 FTSMC020_TPR_WTC(1) | \ 287 FTSMC020_TPR_AHT(1) | \ 288 FTSMC020_TPR_TRNA(1)) 289 #endif 290 291 /* 292 * FLASH on ADP_AG101P is connected to BANK0 293 * Just disalbe the other BANK to avoid detection error. 294 */ 295 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 296 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 297 FTSMC020_BANK_SIZE_32M | \ 298 FTSMC020_BANK_MBW_32) 299 300 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 301 FTSMC020_TPR_CTW(3) | \ 302 FTSMC020_TPR_ATI(0xf) | \ 303 FTSMC020_TPR_AT2(3) | \ 304 FTSMC020_TPR_WTC(3) | \ 305 FTSMC020_TPR_AHT(3) | \ 306 FTSMC020_TPR_TRNA(0xf)) 307 308 #define FTSMC020_BANK1_CONFIG (0x00) 309 #define FTSMC020_BANK1_TIMING (0x00) 310 #endif /* CONFIG_FTSMC020 */ 311 312 /* 313 * FLASH and environment organization 314 */ 315 /* use CFI framework */ 316 #define CONFIG_SYS_FLASH_CFI 317 #define CONFIG_FLASH_CFI_DRIVER 318 319 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 320 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 321 322 /* support JEDEC */ 323 324 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 325 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 326 #define PHYS_FLASH_1 0x80400000 /* BANK 1 */ 327 #else /* !CONFIG_SKIP_LOWLEVEL_INIT */ 328 #ifdef CONFIG_MEM_REMAP 329 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 330 #else 331 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 332 #endif /* CONFIG_MEM_REMAP */ 333 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 334 335 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 336 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 337 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 338 339 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 340 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 341 342 /* max number of memory banks */ 343 /* 344 * There are 4 banks supported for this Controller, 345 * but we have only 1 bank connected to flash on board 346 */ 347 #define CONFIG_SYS_MAX_FLASH_BANKS 1 348 349 /* max number of sectors on one chip */ 350 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2) 351 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 352 #define CONFIG_SYS_MAX_FLASH_SECT 128 353 354 /* environments */ 355 #define CONFIG_ENV_IS_IN_FLASH 356 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 357 #define CONFIG_ENV_SIZE 8192 358 #define CONFIG_ENV_OVERWRITE 359 360 #endif /* __CONFIG_H */ 361