1 /* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch-ag101/ag101.h> 13 14 /* 15 * CPU and Board Configuration Options 16 */ 17 #define CONFIG_USE_INTERRUPT 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 21 #define CONFIG_CMDLINE_EDITING 22 23 #define CONFIG_ARCH_MAP_SYSMEM 24 25 #define CONFIG_BOOTP_SEND_HOSTNAME 26 #define CONFIG_BOOTP_SERVERIP 27 28 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 29 #define CONFIG_MEM_REMAP 30 #endif 31 32 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 33 #ifdef CONFIG_OF_CONTROL 34 #undef CONFIG_OF_SEPARATE 35 #define CONFIG_OF_EMBED 36 #endif 37 #endif 38 39 /* 40 * Timer 41 */ 42 #define CONFIG_SYS_CLK_FREQ 39062500 43 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 44 45 /* 46 * Use Externel CLOCK or PCLK 47 */ 48 #undef CONFIG_FTRTC010_EXTCLK 49 50 #ifndef CONFIG_FTRTC010_EXTCLK 51 #define CONFIG_FTRTC010_PCLK 52 #endif 53 54 #ifdef CONFIG_FTRTC010_EXTCLK 55 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 56 #else 57 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 58 #endif 59 60 #define TIMER_LOAD_VAL 0xffffffff 61 62 /* 63 * Real Time Clock 64 */ 65 #define CONFIG_RTC_FTRTC010 66 67 /* 68 * Real Time Clock Divider 69 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 70 */ 71 #define OSC_5MHZ (5*1000000) 72 #define OSC_CLK (4*OSC_5MHZ) 73 #define RTC_DIV_COUNT (0.5) /* Why?? */ 74 75 /* 76 * Serial console configuration 77 */ 78 79 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 80 #define CONFIG_CONS_INDEX 1 81 #define CONFIG_SYS_NS16550_SERIAL 82 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 83 #ifndef CONFIG_DM_SERIAL 84 #define CONFIG_SYS_NS16550_REG_SIZE -4 85 #endif 86 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 87 88 /* 89 * SD (MMC) controller 90 */ 91 #define CONFIG_FTSDC010_NUMBER 1 92 #define CONFIG_FTSDC010_SDIO 93 94 /* 95 * Miscellaneous configurable options 96 */ 97 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 98 99 /* 100 * Size of malloc() pool 101 */ 102 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 103 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 104 105 /* 106 * AHB Controller configuration 107 */ 108 #define CONFIG_FTAHBC020S 109 110 #ifdef CONFIG_FTAHBC020S 111 #include <faraday/ftahbc020s.h> 112 113 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 114 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 115 116 /* 117 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 118 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 119 * in C language. 120 */ 121 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 122 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 123 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 124 #endif 125 126 /* 127 * Watchdog 128 */ 129 #define CONFIG_FTWDT010_WATCHDOG 130 131 /* 132 * PMU Power controller configuration 133 */ 134 #define CONFIG_PMU 135 #define CONFIG_FTPMU010_POWER 136 137 #ifdef CONFIG_FTPMU010_POWER 138 #include <faraday/ftpmu010.h> 139 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 140 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 141 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 142 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 143 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 144 FTPMU010_SDRAMHTC_CKE_DCSR | \ 145 FTPMU010_SDRAMHTC_DQM_DCSR | \ 146 FTPMU010_SDRAMHTC_SDCLK_DCSR) 147 #endif 148 149 /* 150 * SDRAM controller configuration 151 */ 152 #define CONFIG_FTSDMC021 153 154 #ifdef CONFIG_FTSDMC021 155 #include <faraday/ftsdmc021.h> 156 157 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 158 FTSDMC021_TP1_TRP(1) | \ 159 FTSDMC021_TP1_TRCD(1) | \ 160 FTSDMC021_TP1_TRF(3) | \ 161 FTSDMC021_TP1_TWR(1) | \ 162 FTSDMC021_TP1_TCL(2)) 163 164 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 165 FTSDMC021_TP2_INI_REFT(8) | \ 166 FTSDMC021_TP2_REF_INTV(0x180)) 167 168 /* 169 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 170 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 171 * C language. 172 */ 173 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 174 FTSDMC021_CR1_DSZ(3) | \ 175 FTSDMC021_CR1_MBW(2) | \ 176 FTSDMC021_CR1_BNKSIZE(6)) 177 178 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 179 FTSDMC021_CR2_IREF | \ 180 FTSDMC021_CR2_ISMR) 181 182 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 183 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 184 CONFIG_SYS_FTSDMC021_BANK0_BASE) 185 186 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 187 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 188 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 189 CONFIG_SYS_FTSDMC021_BANK1_BASE) 190 #endif 191 192 /* 193 * Physical Memory Map 194 */ 195 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 196 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 197 #else 198 #ifdef CONFIG_MEM_REMAP 199 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 200 #else 201 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ 202 #endif 203 #endif 204 205 #define PHYS_SDRAM_1 \ 206 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 207 208 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 209 210 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 211 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 212 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 213 #else 214 #ifdef CONFIG_MEM_REMAP 215 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 216 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 217 #else 218 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ 219 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 220 #endif 221 #endif 222 223 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 224 225 #ifdef CONFIG_MEM_REMAP 226 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 227 GENERATED_GBL_DATA_SIZE) 228 #else 229 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 230 GENERATED_GBL_DATA_SIZE) 231 #endif /* CONFIG_MEM_REMAP */ 232 233 /* 234 * Load address and memory test area should agree with 235 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 236 */ 237 #define CONFIG_SYS_LOAD_ADDR 0x300000 238 239 /* memtest works on 63 MB in DRAM */ 240 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 241 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 242 243 /* 244 * Static memory controller configuration 245 */ 246 #define CONFIG_FTSMC020 247 248 #ifdef CONFIG_FTSMC020 249 #include <faraday/ftsmc020.h> 250 251 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 252 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 253 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 254 } 255 256 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 257 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 258 FTSMC020_BANK_SIZE_32M | \ 259 FTSMC020_BANK_MBW_32) 260 261 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 262 FTSMC020_TPR_AST(1) | \ 263 FTSMC020_TPR_CTW(1) | \ 264 FTSMC020_TPR_ATI(1) | \ 265 FTSMC020_TPR_AT2(1) | \ 266 FTSMC020_TPR_WTC(1) | \ 267 FTSMC020_TPR_AHT(1) | \ 268 FTSMC020_TPR_TRNA(1)) 269 #endif 270 271 /* 272 * FLASH on ADP_AG101P is connected to BANK0 273 * Just disalbe the other BANK to avoid detection error. 274 */ 275 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 276 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 277 FTSMC020_BANK_SIZE_32M | \ 278 FTSMC020_BANK_MBW_32) 279 280 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 281 FTSMC020_TPR_CTW(3) | \ 282 FTSMC020_TPR_ATI(0xf) | \ 283 FTSMC020_TPR_AT2(3) | \ 284 FTSMC020_TPR_WTC(3) | \ 285 FTSMC020_TPR_AHT(3) | \ 286 FTSMC020_TPR_TRNA(0xf)) 287 288 #define FTSMC020_BANK1_CONFIG (0x00) 289 #define FTSMC020_BANK1_TIMING (0x00) 290 #endif /* CONFIG_FTSMC020 */ 291 292 /* 293 * FLASH and environment organization 294 */ 295 /* use CFI framework */ 296 #define CONFIG_SYS_FLASH_CFI 297 #define CONFIG_FLASH_CFI_DRIVER 298 299 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 300 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 301 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 302 303 /* support JEDEC */ 304 305 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 306 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 307 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 308 #else 309 #ifdef CONFIG_MEM_REMAP 310 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 311 #else 312 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 313 #endif 314 #endif /* CONFIG_MEM_REMAP */ 315 316 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 317 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 318 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 319 320 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 321 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 322 323 /* max number of memory banks */ 324 /* 325 * There are 4 banks supported for this Controller, 326 * but we have only 1 bank connected to flash on board 327 */ 328 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 329 #define CONFIG_SYS_MAX_FLASH_BANKS 1 330 #endif 331 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 332 333 /* max number of sectors on one chip */ 334 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 335 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 336 #define CONFIG_SYS_MAX_FLASH_SECT 512 337 338 /* environments */ 339 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 340 #define CONFIG_ENV_SIZE 8192 341 #define CONFIG_ENV_OVERWRITE 342 343 /* 344 * For booting Linux, the board info and command line data 345 * have to be in the first 16 MB of memory, since this is 346 * the maximum mapped by the Linux kernel during initialization. 347 */ 348 349 /* Initial Memory map for Linux*/ 350 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) 351 /* Increase max gunzip size */ 352 #define CONFIG_SYS_BOOTM_LEN (64 << 20) 353 354 #endif /* __CONFIG_H */ 355