1 /* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch/ag101.h> 13 14 /* 15 * CPU and Board Configuration Options 16 */ 17 #define CONFIG_ADP_AG101P 18 19 #define CONFIG_USE_INTERRUPT 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 23 /* 24 * Definitions related to passing arguments to kernel. 25 */ 26 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ 27 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ 28 #define CONFIG_INITRD_TAG /* send initrd params */ 29 30 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 31 #define CONFIG_MEM_REMAP 32 #endif 33 34 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 35 #define CONFIG_SYS_TEXT_BASE 0x03200000 36 #else 37 #define CONFIG_SYS_TEXT_BASE 0x00000000 38 #endif 39 40 /* 41 * Timer 42 */ 43 44 /* 45 * According to the discussion in u-boot mailing list before, 46 * CONFIG_SYS_HZ at 1000 is mandatory. 47 */ 48 #define CONFIG_SYS_HZ 1000 49 #define CONFIG_SYS_CLK_FREQ 39062500 50 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 51 52 /* 53 * Use Externel CLOCK or PCLK 54 */ 55 #undef CONFIG_FTRTC010_EXTCLK 56 57 #ifndef CONFIG_FTRTC010_EXTCLK 58 #define CONFIG_FTRTC010_PCLK 59 #endif 60 61 #ifdef CONFIG_FTRTC010_EXTCLK 62 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 63 #else 64 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 65 #endif 66 67 #define TIMER_LOAD_VAL 0xffffffff 68 69 /* 70 * Real Time Clock 71 */ 72 #define CONFIG_RTC_FTRTC010 73 74 /* 75 * Real Time Clock Divider 76 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 77 */ 78 #define OSC_5MHZ (5*1000000) 79 #define OSC_CLK (4*OSC_5MHZ) 80 #define RTC_DIV_COUNT (0.5) /* Why?? */ 81 82 /* 83 * Serial console configuration 84 */ 85 86 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 87 #define CONFIG_BAUDRATE 38400 88 #define CONFIG_CONS_INDEX 1 89 #define CONFIG_SYS_NS16550 90 #define CONFIG_SYS_NS16550_SERIAL 91 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 92 #define CONFIG_SYS_NS16550_REG_SIZE -4 93 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 94 95 /* 96 * Ethernet 97 */ 98 #define CONFIG_FTMAC100 99 100 #define CONFIG_BOOTDELAY 3 101 102 /* 103 * SD (MMC) controller 104 */ 105 #define CONFIG_MMC 106 #define CONFIG_CMD_MMC 107 #define CONFIG_GENERIC_MMC 108 #define CONFIG_DOS_PARTITION 109 #define CONFIG_FTSDC010 110 #define CONFIG_FTSDC010_NUMBER 1 111 #define CONFIG_FTSDC010_SDIO 112 #define CONFIG_CMD_FAT 113 #define CONFIG_CMD_EXT2 114 115 /* 116 * Command line configuration. 117 */ 118 #include <config_cmd_default.h> 119 120 #define CONFIG_CMD_CACHE 121 #define CONFIG_CMD_DATE 122 #define CONFIG_CMD_PING 123 124 /* 125 * Miscellaneous configurable options 126 */ 127 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 128 #define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */ 129 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 130 131 /* Print Buffer Size */ 132 #define CONFIG_SYS_PBSIZE \ 133 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 134 135 /* max number of command args */ 136 #define CONFIG_SYS_MAXARGS 16 137 138 /* Boot Argument Buffer Size */ 139 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 140 141 /* 142 * Size of malloc() pool 143 */ 144 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 145 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 146 147 /* 148 * size in bytes reserved for initial data 149 */ 150 #define CONFIG_SYS_GBL_DATA_SIZE 128 151 152 /* 153 * AHB Controller configuration 154 */ 155 #define CONFIG_FTAHBC020S 156 157 #ifdef CONFIG_FTAHBC020S 158 #include <faraday/ftahbc020s.h> 159 160 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 161 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 162 163 /* 164 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 165 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 166 * in C language. 167 */ 168 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 169 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 170 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 171 #endif 172 173 /* 174 * Watchdog 175 */ 176 #define CONFIG_FTWDT010_WATCHDOG 177 178 /* 179 * PMU Power controller configuration 180 */ 181 #define CONFIG_PMU 182 #define CONFIG_FTPMU010_POWER 183 184 #ifdef CONFIG_FTPMU010_POWER 185 #include <faraday/ftpmu010.h> 186 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 187 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 188 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 189 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 190 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 191 FTPMU010_SDRAMHTC_CKE_DCSR | \ 192 FTPMU010_SDRAMHTC_DQM_DCSR | \ 193 FTPMU010_SDRAMHTC_SDCLK_DCSR) 194 #endif 195 196 /* 197 * SDRAM controller configuration 198 */ 199 #define CONFIG_FTSDMC021 200 201 #ifdef CONFIG_FTSDMC021 202 #include <faraday/ftsdmc021.h> 203 204 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 205 FTSDMC021_TP1_TRP(1) | \ 206 FTSDMC021_TP1_TRCD(1) | \ 207 FTSDMC021_TP1_TRF(3) | \ 208 FTSDMC021_TP1_TWR(1) | \ 209 FTSDMC021_TP1_TCL(2)) 210 211 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 212 FTSDMC021_TP2_INI_REFT(8) | \ 213 FTSDMC021_TP2_REF_INTV(0x180)) 214 215 /* 216 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 217 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 218 * C language. 219 */ 220 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 221 FTSDMC021_CR1_DSZ(3) | \ 222 FTSDMC021_CR1_MBW(2) | \ 223 FTSDMC021_CR1_BNKSIZE(6)) 224 225 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 226 FTSDMC021_CR2_IREF | \ 227 FTSDMC021_CR2_ISMR) 228 229 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 230 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 231 CONFIG_SYS_FTSDMC021_BANK0_BASE) 232 233 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 234 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 235 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 236 CONFIG_SYS_FTSDMC021_BANK1_BASE) 237 #endif 238 239 /* 240 * Physical Memory Map 241 */ 242 #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT) 243 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 244 #if defined(CONFIG_MEM_REMAP) 245 #define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/ 246 #endif 247 #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ 248 #define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */ 249 #endif 250 #define PHYS_SDRAM_1 \ 251 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 252 253 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 254 #define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */ 255 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 256 257 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 258 259 #ifdef CONFIG_MEM_REMAP 260 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 261 GENERATED_GBL_DATA_SIZE) 262 #else 263 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 264 GENERATED_GBL_DATA_SIZE) 265 #endif /* CONFIG_MEM_REMAP */ 266 267 /* 268 * Load address and memory test area should agree with 269 * arch/nds32/config.mk. Be careful not to overwrite U-boot itself. 270 */ 271 #define CONFIG_SYS_LOAD_ADDR 0x300000 272 273 /* memtest works on 63 MB in DRAM */ 274 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 275 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 276 277 /* 278 * Static memory controller configuration 279 */ 280 #define CONFIG_FTSMC020 281 282 #ifdef CONFIG_FTSMC020 283 #include <faraday/ftsmc020.h> 284 285 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 286 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 287 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 288 } 289 290 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 291 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 292 FTSMC020_BANK_SIZE_32M | \ 293 FTSMC020_BANK_MBW_32) 294 295 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 296 FTSMC020_TPR_AST(1) | \ 297 FTSMC020_TPR_CTW(1) | \ 298 FTSMC020_TPR_ATI(1) | \ 299 FTSMC020_TPR_AT2(1) | \ 300 FTSMC020_TPR_WTC(1) | \ 301 FTSMC020_TPR_AHT(1) | \ 302 FTSMC020_TPR_TRNA(1)) 303 #endif 304 305 /* 306 * FLASH on ADP_AG101P is connected to BANK0 307 * Just disalbe the other BANK to avoid detection error. 308 */ 309 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 310 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 311 FTSMC020_BANK_SIZE_32M | \ 312 FTSMC020_BANK_MBW_32) 313 314 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 315 FTSMC020_TPR_CTW(3) | \ 316 FTSMC020_TPR_ATI(0xf) | \ 317 FTSMC020_TPR_AT2(3) | \ 318 FTSMC020_TPR_WTC(3) | \ 319 FTSMC020_TPR_AHT(3) | \ 320 FTSMC020_TPR_TRNA(0xf)) 321 322 #define FTSMC020_BANK1_CONFIG (0x00) 323 #define FTSMC020_BANK1_TIMING (0x00) 324 #endif /* CONFIG_FTSMC020 */ 325 326 /* 327 * FLASH and environment organization 328 */ 329 /* use CFI framework */ 330 #define CONFIG_SYS_FLASH_CFI 331 #define CONFIG_FLASH_CFI_DRIVER 332 333 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 334 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 335 336 /* support JEDEC */ 337 338 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 339 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 340 #define PHYS_FLASH_1 0x80400000 /* BANK 1 */ 341 #else /* !CONFIG_SKIP_LOWLEVEL_INIT */ 342 #ifdef CONFIG_MEM_REMAP 343 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 344 #else 345 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 346 #endif /* CONFIG_MEM_REMAP */ 347 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 348 349 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 350 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 351 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 352 353 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 354 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 355 356 /* max number of memory banks */ 357 /* 358 * There are 4 banks supported for this Controller, 359 * but we have only 1 bank connected to flash on board 360 */ 361 #define CONFIG_SYS_MAX_FLASH_BANKS 1 362 363 /* max number of sectors on one chip */ 364 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2) 365 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 366 #define CONFIG_SYS_MAX_FLASH_SECT 128 367 368 /* environments */ 369 #define CONFIG_ENV_IS_IN_FLASH 370 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 371 #define CONFIG_ENV_SIZE 8192 372 #define CONFIG_ENV_OVERWRITE 373 374 #endif /* __CONFIG_H */ 375