1 /* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch-ag101/ag101.h> 13 14 /* 15 * CPU and Board Configuration Options 16 */ 17 #define CONFIG_ADP_AG101P 18 19 #define CONFIG_USE_INTERRUPT 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 23 #define CONFIG_SYS_GENERIC_GLOBAL_DATA 24 25 /* 26 * Definitions related to passing arguments to kernel. 27 */ 28 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ 29 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ 30 #define CONFIG_INITRD_TAG /* send initrd params */ 31 32 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 33 #define CONFIG_MEM_REMAP 34 #endif 35 36 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 37 #define CONFIG_SYS_TEXT_BASE 0x00500000 38 #else 39 #ifdef CONFIG_MEM_REMAP 40 #define CONFIG_SYS_TEXT_BASE 0x80000000 41 #else 42 #define CONFIG_SYS_TEXT_BASE 0x00000000 43 #endif 44 #endif 45 46 /* 47 * Timer 48 */ 49 #define CONFIG_SYS_CLK_FREQ 39062500 50 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 51 52 /* 53 * Use Externel CLOCK or PCLK 54 */ 55 #undef CONFIG_FTRTC010_EXTCLK 56 57 #ifndef CONFIG_FTRTC010_EXTCLK 58 #define CONFIG_FTRTC010_PCLK 59 #endif 60 61 #ifdef CONFIG_FTRTC010_EXTCLK 62 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 63 #else 64 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 65 #endif 66 67 #define TIMER_LOAD_VAL 0xffffffff 68 69 /* 70 * Real Time Clock 71 */ 72 #define CONFIG_RTC_FTRTC010 73 74 /* 75 * Real Time Clock Divider 76 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 77 */ 78 #define OSC_5MHZ (5*1000000) 79 #define OSC_CLK (4*OSC_5MHZ) 80 #define RTC_DIV_COUNT (0.5) /* Why?? */ 81 82 /* 83 * Serial console configuration 84 */ 85 86 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 87 #define CONFIG_BAUDRATE 38400 88 #define CONFIG_CONS_INDEX 1 89 #define CONFIG_SYS_NS16550_SERIAL 90 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 91 #define CONFIG_SYS_NS16550_REG_SIZE -4 92 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 93 94 /* 95 * Ethernet 96 */ 97 #define CONFIG_FTMAC100 98 99 100 /* 101 * SD (MMC) controller 102 */ 103 #define CONFIG_GENERIC_MMC 104 #define CONFIG_FTSDC010 105 #define CONFIG_FTSDC010_NUMBER 1 106 #define CONFIG_FTSDC010_SDIO 107 108 /* 109 * Command line configuration. 110 */ 111 #define CONFIG_CMD_DATE 112 113 /* 114 * Miscellaneous configurable options 115 */ 116 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 117 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 118 119 /* Print Buffer Size */ 120 #define CONFIG_SYS_PBSIZE \ 121 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 122 123 /* max number of command args */ 124 #define CONFIG_SYS_MAXARGS 16 125 126 /* Boot Argument Buffer Size */ 127 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 128 129 /* 130 * Size of malloc() pool 131 */ 132 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 133 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 134 135 /* 136 * AHB Controller configuration 137 */ 138 #define CONFIG_FTAHBC020S 139 140 #ifdef CONFIG_FTAHBC020S 141 #include <faraday/ftahbc020s.h> 142 143 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 144 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 145 146 /* 147 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 148 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 149 * in C language. 150 */ 151 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 152 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 153 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 154 #endif 155 156 /* 157 * Watchdog 158 */ 159 #define CONFIG_FTWDT010_WATCHDOG 160 161 /* 162 * PMU Power controller configuration 163 */ 164 #define CONFIG_PMU 165 #define CONFIG_FTPMU010_POWER 166 167 #ifdef CONFIG_FTPMU010_POWER 168 #include <faraday/ftpmu010.h> 169 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 170 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 171 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 172 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 173 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 174 FTPMU010_SDRAMHTC_CKE_DCSR | \ 175 FTPMU010_SDRAMHTC_DQM_DCSR | \ 176 FTPMU010_SDRAMHTC_SDCLK_DCSR) 177 #endif 178 179 /* 180 * SDRAM controller configuration 181 */ 182 #define CONFIG_FTSDMC021 183 184 #ifdef CONFIG_FTSDMC021 185 #include <faraday/ftsdmc021.h> 186 187 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 188 FTSDMC021_TP1_TRP(1) | \ 189 FTSDMC021_TP1_TRCD(1) | \ 190 FTSDMC021_TP1_TRF(3) | \ 191 FTSDMC021_TP1_TWR(1) | \ 192 FTSDMC021_TP1_TCL(2)) 193 194 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 195 FTSDMC021_TP2_INI_REFT(8) | \ 196 FTSDMC021_TP2_REF_INTV(0x180)) 197 198 /* 199 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 200 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 201 * C language. 202 */ 203 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 204 FTSDMC021_CR1_DSZ(3) | \ 205 FTSDMC021_CR1_MBW(2) | \ 206 FTSDMC021_CR1_BNKSIZE(6)) 207 208 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 209 FTSDMC021_CR2_IREF | \ 210 FTSDMC021_CR2_ISMR) 211 212 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 213 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 214 CONFIG_SYS_FTSDMC021_BANK0_BASE) 215 216 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 217 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 218 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 219 CONFIG_SYS_FTSDMC021_BANK1_BASE) 220 #endif 221 222 /* 223 * Physical Memory Map 224 */ 225 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 226 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 227 #else 228 #ifdef CONFIG_MEM_REMAP 229 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 230 #else 231 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ 232 #endif 233 #endif 234 235 #define PHYS_SDRAM_1 \ 236 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 237 238 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 239 240 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 241 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 242 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 243 #else 244 #ifdef CONFIG_MEM_REMAP 245 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 246 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 247 #else 248 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ 249 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 250 #endif 251 #endif 252 253 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 254 255 #ifdef CONFIG_MEM_REMAP 256 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 257 GENERATED_GBL_DATA_SIZE) 258 #else 259 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 260 GENERATED_GBL_DATA_SIZE) 261 #endif /* CONFIG_MEM_REMAP */ 262 263 /* 264 * Load address and memory test area should agree with 265 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 266 */ 267 #define CONFIG_SYS_LOAD_ADDR 0x300000 268 269 /* memtest works on 63 MB in DRAM */ 270 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 271 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 272 273 /* 274 * Static memory controller configuration 275 */ 276 #define CONFIG_FTSMC020 277 278 #ifdef CONFIG_FTSMC020 279 #include <faraday/ftsmc020.h> 280 281 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 282 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 283 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 284 } 285 286 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 287 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 288 FTSMC020_BANK_SIZE_32M | \ 289 FTSMC020_BANK_MBW_32) 290 291 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 292 FTSMC020_TPR_AST(1) | \ 293 FTSMC020_TPR_CTW(1) | \ 294 FTSMC020_TPR_ATI(1) | \ 295 FTSMC020_TPR_AT2(1) | \ 296 FTSMC020_TPR_WTC(1) | \ 297 FTSMC020_TPR_AHT(1) | \ 298 FTSMC020_TPR_TRNA(1)) 299 #endif 300 301 /* 302 * FLASH on ADP_AG101P is connected to BANK0 303 * Just disalbe the other BANK to avoid detection error. 304 */ 305 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 306 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 307 FTSMC020_BANK_SIZE_32M | \ 308 FTSMC020_BANK_MBW_32) 309 310 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 311 FTSMC020_TPR_CTW(3) | \ 312 FTSMC020_TPR_ATI(0xf) | \ 313 FTSMC020_TPR_AT2(3) | \ 314 FTSMC020_TPR_WTC(3) | \ 315 FTSMC020_TPR_AHT(3) | \ 316 FTSMC020_TPR_TRNA(0xf)) 317 318 #define FTSMC020_BANK1_CONFIG (0x00) 319 #define FTSMC020_BANK1_TIMING (0x00) 320 #endif /* CONFIG_FTSMC020 */ 321 322 /* 323 * FLASH and environment organization 324 */ 325 /* use CFI framework */ 326 #define CONFIG_SYS_FLASH_CFI 327 #define CONFIG_FLASH_CFI_DRIVER 328 329 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 330 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 331 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 332 333 /* support JEDEC */ 334 335 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 336 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 337 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 338 #else 339 #ifdef CONFIG_MEM_REMAP 340 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 341 #else 342 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 343 #endif 344 #endif /* CONFIG_MEM_REMAP */ 345 346 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 347 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 348 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 349 350 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 351 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 352 353 /* max number of memory banks */ 354 /* 355 * There are 4 banks supported for this Controller, 356 * but we have only 1 bank connected to flash on board 357 */ 358 #define CONFIG_SYS_MAX_FLASH_BANKS 1 359 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 360 361 /* max number of sectors on one chip */ 362 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 363 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 364 #define CONFIG_SYS_MAX_FLASH_SECT 512 365 366 /* environments */ 367 #define CONFIG_ENV_IS_IN_FLASH 368 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 369 #define CONFIG_ENV_SIZE 8192 370 #define CONFIG_ENV_OVERWRITE 371 372 #endif /* __CONFIG_H */ 373