1 /* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch-ag101/ag101.h> 13 14 /* 15 * CPU and Board Configuration Options 16 */ 17 #define CONFIG_ADP_AG101P 18 19 #define CONFIG_USE_INTERRUPT 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 23 #define CONFIG_SYS_GENERIC_GLOBAL_DATA 24 25 /* 26 * Definitions related to passing arguments to kernel. 27 */ 28 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ 29 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ 30 #define CONFIG_INITRD_TAG /* send initrd params */ 31 32 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 33 #define CONFIG_MEM_REMAP 34 #endif 35 36 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 37 #define CONFIG_SYS_TEXT_BASE 0x00500000 38 #else 39 #ifdef CONFIG_MEM_REMAP 40 #define CONFIG_SYS_TEXT_BASE 0x80000000 41 #else 42 #define CONFIG_SYS_TEXT_BASE 0x00000000 43 #endif 44 #endif 45 46 /* 47 * Timer 48 */ 49 #define CONFIG_SYS_CLK_FREQ 39062500 50 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 51 52 /* 53 * Use Externel CLOCK or PCLK 54 */ 55 #undef CONFIG_FTRTC010_EXTCLK 56 57 #ifndef CONFIG_FTRTC010_EXTCLK 58 #define CONFIG_FTRTC010_PCLK 59 #endif 60 61 #ifdef CONFIG_FTRTC010_EXTCLK 62 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 63 #else 64 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 65 #endif 66 67 #define TIMER_LOAD_VAL 0xffffffff 68 69 /* 70 * Real Time Clock 71 */ 72 #define CONFIG_RTC_FTRTC010 73 74 /* 75 * Real Time Clock Divider 76 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 77 */ 78 #define OSC_5MHZ (5*1000000) 79 #define OSC_CLK (4*OSC_5MHZ) 80 #define RTC_DIV_COUNT (0.5) /* Why?? */ 81 82 /* 83 * Serial console configuration 84 */ 85 86 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 87 #define CONFIG_CONS_INDEX 1 88 #define CONFIG_SYS_NS16550_SERIAL 89 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 90 #define CONFIG_SYS_NS16550_REG_SIZE -4 91 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 92 93 /* 94 * Ethernet 95 */ 96 #define CONFIG_FTMAC100 97 98 99 /* 100 * SD (MMC) controller 101 */ 102 #define CONFIG_FTSDC010 103 #define CONFIG_FTSDC010_NUMBER 1 104 #define CONFIG_FTSDC010_SDIO 105 106 /* 107 * Miscellaneous configurable options 108 */ 109 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 110 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 111 112 /* Print Buffer Size */ 113 #define CONFIG_SYS_PBSIZE \ 114 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 115 116 /* max number of command args */ 117 #define CONFIG_SYS_MAXARGS 16 118 119 /* Boot Argument Buffer Size */ 120 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 121 122 /* 123 * Size of malloc() pool 124 */ 125 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 126 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 127 128 /* 129 * AHB Controller configuration 130 */ 131 #define CONFIG_FTAHBC020S 132 133 #ifdef CONFIG_FTAHBC020S 134 #include <faraday/ftahbc020s.h> 135 136 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 137 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 138 139 /* 140 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 141 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 142 * in C language. 143 */ 144 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 145 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 146 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 147 #endif 148 149 /* 150 * Watchdog 151 */ 152 #define CONFIG_FTWDT010_WATCHDOG 153 154 /* 155 * PMU Power controller configuration 156 */ 157 #define CONFIG_PMU 158 #define CONFIG_FTPMU010_POWER 159 160 #ifdef CONFIG_FTPMU010_POWER 161 #include <faraday/ftpmu010.h> 162 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 163 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 164 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 165 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 166 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 167 FTPMU010_SDRAMHTC_CKE_DCSR | \ 168 FTPMU010_SDRAMHTC_DQM_DCSR | \ 169 FTPMU010_SDRAMHTC_SDCLK_DCSR) 170 #endif 171 172 /* 173 * SDRAM controller configuration 174 */ 175 #define CONFIG_FTSDMC021 176 177 #ifdef CONFIG_FTSDMC021 178 #include <faraday/ftsdmc021.h> 179 180 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 181 FTSDMC021_TP1_TRP(1) | \ 182 FTSDMC021_TP1_TRCD(1) | \ 183 FTSDMC021_TP1_TRF(3) | \ 184 FTSDMC021_TP1_TWR(1) | \ 185 FTSDMC021_TP1_TCL(2)) 186 187 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 188 FTSDMC021_TP2_INI_REFT(8) | \ 189 FTSDMC021_TP2_REF_INTV(0x180)) 190 191 /* 192 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 193 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 194 * C language. 195 */ 196 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 197 FTSDMC021_CR1_DSZ(3) | \ 198 FTSDMC021_CR1_MBW(2) | \ 199 FTSDMC021_CR1_BNKSIZE(6)) 200 201 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 202 FTSDMC021_CR2_IREF | \ 203 FTSDMC021_CR2_ISMR) 204 205 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 206 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 207 CONFIG_SYS_FTSDMC021_BANK0_BASE) 208 209 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 210 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 211 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 212 CONFIG_SYS_FTSDMC021_BANK1_BASE) 213 #endif 214 215 /* 216 * Physical Memory Map 217 */ 218 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 219 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 220 #else 221 #ifdef CONFIG_MEM_REMAP 222 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 223 #else 224 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ 225 #endif 226 #endif 227 228 #define PHYS_SDRAM_1 \ 229 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 230 231 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 232 233 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 234 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 235 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 236 #else 237 #ifdef CONFIG_MEM_REMAP 238 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 239 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 240 #else 241 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ 242 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 243 #endif 244 #endif 245 246 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 247 248 #ifdef CONFIG_MEM_REMAP 249 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 250 GENERATED_GBL_DATA_SIZE) 251 #else 252 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 253 GENERATED_GBL_DATA_SIZE) 254 #endif /* CONFIG_MEM_REMAP */ 255 256 /* 257 * Load address and memory test area should agree with 258 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 259 */ 260 #define CONFIG_SYS_LOAD_ADDR 0x300000 261 262 /* memtest works on 63 MB in DRAM */ 263 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 264 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 265 266 /* 267 * Static memory controller configuration 268 */ 269 #define CONFIG_FTSMC020 270 271 #ifdef CONFIG_FTSMC020 272 #include <faraday/ftsmc020.h> 273 274 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 275 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 276 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 277 } 278 279 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 280 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 281 FTSMC020_BANK_SIZE_32M | \ 282 FTSMC020_BANK_MBW_32) 283 284 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 285 FTSMC020_TPR_AST(1) | \ 286 FTSMC020_TPR_CTW(1) | \ 287 FTSMC020_TPR_ATI(1) | \ 288 FTSMC020_TPR_AT2(1) | \ 289 FTSMC020_TPR_WTC(1) | \ 290 FTSMC020_TPR_AHT(1) | \ 291 FTSMC020_TPR_TRNA(1)) 292 #endif 293 294 /* 295 * FLASH on ADP_AG101P is connected to BANK0 296 * Just disalbe the other BANK to avoid detection error. 297 */ 298 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 299 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 300 FTSMC020_BANK_SIZE_32M | \ 301 FTSMC020_BANK_MBW_32) 302 303 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 304 FTSMC020_TPR_CTW(3) | \ 305 FTSMC020_TPR_ATI(0xf) | \ 306 FTSMC020_TPR_AT2(3) | \ 307 FTSMC020_TPR_WTC(3) | \ 308 FTSMC020_TPR_AHT(3) | \ 309 FTSMC020_TPR_TRNA(0xf)) 310 311 #define FTSMC020_BANK1_CONFIG (0x00) 312 #define FTSMC020_BANK1_TIMING (0x00) 313 #endif /* CONFIG_FTSMC020 */ 314 315 /* 316 * FLASH and environment organization 317 */ 318 /* use CFI framework */ 319 #define CONFIG_SYS_FLASH_CFI 320 #define CONFIG_FLASH_CFI_DRIVER 321 322 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 323 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 324 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 325 326 /* support JEDEC */ 327 328 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 329 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 330 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 331 #else 332 #ifdef CONFIG_MEM_REMAP 333 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 334 #else 335 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 336 #endif 337 #endif /* CONFIG_MEM_REMAP */ 338 339 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 340 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 341 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 342 343 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 344 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 345 346 /* max number of memory banks */ 347 /* 348 * There are 4 banks supported for this Controller, 349 * but we have only 1 bank connected to flash on board 350 */ 351 #define CONFIG_SYS_MAX_FLASH_BANKS 1 352 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 353 354 /* max number of sectors on one chip */ 355 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 356 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 357 #define CONFIG_SYS_MAX_FLASH_SECT 512 358 359 /* environments */ 360 #define CONFIG_ENV_IS_IN_FLASH 361 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 362 #define CONFIG_ENV_SIZE 8192 363 #define CONFIG_ENV_OVERWRITE 364 365 #endif /* __CONFIG_H */ 366