1 /* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch-ag101/ag101.h> 13 14 /* 15 * CPU and Board Configuration Options 16 */ 17 #define CONFIG_ADP_AG101P 18 19 #define CONFIG_USE_INTERRUPT 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 23 #define CONFIG_SYS_GENERIC_GLOBAL_DATA 24 25 /* 26 * Definitions related to passing arguments to kernel. 27 */ 28 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ 29 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ 30 #define CONFIG_INITRD_TAG /* send initrd params */ 31 #define CONFIG_NEEDS_MANUAL_RELOC 32 33 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 34 #define CONFIG_MEM_REMAP 35 #endif 36 37 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 38 #define CONFIG_SYS_TEXT_BASE 0x00500000 39 #else 40 #ifdef CONFIG_MEM_REMAP 41 #define CONFIG_SYS_TEXT_BASE 0x80000000 42 #else 43 #define CONFIG_SYS_TEXT_BASE 0x00000000 44 #endif 45 #endif 46 47 /* 48 * Timer 49 */ 50 #define CONFIG_SYS_CLK_FREQ 39062500 51 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 52 53 /* 54 * Use Externel CLOCK or PCLK 55 */ 56 #undef CONFIG_FTRTC010_EXTCLK 57 58 #ifndef CONFIG_FTRTC010_EXTCLK 59 #define CONFIG_FTRTC010_PCLK 60 #endif 61 62 #ifdef CONFIG_FTRTC010_EXTCLK 63 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 64 #else 65 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 66 #endif 67 68 #define TIMER_LOAD_VAL 0xffffffff 69 70 /* 71 * Real Time Clock 72 */ 73 #define CONFIG_RTC_FTRTC010 74 75 /* 76 * Real Time Clock Divider 77 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 78 */ 79 #define OSC_5MHZ (5*1000000) 80 #define OSC_CLK (4*OSC_5MHZ) 81 #define RTC_DIV_COUNT (0.5) /* Why?? */ 82 83 /* 84 * Serial console configuration 85 */ 86 87 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 88 #define CONFIG_BAUDRATE 38400 89 #define CONFIG_CONS_INDEX 1 90 #define CONFIG_SYS_NS16550_SERIAL 91 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 92 #define CONFIG_SYS_NS16550_REG_SIZE -4 93 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 94 95 /* 96 * Ethernet 97 */ 98 #define CONFIG_FTMAC100 99 100 101 /* 102 * SD (MMC) controller 103 */ 104 #define CONFIG_MMC 105 #define CONFIG_GENERIC_MMC 106 #define CONFIG_DOS_PARTITION 107 #define CONFIG_FTSDC010 108 #define CONFIG_FTSDC010_NUMBER 1 109 #define CONFIG_FTSDC010_SDIO 110 111 /* 112 * Command line configuration. 113 */ 114 #define CONFIG_CMD_DATE 115 116 /* 117 * Miscellaneous configurable options 118 */ 119 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 120 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 121 122 /* Print Buffer Size */ 123 #define CONFIG_SYS_PBSIZE \ 124 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 125 126 /* max number of command args */ 127 #define CONFIG_SYS_MAXARGS 16 128 129 /* Boot Argument Buffer Size */ 130 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 131 132 /* 133 * Size of malloc() pool 134 */ 135 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 136 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 137 138 /* 139 * AHB Controller configuration 140 */ 141 #define CONFIG_FTAHBC020S 142 143 #ifdef CONFIG_FTAHBC020S 144 #include <faraday/ftahbc020s.h> 145 146 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 147 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 148 149 /* 150 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 151 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 152 * in C language. 153 */ 154 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 155 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 156 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 157 #endif 158 159 /* 160 * Watchdog 161 */ 162 #define CONFIG_FTWDT010_WATCHDOG 163 164 /* 165 * PMU Power controller configuration 166 */ 167 #define CONFIG_PMU 168 #define CONFIG_FTPMU010_POWER 169 170 #ifdef CONFIG_FTPMU010_POWER 171 #include <faraday/ftpmu010.h> 172 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 173 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 174 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 175 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 176 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 177 FTPMU010_SDRAMHTC_CKE_DCSR | \ 178 FTPMU010_SDRAMHTC_DQM_DCSR | \ 179 FTPMU010_SDRAMHTC_SDCLK_DCSR) 180 #endif 181 182 /* 183 * SDRAM controller configuration 184 */ 185 #define CONFIG_FTSDMC021 186 187 #ifdef CONFIG_FTSDMC021 188 #include <faraday/ftsdmc021.h> 189 190 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 191 FTSDMC021_TP1_TRP(1) | \ 192 FTSDMC021_TP1_TRCD(1) | \ 193 FTSDMC021_TP1_TRF(3) | \ 194 FTSDMC021_TP1_TWR(1) | \ 195 FTSDMC021_TP1_TCL(2)) 196 197 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 198 FTSDMC021_TP2_INI_REFT(8) | \ 199 FTSDMC021_TP2_REF_INTV(0x180)) 200 201 /* 202 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 203 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 204 * C language. 205 */ 206 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 207 FTSDMC021_CR1_DSZ(3) | \ 208 FTSDMC021_CR1_MBW(2) | \ 209 FTSDMC021_CR1_BNKSIZE(6)) 210 211 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 212 FTSDMC021_CR2_IREF | \ 213 FTSDMC021_CR2_ISMR) 214 215 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 216 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 217 CONFIG_SYS_FTSDMC021_BANK0_BASE) 218 219 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 220 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 221 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 222 CONFIG_SYS_FTSDMC021_BANK1_BASE) 223 #endif 224 225 /* 226 * Physical Memory Map 227 */ 228 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 229 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 230 #else 231 #ifdef CONFIG_MEM_REMAP 232 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 233 #else 234 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ 235 #endif 236 #endif 237 238 #define PHYS_SDRAM_1 \ 239 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 240 241 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 242 243 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 244 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 245 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 246 #else 247 #ifdef CONFIG_MEM_REMAP 248 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 249 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 250 #else 251 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ 252 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 253 #endif 254 #endif 255 256 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 257 258 #ifdef CONFIG_MEM_REMAP 259 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 260 GENERATED_GBL_DATA_SIZE) 261 #else 262 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 263 GENERATED_GBL_DATA_SIZE) 264 #endif /* CONFIG_MEM_REMAP */ 265 266 /* 267 * Load address and memory test area should agree with 268 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 269 */ 270 #define CONFIG_SYS_LOAD_ADDR 0x300000 271 272 /* memtest works on 63 MB in DRAM */ 273 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 274 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 275 276 /* 277 * Static memory controller configuration 278 */ 279 #define CONFIG_FTSMC020 280 281 #ifdef CONFIG_FTSMC020 282 #include <faraday/ftsmc020.h> 283 284 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 285 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 286 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 287 } 288 289 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 290 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 291 FTSMC020_BANK_SIZE_32M | \ 292 FTSMC020_BANK_MBW_32) 293 294 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 295 FTSMC020_TPR_AST(1) | \ 296 FTSMC020_TPR_CTW(1) | \ 297 FTSMC020_TPR_ATI(1) | \ 298 FTSMC020_TPR_AT2(1) | \ 299 FTSMC020_TPR_WTC(1) | \ 300 FTSMC020_TPR_AHT(1) | \ 301 FTSMC020_TPR_TRNA(1)) 302 #endif 303 304 /* 305 * FLASH on ADP_AG101P is connected to BANK0 306 * Just disalbe the other BANK to avoid detection error. 307 */ 308 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 309 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 310 FTSMC020_BANK_SIZE_32M | \ 311 FTSMC020_BANK_MBW_32) 312 313 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 314 FTSMC020_TPR_CTW(3) | \ 315 FTSMC020_TPR_ATI(0xf) | \ 316 FTSMC020_TPR_AT2(3) | \ 317 FTSMC020_TPR_WTC(3) | \ 318 FTSMC020_TPR_AHT(3) | \ 319 FTSMC020_TPR_TRNA(0xf)) 320 321 #define FTSMC020_BANK1_CONFIG (0x00) 322 #define FTSMC020_BANK1_TIMING (0x00) 323 #endif /* CONFIG_FTSMC020 */ 324 325 /* 326 * FLASH and environment organization 327 */ 328 /* use CFI framework */ 329 #define CONFIG_SYS_FLASH_CFI 330 #define CONFIG_FLASH_CFI_DRIVER 331 332 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 333 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 334 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 335 336 /* support JEDEC */ 337 338 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 339 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 340 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 341 #else 342 #ifdef CONFIG_MEM_REMAP 343 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 344 #else 345 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 346 #endif 347 #endif /* CONFIG_MEM_REMAP */ 348 349 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 350 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 351 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 352 353 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 354 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 355 356 /* max number of memory banks */ 357 /* 358 * There are 4 banks supported for this Controller, 359 * but we have only 1 bank connected to flash on board 360 */ 361 #define CONFIG_SYS_MAX_FLASH_BANKS 1 362 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 363 364 /* max number of sectors on one chip */ 365 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 366 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 367 #define CONFIG_SYS_MAX_FLASH_SECT 512 368 369 /* environments */ 370 #define CONFIG_ENV_IS_IN_FLASH 371 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 372 #define CONFIG_ENV_SIZE 8192 373 #define CONFIG_ENV_OVERWRITE 374 375 #endif /* __CONFIG_H */ 376