16cb144bcSMacpaul Lin /* 26cb144bcSMacpaul Lin * Copyright (C) 2011 Andes Technology Corporation 36cb144bcSMacpaul Lin * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 46cb144bcSMacpaul Lin * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 56cb144bcSMacpaul Lin * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 76cb144bcSMacpaul Lin */ 86cb144bcSMacpaul Lin 96cb144bcSMacpaul Lin #ifndef __CONFIG_H 106cb144bcSMacpaul Lin #define __CONFIG_H 116cb144bcSMacpaul Lin 127e3f94e1SMasahiro Yamada #include <asm/arch-ag101/ag101.h> 136cb144bcSMacpaul Lin 146cb144bcSMacpaul Lin /* 156cb144bcSMacpaul Lin * CPU and Board Configuration Options 166cb144bcSMacpaul Lin */ 176cb144bcSMacpaul Lin #define CONFIG_ADP_AG101P 186cb144bcSMacpaul Lin 196cb144bcSMacpaul Lin #define CONFIG_USE_INTERRUPT 206cb144bcSMacpaul Lin 216cb144bcSMacpaul Lin #define CONFIG_SKIP_LOWLEVEL_INIT 226cb144bcSMacpaul Lin 23b841b6e9Srick #define CONFIG_CMDLINE_EDITING 24b841b6e9Srick 25*e336b73dSrick #define CONFIG_ARCH_MAP_SYSMEM 26b841b6e9Srick 27b841b6e9Srick #define CONFIG_BOOTP_SEND_HOSTNAME 28b841b6e9Srick #define CONFIG_BOOTP_SERVERIP 29e3c58b02Sken kuo 306cb144bcSMacpaul Lin #ifndef CONFIG_SKIP_LOWLEVEL_INIT 316cb144bcSMacpaul Lin #define CONFIG_MEM_REMAP 326cb144bcSMacpaul Lin #endif 336cb144bcSMacpaul Lin 346cb144bcSMacpaul Lin #ifdef CONFIG_SKIP_LOWLEVEL_INIT 352e88bb28SKun-Hua Huang #define CONFIG_SYS_TEXT_BASE 0x00500000 3686132af7Srick #ifdef CONFIG_OF_CONTROL 3786132af7Srick #undef CONFIG_OF_SEPARATE 3886132af7Srick #define CONFIG_OF_EMBED 3986132af7Srick #endif 402e88bb28SKun-Hua Huang #else 412e88bb28SKun-Hua Huang #ifdef CONFIG_MEM_REMAP 422e88bb28SKun-Hua Huang #define CONFIG_SYS_TEXT_BASE 0x80000000 436cb144bcSMacpaul Lin #else 446cb144bcSMacpaul Lin #define CONFIG_SYS_TEXT_BASE 0x00000000 456cb144bcSMacpaul Lin #endif 462e88bb28SKun-Hua Huang #endif 476cb144bcSMacpaul Lin 486cb144bcSMacpaul Lin /* 496cb144bcSMacpaul Lin * Timer 506cb144bcSMacpaul Lin */ 516cb144bcSMacpaul Lin #define CONFIG_SYS_CLK_FREQ 39062500 526cb144bcSMacpaul Lin #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 536cb144bcSMacpaul Lin 546cb144bcSMacpaul Lin /* 556cb144bcSMacpaul Lin * Use Externel CLOCK or PCLK 566cb144bcSMacpaul Lin */ 576cb144bcSMacpaul Lin #undef CONFIG_FTRTC010_EXTCLK 586cb144bcSMacpaul Lin 596cb144bcSMacpaul Lin #ifndef CONFIG_FTRTC010_EXTCLK 606cb144bcSMacpaul Lin #define CONFIG_FTRTC010_PCLK 616cb144bcSMacpaul Lin #endif 626cb144bcSMacpaul Lin 636cb144bcSMacpaul Lin #ifdef CONFIG_FTRTC010_EXTCLK 646cb144bcSMacpaul Lin #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 656cb144bcSMacpaul Lin #else 666cb144bcSMacpaul Lin #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 676cb144bcSMacpaul Lin #endif 686cb144bcSMacpaul Lin 696cb144bcSMacpaul Lin #define TIMER_LOAD_VAL 0xffffffff 706cb144bcSMacpaul Lin 716cb144bcSMacpaul Lin /* 726cb144bcSMacpaul Lin * Real Time Clock 736cb144bcSMacpaul Lin */ 746cb144bcSMacpaul Lin #define CONFIG_RTC_FTRTC010 756cb144bcSMacpaul Lin 766cb144bcSMacpaul Lin /* 776cb144bcSMacpaul Lin * Real Time Clock Divider 786cb144bcSMacpaul Lin * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 796cb144bcSMacpaul Lin */ 806cb144bcSMacpaul Lin #define OSC_5MHZ (5*1000000) 816cb144bcSMacpaul Lin #define OSC_CLK (4*OSC_5MHZ) 826cb144bcSMacpaul Lin #define RTC_DIV_COUNT (0.5) /* Why?? */ 836cb144bcSMacpaul Lin 846cb144bcSMacpaul Lin /* 856cb144bcSMacpaul Lin * Serial console configuration 866cb144bcSMacpaul Lin */ 876cb144bcSMacpaul Lin 886cb144bcSMacpaul Lin /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 896cb144bcSMacpaul Lin #define CONFIG_CONS_INDEX 1 906cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_SERIAL 916cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 9286132af7Srick #ifndef CONFIG_DM_SERIAL 936cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_REG_SIZE -4 9486132af7Srick #endif 956cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 966cb144bcSMacpaul Lin 976cb144bcSMacpaul Lin /* 986cb144bcSMacpaul Lin * SD (MMC) controller 996cb144bcSMacpaul Lin */ 1006cb144bcSMacpaul Lin #define CONFIG_FTSDC010 1016cb144bcSMacpaul Lin #define CONFIG_FTSDC010_NUMBER 1 10261ccf082Sken kuo #define CONFIG_FTSDC010_SDIO 1036cb144bcSMacpaul Lin 1046cb144bcSMacpaul Lin /* 1056cb144bcSMacpaul Lin * Miscellaneous configurable options 1066cb144bcSMacpaul Lin */ 1076cb144bcSMacpaul Lin #define CONFIG_SYS_LONGHELP /* undef to save memory */ 1086cb144bcSMacpaul Lin 1096cb144bcSMacpaul Lin /* 1106cb144bcSMacpaul Lin * Size of malloc() pool 1116cb144bcSMacpaul Lin */ 1126cb144bcSMacpaul Lin /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 1136cb144bcSMacpaul Lin #define CONFIG_SYS_MALLOC_LEN (512 << 10) 1146cb144bcSMacpaul Lin 1156cb144bcSMacpaul Lin /* 1166cb144bcSMacpaul Lin * AHB Controller configuration 1176cb144bcSMacpaul Lin */ 1186cb144bcSMacpaul Lin #define CONFIG_FTAHBC020S 1196cb144bcSMacpaul Lin 1206cb144bcSMacpaul Lin #ifdef CONFIG_FTAHBC020S 1216cb144bcSMacpaul Lin #include <faraday/ftahbc020s.h> 1226cb144bcSMacpaul Lin 1236cb144bcSMacpaul Lin /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 1246cb144bcSMacpaul Lin #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 1256cb144bcSMacpaul Lin 1266cb144bcSMacpaul Lin /* 1276cb144bcSMacpaul Lin * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 1286cb144bcSMacpaul Lin * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 1296cb144bcSMacpaul Lin * in C language. 1306cb144bcSMacpaul Lin */ 1316cb144bcSMacpaul Lin #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 1326cb144bcSMacpaul Lin (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 1336cb144bcSMacpaul Lin FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 1346cb144bcSMacpaul Lin #endif 1356cb144bcSMacpaul Lin 1366cb144bcSMacpaul Lin /* 1376cb144bcSMacpaul Lin * Watchdog 1386cb144bcSMacpaul Lin */ 1396cb144bcSMacpaul Lin #define CONFIG_FTWDT010_WATCHDOG 1406cb144bcSMacpaul Lin 1416cb144bcSMacpaul Lin /* 1426cb144bcSMacpaul Lin * PMU Power controller configuration 1436cb144bcSMacpaul Lin */ 1446cb144bcSMacpaul Lin #define CONFIG_PMU 1456cb144bcSMacpaul Lin #define CONFIG_FTPMU010_POWER 1466cb144bcSMacpaul Lin 1476cb144bcSMacpaul Lin #ifdef CONFIG_FTPMU010_POWER 1486cb144bcSMacpaul Lin #include <faraday/ftpmu010.h> 1496cb144bcSMacpaul Lin #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 1506cb144bcSMacpaul Lin #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 1516cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 1526cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 1536cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 1546cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_CKE_DCSR | \ 1556cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_DQM_DCSR | \ 1566cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_SDCLK_DCSR) 1576cb144bcSMacpaul Lin #endif 1586cb144bcSMacpaul Lin 1596cb144bcSMacpaul Lin /* 1606cb144bcSMacpaul Lin * SDRAM controller configuration 1616cb144bcSMacpaul Lin */ 1626cb144bcSMacpaul Lin #define CONFIG_FTSDMC021 1636cb144bcSMacpaul Lin 1646cb144bcSMacpaul Lin #ifdef CONFIG_FTSDMC021 1656cb144bcSMacpaul Lin #include <faraday/ftsdmc021.h> 1666cb144bcSMacpaul Lin 1676cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 1686cb144bcSMacpaul Lin FTSDMC021_TP1_TRP(1) | \ 1696cb144bcSMacpaul Lin FTSDMC021_TP1_TRCD(1) | \ 1706cb144bcSMacpaul Lin FTSDMC021_TP1_TRF(3) | \ 1716cb144bcSMacpaul Lin FTSDMC021_TP1_TWR(1) | \ 1726cb144bcSMacpaul Lin FTSDMC021_TP1_TCL(2)) 1736cb144bcSMacpaul Lin 1746cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 1756cb144bcSMacpaul Lin FTSDMC021_TP2_INI_REFT(8) | \ 1766cb144bcSMacpaul Lin FTSDMC021_TP2_REF_INTV(0x180)) 1776cb144bcSMacpaul Lin 1786cb144bcSMacpaul Lin /* 1796cb144bcSMacpaul Lin * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 1806cb144bcSMacpaul Lin * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 1816cb144bcSMacpaul Lin * C language. 1826cb144bcSMacpaul Lin */ 1836cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 1846cb144bcSMacpaul Lin FTSDMC021_CR1_DSZ(3) | \ 1856cb144bcSMacpaul Lin FTSDMC021_CR1_MBW(2) | \ 1866cb144bcSMacpaul Lin FTSDMC021_CR1_BNKSIZE(6)) 1876cb144bcSMacpaul Lin 1886cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 1896cb144bcSMacpaul Lin FTSDMC021_CR2_IREF | \ 1906cb144bcSMacpaul Lin FTSDMC021_CR2_ISMR) 1916cb144bcSMacpaul Lin 1926cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 1936cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 1946cb144bcSMacpaul Lin CONFIG_SYS_FTSDMC021_BANK0_BASE) 1956cb144bcSMacpaul Lin 1963c016704Sken kuo #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 1973c016704Sken kuo (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 1983c016704Sken kuo #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 1993c016704Sken kuo CONFIG_SYS_FTSDMC021_BANK1_BASE) 2006cb144bcSMacpaul Lin #endif 2016cb144bcSMacpaul Lin 2026cb144bcSMacpaul Lin /* 2036cb144bcSMacpaul Lin * Physical Memory Map 2046cb144bcSMacpaul Lin */ 2052e88bb28SKun-Hua Huang #ifdef CONFIG_SKIP_LOWLEVEL_INIT 2066cb144bcSMacpaul Lin #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 2072e88bb28SKun-Hua Huang #else 2082e88bb28SKun-Hua Huang #ifdef CONFIG_MEM_REMAP 2092e88bb28SKun-Hua Huang #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 2102e88bb28SKun-Hua Huang #else 2112e88bb28SKun-Hua Huang #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ 2126cb144bcSMacpaul Lin #endif 2136cb144bcSMacpaul Lin #endif 2142e88bb28SKun-Hua Huang 2153c016704Sken kuo #define PHYS_SDRAM_1 \ 2163c016704Sken kuo (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 2176cb144bcSMacpaul Lin 2183c016704Sken kuo #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 2192e88bb28SKun-Hua Huang 2202e88bb28SKun-Hua Huang #ifdef CONFIG_SKIP_LOWLEVEL_INIT 2212e88bb28SKun-Hua Huang #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 2222e88bb28SKun-Hua Huang #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 2232e88bb28SKun-Hua Huang #else 2242e88bb28SKun-Hua Huang #ifdef CONFIG_MEM_REMAP 2252e88bb28SKun-Hua Huang #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 2262e88bb28SKun-Hua Huang #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 2272e88bb28SKun-Hua Huang #else 2282e88bb28SKun-Hua Huang #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ 2292e88bb28SKun-Hua Huang #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 2302e88bb28SKun-Hua Huang #endif 2312e88bb28SKun-Hua Huang #endif 2326cb144bcSMacpaul Lin 2336cb144bcSMacpaul Lin #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 2346cb144bcSMacpaul Lin 2356cb144bcSMacpaul Lin #ifdef CONFIG_MEM_REMAP 2366cb144bcSMacpaul Lin #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 2376cb144bcSMacpaul Lin GENERATED_GBL_DATA_SIZE) 2386cb144bcSMacpaul Lin #else 2396cb144bcSMacpaul Lin #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 2406cb144bcSMacpaul Lin GENERATED_GBL_DATA_SIZE) 2416cb144bcSMacpaul Lin #endif /* CONFIG_MEM_REMAP */ 2426cb144bcSMacpaul Lin 2436cb144bcSMacpaul Lin /* 2446cb144bcSMacpaul Lin * Load address and memory test area should agree with 245a187559eSBin Meng * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 2466cb144bcSMacpaul Lin */ 2476cb144bcSMacpaul Lin #define CONFIG_SYS_LOAD_ADDR 0x300000 2486cb144bcSMacpaul Lin 2496cb144bcSMacpaul Lin /* memtest works on 63 MB in DRAM */ 2506cb144bcSMacpaul Lin #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 2516cb144bcSMacpaul Lin #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 2526cb144bcSMacpaul Lin 2536cb144bcSMacpaul Lin /* 2546cb144bcSMacpaul Lin * Static memory controller configuration 2556cb144bcSMacpaul Lin */ 2566cb144bcSMacpaul Lin #define CONFIG_FTSMC020 2576cb144bcSMacpaul Lin 2586cb144bcSMacpaul Lin #ifdef CONFIG_FTSMC020 2596cb144bcSMacpaul Lin #include <faraday/ftsmc020.h> 2606cb144bcSMacpaul Lin 2616cb144bcSMacpaul Lin #define CONFIG_SYS_FTSMC020_CONFIGS { \ 2626cb144bcSMacpaul Lin { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 2636cb144bcSMacpaul Lin { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 2646cb144bcSMacpaul Lin } 2656cb144bcSMacpaul Lin 2666cb144bcSMacpaul Lin #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 2676cb144bcSMacpaul Lin #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 2686cb144bcSMacpaul Lin FTSMC020_BANK_SIZE_32M | \ 2696cb144bcSMacpaul Lin FTSMC020_BANK_MBW_32) 2706cb144bcSMacpaul Lin 2716cb144bcSMacpaul Lin #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 2726cb144bcSMacpaul Lin FTSMC020_TPR_AST(1) | \ 2736cb144bcSMacpaul Lin FTSMC020_TPR_CTW(1) | \ 2746cb144bcSMacpaul Lin FTSMC020_TPR_ATI(1) | \ 2756cb144bcSMacpaul Lin FTSMC020_TPR_AT2(1) | \ 2766cb144bcSMacpaul Lin FTSMC020_TPR_WTC(1) | \ 2776cb144bcSMacpaul Lin FTSMC020_TPR_AHT(1) | \ 2786cb144bcSMacpaul Lin FTSMC020_TPR_TRNA(1)) 2796cb144bcSMacpaul Lin #endif 2806cb144bcSMacpaul Lin 2816cb144bcSMacpaul Lin /* 2826cb144bcSMacpaul Lin * FLASH on ADP_AG101P is connected to BANK0 2836cb144bcSMacpaul Lin * Just disalbe the other BANK to avoid detection error. 2846cb144bcSMacpaul Lin */ 2856cb144bcSMacpaul Lin #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 2866cb144bcSMacpaul Lin FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 2876cb144bcSMacpaul Lin FTSMC020_BANK_SIZE_32M | \ 2886cb144bcSMacpaul Lin FTSMC020_BANK_MBW_32) 2896cb144bcSMacpaul Lin 2906cb144bcSMacpaul Lin #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 2916cb144bcSMacpaul Lin FTSMC020_TPR_CTW(3) | \ 2926cb144bcSMacpaul Lin FTSMC020_TPR_ATI(0xf) | \ 2936cb144bcSMacpaul Lin FTSMC020_TPR_AT2(3) | \ 2946cb144bcSMacpaul Lin FTSMC020_TPR_WTC(3) | \ 2956cb144bcSMacpaul Lin FTSMC020_TPR_AHT(3) | \ 2966cb144bcSMacpaul Lin FTSMC020_TPR_TRNA(0xf)) 2976cb144bcSMacpaul Lin 2986cb144bcSMacpaul Lin #define FTSMC020_BANK1_CONFIG (0x00) 2996cb144bcSMacpaul Lin #define FTSMC020_BANK1_TIMING (0x00) 3006cb144bcSMacpaul Lin #endif /* CONFIG_FTSMC020 */ 3016cb144bcSMacpaul Lin 3026cb144bcSMacpaul Lin /* 3036cb144bcSMacpaul Lin * FLASH and environment organization 3046cb144bcSMacpaul Lin */ 3056cb144bcSMacpaul Lin /* use CFI framework */ 3066cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_CFI 3076cb144bcSMacpaul Lin #define CONFIG_FLASH_CFI_DRIVER 3086cb144bcSMacpaul Lin 3096cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 3106cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 3112e88bb28SKun-Hua Huang #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 3126cb144bcSMacpaul Lin 3136cb144bcSMacpaul Lin /* support JEDEC */ 3146cb144bcSMacpaul Lin 3156cb144bcSMacpaul Lin /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 3166cb144bcSMacpaul Lin #ifdef CONFIG_SKIP_LOWLEVEL_INIT 3172e88bb28SKun-Hua Huang #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 3182e88bb28SKun-Hua Huang #else 3196cb144bcSMacpaul Lin #ifdef CONFIG_MEM_REMAP 3206cb144bcSMacpaul Lin #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 3216cb144bcSMacpaul Lin #else 3226cb144bcSMacpaul Lin #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 3232e88bb28SKun-Hua Huang #endif 3246cb144bcSMacpaul Lin #endif /* CONFIG_MEM_REMAP */ 3256cb144bcSMacpaul Lin 3266cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 3276cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 3286cb144bcSMacpaul Lin #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 3296cb144bcSMacpaul Lin 3306cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 3316cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 3326cb144bcSMacpaul Lin 3336cb144bcSMacpaul Lin /* max number of memory banks */ 3346cb144bcSMacpaul Lin /* 3356cb144bcSMacpaul Lin * There are 4 banks supported for this Controller, 3366cb144bcSMacpaul Lin * but we have only 1 bank connected to flash on board 3376cb144bcSMacpaul Lin */ 338b841b6e9Srick #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 3396cb144bcSMacpaul Lin #define CONFIG_SYS_MAX_FLASH_BANKS 1 340b841b6e9Srick #endif 3412e88bb28SKun-Hua Huang #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 3426cb144bcSMacpaul Lin 3436cb144bcSMacpaul Lin /* max number of sectors on one chip */ 3442e88bb28SKun-Hua Huang #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 3456cb144bcSMacpaul Lin #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 3462e88bb28SKun-Hua Huang #define CONFIG_SYS_MAX_FLASH_SECT 512 3476cb144bcSMacpaul Lin 3486cb144bcSMacpaul Lin /* environments */ 3496cb144bcSMacpaul Lin #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 3506cb144bcSMacpaul Lin #define CONFIG_ENV_SIZE 8192 3516cb144bcSMacpaul Lin #define CONFIG_ENV_OVERWRITE 3526cb144bcSMacpaul Lin 353b841b6e9Srick /* 354b841b6e9Srick * For booting Linux, the board info and command line data 355b841b6e9Srick * have to be in the first 16 MB of memory, since this is 356b841b6e9Srick * the maximum mapped by the Linux kernel during initialization. 357b841b6e9Srick */ 358b841b6e9Srick 359b841b6e9Srick /* Initial Memory map for Linux*/ 360b841b6e9Srick #define CONFIG_SYS_BOOTMAPSZ (64 << 20) 361b841b6e9Srick /* Increase max gunzip size */ 362b841b6e9Srick #define CONFIG_SYS_BOOTM_LEN (64 << 20) 363b841b6e9Srick 3646cb144bcSMacpaul Lin #endif /* __CONFIG_H */ 365