1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 26cb144bcSMacpaul Lin /* 36cb144bcSMacpaul Lin * Copyright (C) 2011 Andes Technology Corporation 46cb144bcSMacpaul Lin * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 56cb144bcSMacpaul Lin * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 66cb144bcSMacpaul Lin */ 76cb144bcSMacpaul Lin 86cb144bcSMacpaul Lin #ifndef __CONFIG_H 96cb144bcSMacpaul Lin #define __CONFIG_H 106cb144bcSMacpaul Lin 117e3f94e1SMasahiro Yamada #include <asm/arch-ag101/ag101.h> 126cb144bcSMacpaul Lin 136cb144bcSMacpaul Lin /* 146cb144bcSMacpaul Lin * CPU and Board Configuration Options 156cb144bcSMacpaul Lin */ 166cb144bcSMacpaul Lin #define CONFIG_USE_INTERRUPT 176cb144bcSMacpaul Lin 186cb144bcSMacpaul Lin #define CONFIG_SKIP_LOWLEVEL_INIT 196cb144bcSMacpaul Lin 20e336b73dSrick #define CONFIG_ARCH_MAP_SYSMEM 21b841b6e9Srick 22b841b6e9Srick #define CONFIG_BOOTP_SEND_HOSTNAME 23b841b6e9Srick #define CONFIG_BOOTP_SERVERIP 24e3c58b02Sken kuo 256cb144bcSMacpaul Lin #ifndef CONFIG_SKIP_LOWLEVEL_INIT 266cb144bcSMacpaul Lin #define CONFIG_MEM_REMAP 276cb144bcSMacpaul Lin #endif 286cb144bcSMacpaul Lin 296cb144bcSMacpaul Lin #ifdef CONFIG_SKIP_LOWLEVEL_INIT 3086132af7Srick #ifdef CONFIG_OF_CONTROL 3186132af7Srick #undef CONFIG_OF_SEPARATE 3286132af7Srick #define CONFIG_OF_EMBED 3386132af7Srick #endif 342e88bb28SKun-Hua Huang #endif 356cb144bcSMacpaul Lin 366cb144bcSMacpaul Lin /* 376cb144bcSMacpaul Lin * Timer 386cb144bcSMacpaul Lin */ 396cb144bcSMacpaul Lin #define CONFIG_SYS_CLK_FREQ 39062500 406cb144bcSMacpaul Lin #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 416cb144bcSMacpaul Lin 426cb144bcSMacpaul Lin /* 436cb144bcSMacpaul Lin * Use Externel CLOCK or PCLK 446cb144bcSMacpaul Lin */ 456cb144bcSMacpaul Lin #undef CONFIG_FTRTC010_EXTCLK 466cb144bcSMacpaul Lin 476cb144bcSMacpaul Lin #ifndef CONFIG_FTRTC010_EXTCLK 486cb144bcSMacpaul Lin #define CONFIG_FTRTC010_PCLK 496cb144bcSMacpaul Lin #endif 506cb144bcSMacpaul Lin 516cb144bcSMacpaul Lin #ifdef CONFIG_FTRTC010_EXTCLK 526cb144bcSMacpaul Lin #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 536cb144bcSMacpaul Lin #else 546cb144bcSMacpaul Lin #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 556cb144bcSMacpaul Lin #endif 566cb144bcSMacpaul Lin 576cb144bcSMacpaul Lin #define TIMER_LOAD_VAL 0xffffffff 586cb144bcSMacpaul Lin 596cb144bcSMacpaul Lin /* 606cb144bcSMacpaul Lin * Real Time Clock 616cb144bcSMacpaul Lin */ 626cb144bcSMacpaul Lin #define CONFIG_RTC_FTRTC010 636cb144bcSMacpaul Lin 646cb144bcSMacpaul Lin /* 656cb144bcSMacpaul Lin * Real Time Clock Divider 666cb144bcSMacpaul Lin * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 676cb144bcSMacpaul Lin */ 686cb144bcSMacpaul Lin #define OSC_5MHZ (5*1000000) 696cb144bcSMacpaul Lin #define OSC_CLK (4*OSC_5MHZ) 706cb144bcSMacpaul Lin #define RTC_DIV_COUNT (0.5) /* Why?? */ 716cb144bcSMacpaul Lin 726cb144bcSMacpaul Lin /* 736cb144bcSMacpaul Lin * Serial console configuration 746cb144bcSMacpaul Lin */ 756cb144bcSMacpaul Lin 766cb144bcSMacpaul Lin /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 776cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_SERIAL 786cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 7986132af7Srick #ifndef CONFIG_DM_SERIAL 806cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_REG_SIZE -4 8186132af7Srick #endif 826cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 836cb144bcSMacpaul Lin 846cb144bcSMacpaul Lin /* 856cb144bcSMacpaul Lin * Miscellaneous configurable options 866cb144bcSMacpaul Lin */ 876cb144bcSMacpaul Lin 886cb144bcSMacpaul Lin /* 896cb144bcSMacpaul Lin * Size of malloc() pool 906cb144bcSMacpaul Lin */ 916cb144bcSMacpaul Lin /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 926cb144bcSMacpaul Lin #define CONFIG_SYS_MALLOC_LEN (512 << 10) 936cb144bcSMacpaul Lin 946cb144bcSMacpaul Lin /* 956cb144bcSMacpaul Lin * AHB Controller configuration 966cb144bcSMacpaul Lin */ 976cb144bcSMacpaul Lin #define CONFIG_FTAHBC020S 986cb144bcSMacpaul Lin 996cb144bcSMacpaul Lin #ifdef CONFIG_FTAHBC020S 1006cb144bcSMacpaul Lin #include <faraday/ftahbc020s.h> 1016cb144bcSMacpaul Lin 1026cb144bcSMacpaul Lin /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 1036cb144bcSMacpaul Lin #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 1046cb144bcSMacpaul Lin 1056cb144bcSMacpaul Lin /* 1066cb144bcSMacpaul Lin * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 1076cb144bcSMacpaul Lin * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 1086cb144bcSMacpaul Lin * in C language. 1096cb144bcSMacpaul Lin */ 1106cb144bcSMacpaul Lin #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 1116cb144bcSMacpaul Lin (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 1126cb144bcSMacpaul Lin FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 1136cb144bcSMacpaul Lin #endif 1146cb144bcSMacpaul Lin 1156cb144bcSMacpaul Lin /* 1166cb144bcSMacpaul Lin * Watchdog 1176cb144bcSMacpaul Lin */ 1186cb144bcSMacpaul Lin #define CONFIG_FTWDT010_WATCHDOG 1196cb144bcSMacpaul Lin 1206cb144bcSMacpaul Lin /* 1216cb144bcSMacpaul Lin * PMU Power controller configuration 1226cb144bcSMacpaul Lin */ 1236cb144bcSMacpaul Lin #define CONFIG_PMU 1246cb144bcSMacpaul Lin #define CONFIG_FTPMU010_POWER 1256cb144bcSMacpaul Lin 1266cb144bcSMacpaul Lin #ifdef CONFIG_FTPMU010_POWER 1276cb144bcSMacpaul Lin #include <faraday/ftpmu010.h> 1286cb144bcSMacpaul Lin #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 1296cb144bcSMacpaul Lin #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 1306cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 1316cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 1326cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 1336cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_CKE_DCSR | \ 1346cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_DQM_DCSR | \ 1356cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_SDCLK_DCSR) 1366cb144bcSMacpaul Lin #endif 1376cb144bcSMacpaul Lin 1386cb144bcSMacpaul Lin /* 1396cb144bcSMacpaul Lin * SDRAM controller configuration 1406cb144bcSMacpaul Lin */ 1416cb144bcSMacpaul Lin #define CONFIG_FTSDMC021 1426cb144bcSMacpaul Lin 1436cb144bcSMacpaul Lin #ifdef CONFIG_FTSDMC021 1446cb144bcSMacpaul Lin #include <faraday/ftsdmc021.h> 1456cb144bcSMacpaul Lin 1466cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 1476cb144bcSMacpaul Lin FTSDMC021_TP1_TRP(1) | \ 1486cb144bcSMacpaul Lin FTSDMC021_TP1_TRCD(1) | \ 1496cb144bcSMacpaul Lin FTSDMC021_TP1_TRF(3) | \ 1506cb144bcSMacpaul Lin FTSDMC021_TP1_TWR(1) | \ 1516cb144bcSMacpaul Lin FTSDMC021_TP1_TCL(2)) 1526cb144bcSMacpaul Lin 1536cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 1546cb144bcSMacpaul Lin FTSDMC021_TP2_INI_REFT(8) | \ 1556cb144bcSMacpaul Lin FTSDMC021_TP2_REF_INTV(0x180)) 1566cb144bcSMacpaul Lin 1576cb144bcSMacpaul Lin /* 1586cb144bcSMacpaul Lin * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 1596cb144bcSMacpaul Lin * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 1606cb144bcSMacpaul Lin * C language. 1616cb144bcSMacpaul Lin */ 1626cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 1636cb144bcSMacpaul Lin FTSDMC021_CR1_DSZ(3) | \ 1646cb144bcSMacpaul Lin FTSDMC021_CR1_MBW(2) | \ 1656cb144bcSMacpaul Lin FTSDMC021_CR1_BNKSIZE(6)) 1666cb144bcSMacpaul Lin 1676cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 1686cb144bcSMacpaul Lin FTSDMC021_CR2_IREF | \ 1696cb144bcSMacpaul Lin FTSDMC021_CR2_ISMR) 1706cb144bcSMacpaul Lin 1716cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 1726cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 1736cb144bcSMacpaul Lin CONFIG_SYS_FTSDMC021_BANK0_BASE) 1746cb144bcSMacpaul Lin 1753c016704Sken kuo #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 1763c016704Sken kuo (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 1773c016704Sken kuo #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 1783c016704Sken kuo CONFIG_SYS_FTSDMC021_BANK1_BASE) 1796cb144bcSMacpaul Lin #endif 1806cb144bcSMacpaul Lin 1816cb144bcSMacpaul Lin /* 1826cb144bcSMacpaul Lin * Physical Memory Map 1836cb144bcSMacpaul Lin */ 1842e88bb28SKun-Hua Huang #ifdef CONFIG_SKIP_LOWLEVEL_INIT 1856cb144bcSMacpaul Lin #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 1862e88bb28SKun-Hua Huang #else 1872e88bb28SKun-Hua Huang #ifdef CONFIG_MEM_REMAP 1882e88bb28SKun-Hua Huang #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 1892e88bb28SKun-Hua Huang #else 1902e88bb28SKun-Hua Huang #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ 1916cb144bcSMacpaul Lin #endif 1926cb144bcSMacpaul Lin #endif 1932e88bb28SKun-Hua Huang 1943c016704Sken kuo #define PHYS_SDRAM_1 \ 1953c016704Sken kuo (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 1966cb144bcSMacpaul Lin 1972e88bb28SKun-Hua Huang #ifdef CONFIG_SKIP_LOWLEVEL_INIT 1982e88bb28SKun-Hua Huang #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 1992e88bb28SKun-Hua Huang #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 2002e88bb28SKun-Hua Huang #else 2012e88bb28SKun-Hua Huang #ifdef CONFIG_MEM_REMAP 2022e88bb28SKun-Hua Huang #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 2032e88bb28SKun-Hua Huang #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 2042e88bb28SKun-Hua Huang #else 2052e88bb28SKun-Hua Huang #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ 2062e88bb28SKun-Hua Huang #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 2072e88bb28SKun-Hua Huang #endif 2082e88bb28SKun-Hua Huang #endif 2096cb144bcSMacpaul Lin 2106cb144bcSMacpaul Lin #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 2116cb144bcSMacpaul Lin 2126cb144bcSMacpaul Lin #ifdef CONFIG_MEM_REMAP 2136cb144bcSMacpaul Lin #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 2146cb144bcSMacpaul Lin GENERATED_GBL_DATA_SIZE) 2156cb144bcSMacpaul Lin #else 2166cb144bcSMacpaul Lin #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 2176cb144bcSMacpaul Lin GENERATED_GBL_DATA_SIZE) 2186cb144bcSMacpaul Lin #endif /* CONFIG_MEM_REMAP */ 2196cb144bcSMacpaul Lin 2206cb144bcSMacpaul Lin /* 2216cb144bcSMacpaul Lin * Load address and memory test area should agree with 222a187559eSBin Meng * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 2236cb144bcSMacpaul Lin */ 2246cb144bcSMacpaul Lin #define CONFIG_SYS_LOAD_ADDR 0x300000 2256cb144bcSMacpaul Lin 2266cb144bcSMacpaul Lin /* memtest works on 63 MB in DRAM */ 2276cb144bcSMacpaul Lin #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 2286cb144bcSMacpaul Lin #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 2296cb144bcSMacpaul Lin 2306cb144bcSMacpaul Lin /* 2316cb144bcSMacpaul Lin * Static memory controller configuration 2326cb144bcSMacpaul Lin */ 2336cb144bcSMacpaul Lin #define CONFIG_FTSMC020 2346cb144bcSMacpaul Lin 2356cb144bcSMacpaul Lin #ifdef CONFIG_FTSMC020 2366cb144bcSMacpaul Lin #include <faraday/ftsmc020.h> 2376cb144bcSMacpaul Lin 2386cb144bcSMacpaul Lin #define CONFIG_SYS_FTSMC020_CONFIGS { \ 2396cb144bcSMacpaul Lin { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 2406cb144bcSMacpaul Lin { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 2416cb144bcSMacpaul Lin } 2426cb144bcSMacpaul Lin 2436cb144bcSMacpaul Lin #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 2446cb144bcSMacpaul Lin #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 2456cb144bcSMacpaul Lin FTSMC020_BANK_SIZE_32M | \ 2466cb144bcSMacpaul Lin FTSMC020_BANK_MBW_32) 2476cb144bcSMacpaul Lin 2486cb144bcSMacpaul Lin #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 2496cb144bcSMacpaul Lin FTSMC020_TPR_AST(1) | \ 2506cb144bcSMacpaul Lin FTSMC020_TPR_CTW(1) | \ 2516cb144bcSMacpaul Lin FTSMC020_TPR_ATI(1) | \ 2526cb144bcSMacpaul Lin FTSMC020_TPR_AT2(1) | \ 2536cb144bcSMacpaul Lin FTSMC020_TPR_WTC(1) | \ 2546cb144bcSMacpaul Lin FTSMC020_TPR_AHT(1) | \ 2556cb144bcSMacpaul Lin FTSMC020_TPR_TRNA(1)) 2566cb144bcSMacpaul Lin #endif 2576cb144bcSMacpaul Lin 2586cb144bcSMacpaul Lin /* 2596cb144bcSMacpaul Lin * FLASH on ADP_AG101P is connected to BANK0 2606cb144bcSMacpaul Lin * Just disalbe the other BANK to avoid detection error. 2616cb144bcSMacpaul Lin */ 2626cb144bcSMacpaul Lin #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 2636cb144bcSMacpaul Lin FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 2646cb144bcSMacpaul Lin FTSMC020_BANK_SIZE_32M | \ 2656cb144bcSMacpaul Lin FTSMC020_BANK_MBW_32) 2666cb144bcSMacpaul Lin 2676cb144bcSMacpaul Lin #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 2686cb144bcSMacpaul Lin FTSMC020_TPR_CTW(3) | \ 2696cb144bcSMacpaul Lin FTSMC020_TPR_ATI(0xf) | \ 2706cb144bcSMacpaul Lin FTSMC020_TPR_AT2(3) | \ 2716cb144bcSMacpaul Lin FTSMC020_TPR_WTC(3) | \ 2726cb144bcSMacpaul Lin FTSMC020_TPR_AHT(3) | \ 2736cb144bcSMacpaul Lin FTSMC020_TPR_TRNA(0xf)) 2746cb144bcSMacpaul Lin 2756cb144bcSMacpaul Lin #define FTSMC020_BANK1_CONFIG (0x00) 2766cb144bcSMacpaul Lin #define FTSMC020_BANK1_TIMING (0x00) 2776cb144bcSMacpaul Lin #endif /* CONFIG_FTSMC020 */ 2786cb144bcSMacpaul Lin 2796cb144bcSMacpaul Lin /* 2806cb144bcSMacpaul Lin * FLASH and environment organization 2816cb144bcSMacpaul Lin */ 2826cb144bcSMacpaul Lin /* use CFI framework */ 2836cb144bcSMacpaul Lin 2846cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 2852e88bb28SKun-Hua Huang #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 2866cb144bcSMacpaul Lin 2876cb144bcSMacpaul Lin /* support JEDEC */ 2886cb144bcSMacpaul Lin 2896cb144bcSMacpaul Lin /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 2906cb144bcSMacpaul Lin #ifdef CONFIG_SKIP_LOWLEVEL_INIT 2912e88bb28SKun-Hua Huang #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 2922e88bb28SKun-Hua Huang #else 2936cb144bcSMacpaul Lin #ifdef CONFIG_MEM_REMAP 2946cb144bcSMacpaul Lin #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 2956cb144bcSMacpaul Lin #else 2966cb144bcSMacpaul Lin #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 2972e88bb28SKun-Hua Huang #endif 2986cb144bcSMacpaul Lin #endif /* CONFIG_MEM_REMAP */ 2996cb144bcSMacpaul Lin 3006cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 3016cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 3026cb144bcSMacpaul Lin #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 3036cb144bcSMacpaul Lin 3046cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 3056cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 3066cb144bcSMacpaul Lin 3076cb144bcSMacpaul Lin /* max number of memory banks */ 3086cb144bcSMacpaul Lin /* 3096cb144bcSMacpaul Lin * There are 4 banks supported for this Controller, 3106cb144bcSMacpaul Lin * but we have only 1 bank connected to flash on board 3116cb144bcSMacpaul Lin */ 312b841b6e9Srick #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 3136cb144bcSMacpaul Lin #define CONFIG_SYS_MAX_FLASH_BANKS 1 314b841b6e9Srick #endif 3152e88bb28SKun-Hua Huang #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 3166cb144bcSMacpaul Lin 3176cb144bcSMacpaul Lin /* max number of sectors on one chip */ 3182e88bb28SKun-Hua Huang #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 3196cb144bcSMacpaul Lin #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 3202e88bb28SKun-Hua Huang #define CONFIG_SYS_MAX_FLASH_SECT 512 3216cb144bcSMacpaul Lin 3226cb144bcSMacpaul Lin /* environments */ 3236cb144bcSMacpaul Lin #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 3246cb144bcSMacpaul Lin #define CONFIG_ENV_SIZE 8192 3256cb144bcSMacpaul Lin #define CONFIG_ENV_OVERWRITE 3266cb144bcSMacpaul Lin 327b841b6e9Srick /* 328b841b6e9Srick * For booting Linux, the board info and command line data 329b841b6e9Srick * have to be in the first 16 MB of memory, since this is 330b841b6e9Srick * the maximum mapped by the Linux kernel during initialization. 331b841b6e9Srick */ 332b841b6e9Srick 333b841b6e9Srick /* Initial Memory map for Linux*/ 334b841b6e9Srick #define CONFIG_SYS_BOOTMAPSZ (64 << 20) 335b841b6e9Srick /* Increase max gunzip size */ 336b841b6e9Srick #define CONFIG_SYS_BOOTM_LEN (64 << 20) 337b841b6e9Srick 3386cb144bcSMacpaul Lin #endif /* __CONFIG_H */ 339