16cb144bcSMacpaul Lin /* 26cb144bcSMacpaul Lin * Copyright (C) 2011 Andes Technology Corporation 36cb144bcSMacpaul Lin * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 46cb144bcSMacpaul Lin * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 56cb144bcSMacpaul Lin * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 76cb144bcSMacpaul Lin */ 86cb144bcSMacpaul Lin 96cb144bcSMacpaul Lin #ifndef __CONFIG_H 106cb144bcSMacpaul Lin #define __CONFIG_H 116cb144bcSMacpaul Lin 127e3f94e1SMasahiro Yamada #include <asm/arch-ag101/ag101.h> 136cb144bcSMacpaul Lin 146cb144bcSMacpaul Lin /* 156cb144bcSMacpaul Lin * CPU and Board Configuration Options 166cb144bcSMacpaul Lin */ 176cb144bcSMacpaul Lin #define CONFIG_ADP_AG101P 186cb144bcSMacpaul Lin 196cb144bcSMacpaul Lin #define CONFIG_USE_INTERRUPT 206cb144bcSMacpaul Lin 216cb144bcSMacpaul Lin #define CONFIG_SKIP_LOWLEVEL_INIT 226cb144bcSMacpaul Lin 23*b841b6e9Srick #define CONFIG_CMDLINE_EDITING 24*b841b6e9Srick 25*b841b6e9Srick #define CONFIG_SYS_ICACHE_OFF 26*b841b6e9Srick #define CONFIG_SYS_DCACHE_OFF 27*b841b6e9Srick 28*b841b6e9Srick #define CONFIG_BOOTP_SEND_HOSTNAME 29*b841b6e9Srick #define CONFIG_BOOTP_SERVERIP 30e3c58b02Sken kuo 316cb144bcSMacpaul Lin #ifndef CONFIG_SKIP_LOWLEVEL_INIT 326cb144bcSMacpaul Lin #define CONFIG_MEM_REMAP 336cb144bcSMacpaul Lin #endif 346cb144bcSMacpaul Lin 356cb144bcSMacpaul Lin #ifdef CONFIG_SKIP_LOWLEVEL_INIT 362e88bb28SKun-Hua Huang #define CONFIG_SYS_TEXT_BASE 0x00500000 3786132af7Srick #ifdef CONFIG_OF_CONTROL 3886132af7Srick #undef CONFIG_OF_SEPARATE 3986132af7Srick #define CONFIG_OF_EMBED 4086132af7Srick #endif 412e88bb28SKun-Hua Huang #else 422e88bb28SKun-Hua Huang #ifdef CONFIG_MEM_REMAP 432e88bb28SKun-Hua Huang #define CONFIG_SYS_TEXT_BASE 0x80000000 446cb144bcSMacpaul Lin #else 456cb144bcSMacpaul Lin #define CONFIG_SYS_TEXT_BASE 0x00000000 466cb144bcSMacpaul Lin #endif 472e88bb28SKun-Hua Huang #endif 486cb144bcSMacpaul Lin 496cb144bcSMacpaul Lin /* 506cb144bcSMacpaul Lin * Timer 516cb144bcSMacpaul Lin */ 526cb144bcSMacpaul Lin #define CONFIG_SYS_CLK_FREQ 39062500 536cb144bcSMacpaul Lin #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 546cb144bcSMacpaul Lin 556cb144bcSMacpaul Lin /* 566cb144bcSMacpaul Lin * Use Externel CLOCK or PCLK 576cb144bcSMacpaul Lin */ 586cb144bcSMacpaul Lin #undef CONFIG_FTRTC010_EXTCLK 596cb144bcSMacpaul Lin 606cb144bcSMacpaul Lin #ifndef CONFIG_FTRTC010_EXTCLK 616cb144bcSMacpaul Lin #define CONFIG_FTRTC010_PCLK 626cb144bcSMacpaul Lin #endif 636cb144bcSMacpaul Lin 646cb144bcSMacpaul Lin #ifdef CONFIG_FTRTC010_EXTCLK 656cb144bcSMacpaul Lin #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 666cb144bcSMacpaul Lin #else 676cb144bcSMacpaul Lin #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 686cb144bcSMacpaul Lin #endif 696cb144bcSMacpaul Lin 706cb144bcSMacpaul Lin #define TIMER_LOAD_VAL 0xffffffff 716cb144bcSMacpaul Lin 726cb144bcSMacpaul Lin /* 736cb144bcSMacpaul Lin * Real Time Clock 746cb144bcSMacpaul Lin */ 756cb144bcSMacpaul Lin #define CONFIG_RTC_FTRTC010 766cb144bcSMacpaul Lin 776cb144bcSMacpaul Lin /* 786cb144bcSMacpaul Lin * Real Time Clock Divider 796cb144bcSMacpaul Lin * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 806cb144bcSMacpaul Lin */ 816cb144bcSMacpaul Lin #define OSC_5MHZ (5*1000000) 826cb144bcSMacpaul Lin #define OSC_CLK (4*OSC_5MHZ) 836cb144bcSMacpaul Lin #define RTC_DIV_COUNT (0.5) /* Why?? */ 846cb144bcSMacpaul Lin 856cb144bcSMacpaul Lin /* 866cb144bcSMacpaul Lin * Serial console configuration 876cb144bcSMacpaul Lin */ 886cb144bcSMacpaul Lin 896cb144bcSMacpaul Lin /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 906cb144bcSMacpaul Lin #define CONFIG_CONS_INDEX 1 916cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_SERIAL 926cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 9386132af7Srick #ifndef CONFIG_DM_SERIAL 946cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_REG_SIZE -4 9586132af7Srick #endif 966cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 976cb144bcSMacpaul Lin 986cb144bcSMacpaul Lin /* 996cb144bcSMacpaul Lin * Ethernet 1006cb144bcSMacpaul Lin */ 1016cb144bcSMacpaul Lin #define CONFIG_FTMAC100 1026cb144bcSMacpaul Lin 1036cb144bcSMacpaul Lin /* 1046cb144bcSMacpaul Lin * SD (MMC) controller 1056cb144bcSMacpaul Lin */ 1066cb144bcSMacpaul Lin #define CONFIG_FTSDC010 1076cb144bcSMacpaul Lin #define CONFIG_FTSDC010_NUMBER 1 10861ccf082Sken kuo #define CONFIG_FTSDC010_SDIO 1096cb144bcSMacpaul Lin 1106cb144bcSMacpaul Lin /* 1116cb144bcSMacpaul Lin * Miscellaneous configurable options 1126cb144bcSMacpaul Lin */ 1136cb144bcSMacpaul Lin #define CONFIG_SYS_LONGHELP /* undef to save memory */ 1146cb144bcSMacpaul Lin #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 1156cb144bcSMacpaul Lin 1166cb144bcSMacpaul Lin /* Print Buffer Size */ 1176cb144bcSMacpaul Lin #define CONFIG_SYS_PBSIZE \ 1186cb144bcSMacpaul Lin (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 1196cb144bcSMacpaul Lin 1206cb144bcSMacpaul Lin /* max number of command args */ 1216cb144bcSMacpaul Lin #define CONFIG_SYS_MAXARGS 16 1226cb144bcSMacpaul Lin 1236cb144bcSMacpaul Lin /* Boot Argument Buffer Size */ 1246cb144bcSMacpaul Lin #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 1256cb144bcSMacpaul Lin 1266cb144bcSMacpaul Lin /* 1276cb144bcSMacpaul Lin * Size of malloc() pool 1286cb144bcSMacpaul Lin */ 1296cb144bcSMacpaul Lin /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 1306cb144bcSMacpaul Lin #define CONFIG_SYS_MALLOC_LEN (512 << 10) 1316cb144bcSMacpaul Lin 1326cb144bcSMacpaul Lin /* 1336cb144bcSMacpaul Lin * AHB Controller configuration 1346cb144bcSMacpaul Lin */ 1356cb144bcSMacpaul Lin #define CONFIG_FTAHBC020S 1366cb144bcSMacpaul Lin 1376cb144bcSMacpaul Lin #ifdef CONFIG_FTAHBC020S 1386cb144bcSMacpaul Lin #include <faraday/ftahbc020s.h> 1396cb144bcSMacpaul Lin 1406cb144bcSMacpaul Lin /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 1416cb144bcSMacpaul Lin #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 1426cb144bcSMacpaul Lin 1436cb144bcSMacpaul Lin /* 1446cb144bcSMacpaul Lin * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 1456cb144bcSMacpaul Lin * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 1466cb144bcSMacpaul Lin * in C language. 1476cb144bcSMacpaul Lin */ 1486cb144bcSMacpaul Lin #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 1496cb144bcSMacpaul Lin (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 1506cb144bcSMacpaul Lin FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 1516cb144bcSMacpaul Lin #endif 1526cb144bcSMacpaul Lin 1536cb144bcSMacpaul Lin /* 1546cb144bcSMacpaul Lin * Watchdog 1556cb144bcSMacpaul Lin */ 1566cb144bcSMacpaul Lin #define CONFIG_FTWDT010_WATCHDOG 1576cb144bcSMacpaul Lin 1586cb144bcSMacpaul Lin /* 1596cb144bcSMacpaul Lin * PMU Power controller configuration 1606cb144bcSMacpaul Lin */ 1616cb144bcSMacpaul Lin #define CONFIG_PMU 1626cb144bcSMacpaul Lin #define CONFIG_FTPMU010_POWER 1636cb144bcSMacpaul Lin 1646cb144bcSMacpaul Lin #ifdef CONFIG_FTPMU010_POWER 1656cb144bcSMacpaul Lin #include <faraday/ftpmu010.h> 1666cb144bcSMacpaul Lin #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 1676cb144bcSMacpaul Lin #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 1686cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 1696cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 1706cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 1716cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_CKE_DCSR | \ 1726cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_DQM_DCSR | \ 1736cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_SDCLK_DCSR) 1746cb144bcSMacpaul Lin #endif 1756cb144bcSMacpaul Lin 1766cb144bcSMacpaul Lin /* 1776cb144bcSMacpaul Lin * SDRAM controller configuration 1786cb144bcSMacpaul Lin */ 1796cb144bcSMacpaul Lin #define CONFIG_FTSDMC021 1806cb144bcSMacpaul Lin 1816cb144bcSMacpaul Lin #ifdef CONFIG_FTSDMC021 1826cb144bcSMacpaul Lin #include <faraday/ftsdmc021.h> 1836cb144bcSMacpaul Lin 1846cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 1856cb144bcSMacpaul Lin FTSDMC021_TP1_TRP(1) | \ 1866cb144bcSMacpaul Lin FTSDMC021_TP1_TRCD(1) | \ 1876cb144bcSMacpaul Lin FTSDMC021_TP1_TRF(3) | \ 1886cb144bcSMacpaul Lin FTSDMC021_TP1_TWR(1) | \ 1896cb144bcSMacpaul Lin FTSDMC021_TP1_TCL(2)) 1906cb144bcSMacpaul Lin 1916cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 1926cb144bcSMacpaul Lin FTSDMC021_TP2_INI_REFT(8) | \ 1936cb144bcSMacpaul Lin FTSDMC021_TP2_REF_INTV(0x180)) 1946cb144bcSMacpaul Lin 1956cb144bcSMacpaul Lin /* 1966cb144bcSMacpaul Lin * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 1976cb144bcSMacpaul Lin * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 1986cb144bcSMacpaul Lin * C language. 1996cb144bcSMacpaul Lin */ 2006cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 2016cb144bcSMacpaul Lin FTSDMC021_CR1_DSZ(3) | \ 2026cb144bcSMacpaul Lin FTSDMC021_CR1_MBW(2) | \ 2036cb144bcSMacpaul Lin FTSDMC021_CR1_BNKSIZE(6)) 2046cb144bcSMacpaul Lin 2056cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 2066cb144bcSMacpaul Lin FTSDMC021_CR2_IREF | \ 2076cb144bcSMacpaul Lin FTSDMC021_CR2_ISMR) 2086cb144bcSMacpaul Lin 2096cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 2106cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 2116cb144bcSMacpaul Lin CONFIG_SYS_FTSDMC021_BANK0_BASE) 2126cb144bcSMacpaul Lin 2133c016704Sken kuo #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 2143c016704Sken kuo (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 2153c016704Sken kuo #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 2163c016704Sken kuo CONFIG_SYS_FTSDMC021_BANK1_BASE) 2176cb144bcSMacpaul Lin #endif 2186cb144bcSMacpaul Lin 2196cb144bcSMacpaul Lin /* 2206cb144bcSMacpaul Lin * Physical Memory Map 2216cb144bcSMacpaul Lin */ 2222e88bb28SKun-Hua Huang #ifdef CONFIG_SKIP_LOWLEVEL_INIT 2236cb144bcSMacpaul Lin #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 2242e88bb28SKun-Hua Huang #else 2252e88bb28SKun-Hua Huang #ifdef CONFIG_MEM_REMAP 2262e88bb28SKun-Hua Huang #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 2272e88bb28SKun-Hua Huang #else 2282e88bb28SKun-Hua Huang #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ 2296cb144bcSMacpaul Lin #endif 2306cb144bcSMacpaul Lin #endif 2312e88bb28SKun-Hua Huang 2323c016704Sken kuo #define PHYS_SDRAM_1 \ 2333c016704Sken kuo (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 2346cb144bcSMacpaul Lin 2353c016704Sken kuo #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 2362e88bb28SKun-Hua Huang 2372e88bb28SKun-Hua Huang #ifdef CONFIG_SKIP_LOWLEVEL_INIT 2382e88bb28SKun-Hua Huang #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 2392e88bb28SKun-Hua Huang #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 2402e88bb28SKun-Hua Huang #else 2412e88bb28SKun-Hua Huang #ifdef CONFIG_MEM_REMAP 2422e88bb28SKun-Hua Huang #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 2432e88bb28SKun-Hua Huang #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 2442e88bb28SKun-Hua Huang #else 2452e88bb28SKun-Hua Huang #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ 2462e88bb28SKun-Hua Huang #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 2472e88bb28SKun-Hua Huang #endif 2482e88bb28SKun-Hua Huang #endif 2496cb144bcSMacpaul Lin 2506cb144bcSMacpaul Lin #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 2516cb144bcSMacpaul Lin 2526cb144bcSMacpaul Lin #ifdef CONFIG_MEM_REMAP 2536cb144bcSMacpaul Lin #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 2546cb144bcSMacpaul Lin GENERATED_GBL_DATA_SIZE) 2556cb144bcSMacpaul Lin #else 2566cb144bcSMacpaul Lin #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 2576cb144bcSMacpaul Lin GENERATED_GBL_DATA_SIZE) 2586cb144bcSMacpaul Lin #endif /* CONFIG_MEM_REMAP */ 2596cb144bcSMacpaul Lin 2606cb144bcSMacpaul Lin /* 2616cb144bcSMacpaul Lin * Load address and memory test area should agree with 262a187559eSBin Meng * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 2636cb144bcSMacpaul Lin */ 2646cb144bcSMacpaul Lin #define CONFIG_SYS_LOAD_ADDR 0x300000 2656cb144bcSMacpaul Lin 2666cb144bcSMacpaul Lin /* memtest works on 63 MB in DRAM */ 2676cb144bcSMacpaul Lin #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 2686cb144bcSMacpaul Lin #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 2696cb144bcSMacpaul Lin 2706cb144bcSMacpaul Lin /* 2716cb144bcSMacpaul Lin * Static memory controller configuration 2726cb144bcSMacpaul Lin */ 2736cb144bcSMacpaul Lin #define CONFIG_FTSMC020 2746cb144bcSMacpaul Lin 2756cb144bcSMacpaul Lin #ifdef CONFIG_FTSMC020 2766cb144bcSMacpaul Lin #include <faraday/ftsmc020.h> 2776cb144bcSMacpaul Lin 2786cb144bcSMacpaul Lin #define CONFIG_SYS_FTSMC020_CONFIGS { \ 2796cb144bcSMacpaul Lin { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 2806cb144bcSMacpaul Lin { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 2816cb144bcSMacpaul Lin } 2826cb144bcSMacpaul Lin 2836cb144bcSMacpaul Lin #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 2846cb144bcSMacpaul Lin #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 2856cb144bcSMacpaul Lin FTSMC020_BANK_SIZE_32M | \ 2866cb144bcSMacpaul Lin FTSMC020_BANK_MBW_32) 2876cb144bcSMacpaul Lin 2886cb144bcSMacpaul Lin #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 2896cb144bcSMacpaul Lin FTSMC020_TPR_AST(1) | \ 2906cb144bcSMacpaul Lin FTSMC020_TPR_CTW(1) | \ 2916cb144bcSMacpaul Lin FTSMC020_TPR_ATI(1) | \ 2926cb144bcSMacpaul Lin FTSMC020_TPR_AT2(1) | \ 2936cb144bcSMacpaul Lin FTSMC020_TPR_WTC(1) | \ 2946cb144bcSMacpaul Lin FTSMC020_TPR_AHT(1) | \ 2956cb144bcSMacpaul Lin FTSMC020_TPR_TRNA(1)) 2966cb144bcSMacpaul Lin #endif 2976cb144bcSMacpaul Lin 2986cb144bcSMacpaul Lin /* 2996cb144bcSMacpaul Lin * FLASH on ADP_AG101P is connected to BANK0 3006cb144bcSMacpaul Lin * Just disalbe the other BANK to avoid detection error. 3016cb144bcSMacpaul Lin */ 3026cb144bcSMacpaul Lin #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 3036cb144bcSMacpaul Lin FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 3046cb144bcSMacpaul Lin FTSMC020_BANK_SIZE_32M | \ 3056cb144bcSMacpaul Lin FTSMC020_BANK_MBW_32) 3066cb144bcSMacpaul Lin 3076cb144bcSMacpaul Lin #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 3086cb144bcSMacpaul Lin FTSMC020_TPR_CTW(3) | \ 3096cb144bcSMacpaul Lin FTSMC020_TPR_ATI(0xf) | \ 3106cb144bcSMacpaul Lin FTSMC020_TPR_AT2(3) | \ 3116cb144bcSMacpaul Lin FTSMC020_TPR_WTC(3) | \ 3126cb144bcSMacpaul Lin FTSMC020_TPR_AHT(3) | \ 3136cb144bcSMacpaul Lin FTSMC020_TPR_TRNA(0xf)) 3146cb144bcSMacpaul Lin 3156cb144bcSMacpaul Lin #define FTSMC020_BANK1_CONFIG (0x00) 3166cb144bcSMacpaul Lin #define FTSMC020_BANK1_TIMING (0x00) 3176cb144bcSMacpaul Lin #endif /* CONFIG_FTSMC020 */ 3186cb144bcSMacpaul Lin 3196cb144bcSMacpaul Lin /* 3206cb144bcSMacpaul Lin * FLASH and environment organization 3216cb144bcSMacpaul Lin */ 3226cb144bcSMacpaul Lin /* use CFI framework */ 3236cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_CFI 3246cb144bcSMacpaul Lin #define CONFIG_FLASH_CFI_DRIVER 3256cb144bcSMacpaul Lin 3266cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 3276cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 3282e88bb28SKun-Hua Huang #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 3296cb144bcSMacpaul Lin 3306cb144bcSMacpaul Lin /* support JEDEC */ 3316cb144bcSMacpaul Lin 3326cb144bcSMacpaul Lin /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 3336cb144bcSMacpaul Lin #ifdef CONFIG_SKIP_LOWLEVEL_INIT 3342e88bb28SKun-Hua Huang #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 3352e88bb28SKun-Hua Huang #else 3366cb144bcSMacpaul Lin #ifdef CONFIG_MEM_REMAP 3376cb144bcSMacpaul Lin #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 3386cb144bcSMacpaul Lin #else 3396cb144bcSMacpaul Lin #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 3402e88bb28SKun-Hua Huang #endif 3416cb144bcSMacpaul Lin #endif /* CONFIG_MEM_REMAP */ 3426cb144bcSMacpaul Lin 3436cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 3446cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 3456cb144bcSMacpaul Lin #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 3466cb144bcSMacpaul Lin 3476cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 3486cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 3496cb144bcSMacpaul Lin 3506cb144bcSMacpaul Lin /* max number of memory banks */ 3516cb144bcSMacpaul Lin /* 3526cb144bcSMacpaul Lin * There are 4 banks supported for this Controller, 3536cb144bcSMacpaul Lin * but we have only 1 bank connected to flash on board 3546cb144bcSMacpaul Lin */ 355*b841b6e9Srick #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 3566cb144bcSMacpaul Lin #define CONFIG_SYS_MAX_FLASH_BANKS 1 357*b841b6e9Srick #endif 3582e88bb28SKun-Hua Huang #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 3596cb144bcSMacpaul Lin 3606cb144bcSMacpaul Lin /* max number of sectors on one chip */ 3612e88bb28SKun-Hua Huang #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 3626cb144bcSMacpaul Lin #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 3632e88bb28SKun-Hua Huang #define CONFIG_SYS_MAX_FLASH_SECT 512 3646cb144bcSMacpaul Lin 3656cb144bcSMacpaul Lin /* environments */ 3666cb144bcSMacpaul Lin #define CONFIG_ENV_IS_IN_FLASH 3676cb144bcSMacpaul Lin #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 3686cb144bcSMacpaul Lin #define CONFIG_ENV_SIZE 8192 3696cb144bcSMacpaul Lin #define CONFIG_ENV_OVERWRITE 3706cb144bcSMacpaul Lin 371*b841b6e9Srick /* 372*b841b6e9Srick * For booting Linux, the board info and command line data 373*b841b6e9Srick * have to be in the first 16 MB of memory, since this is 374*b841b6e9Srick * the maximum mapped by the Linux kernel during initialization. 375*b841b6e9Srick */ 376*b841b6e9Srick 377*b841b6e9Srick /* Initial Memory map for Linux*/ 378*b841b6e9Srick #define CONFIG_SYS_BOOTMAPSZ (64 << 20) 379*b841b6e9Srick /* Increase max gunzip size */ 380*b841b6e9Srick #define CONFIG_SYS_BOOTM_LEN (64 << 20) 381*b841b6e9Srick 3826cb144bcSMacpaul Lin #endif /* __CONFIG_H */ 383