16cb144bcSMacpaul Lin /* 26cb144bcSMacpaul Lin * Copyright (C) 2011 Andes Technology Corporation 36cb144bcSMacpaul Lin * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 46cb144bcSMacpaul Lin * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 56cb144bcSMacpaul Lin * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 76cb144bcSMacpaul Lin */ 86cb144bcSMacpaul Lin 96cb144bcSMacpaul Lin #ifndef __CONFIG_H 106cb144bcSMacpaul Lin #define __CONFIG_H 116cb144bcSMacpaul Lin 127e3f94e1SMasahiro Yamada #include <asm/arch-ag101/ag101.h> 136cb144bcSMacpaul Lin 146cb144bcSMacpaul Lin /* 156cb144bcSMacpaul Lin * CPU and Board Configuration Options 166cb144bcSMacpaul Lin */ 176cb144bcSMacpaul Lin #define CONFIG_ADP_AG101P 186cb144bcSMacpaul Lin 196cb144bcSMacpaul Lin #define CONFIG_USE_INTERRUPT 206cb144bcSMacpaul Lin 216cb144bcSMacpaul Lin #define CONFIG_SKIP_LOWLEVEL_INIT 226cb144bcSMacpaul Lin 232e88bb28SKun-Hua Huang #define CONFIG_SYS_GENERIC_GLOBAL_DATA 242e88bb28SKun-Hua Huang 25e3c58b02Sken kuo /* 26e3c58b02Sken kuo * Definitions related to passing arguments to kernel. 27e3c58b02Sken kuo */ 28e3c58b02Sken kuo #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ 29e3c58b02Sken kuo #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ 30e3c58b02Sken kuo #define CONFIG_INITRD_TAG /* send initrd params */ 312e88bb28SKun-Hua Huang #define CONFIG_NEEDS_MANUAL_RELOC 32e3c58b02Sken kuo 336cb144bcSMacpaul Lin #ifndef CONFIG_SKIP_LOWLEVEL_INIT 346cb144bcSMacpaul Lin #define CONFIG_MEM_REMAP 356cb144bcSMacpaul Lin #endif 366cb144bcSMacpaul Lin 376cb144bcSMacpaul Lin #ifdef CONFIG_SKIP_LOWLEVEL_INIT 382e88bb28SKun-Hua Huang #define CONFIG_SYS_TEXT_BASE 0x00500000 392e88bb28SKun-Hua Huang #else 402e88bb28SKun-Hua Huang #ifdef CONFIG_MEM_REMAP 412e88bb28SKun-Hua Huang #define CONFIG_SYS_TEXT_BASE 0x80000000 426cb144bcSMacpaul Lin #else 436cb144bcSMacpaul Lin #define CONFIG_SYS_TEXT_BASE 0x00000000 446cb144bcSMacpaul Lin #endif 452e88bb28SKun-Hua Huang #endif 466cb144bcSMacpaul Lin 476cb144bcSMacpaul Lin /* 486cb144bcSMacpaul Lin * Timer 496cb144bcSMacpaul Lin */ 506cb144bcSMacpaul Lin #define CONFIG_SYS_CLK_FREQ 39062500 516cb144bcSMacpaul Lin #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 526cb144bcSMacpaul Lin 536cb144bcSMacpaul Lin /* 546cb144bcSMacpaul Lin * Use Externel CLOCK or PCLK 556cb144bcSMacpaul Lin */ 566cb144bcSMacpaul Lin #undef CONFIG_FTRTC010_EXTCLK 576cb144bcSMacpaul Lin 586cb144bcSMacpaul Lin #ifndef CONFIG_FTRTC010_EXTCLK 596cb144bcSMacpaul Lin #define CONFIG_FTRTC010_PCLK 606cb144bcSMacpaul Lin #endif 616cb144bcSMacpaul Lin 626cb144bcSMacpaul Lin #ifdef CONFIG_FTRTC010_EXTCLK 636cb144bcSMacpaul Lin #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 646cb144bcSMacpaul Lin #else 656cb144bcSMacpaul Lin #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 666cb144bcSMacpaul Lin #endif 676cb144bcSMacpaul Lin 686cb144bcSMacpaul Lin #define TIMER_LOAD_VAL 0xffffffff 696cb144bcSMacpaul Lin 706cb144bcSMacpaul Lin /* 716cb144bcSMacpaul Lin * Real Time Clock 726cb144bcSMacpaul Lin */ 736cb144bcSMacpaul Lin #define CONFIG_RTC_FTRTC010 746cb144bcSMacpaul Lin 756cb144bcSMacpaul Lin /* 766cb144bcSMacpaul Lin * Real Time Clock Divider 776cb144bcSMacpaul Lin * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 786cb144bcSMacpaul Lin */ 796cb144bcSMacpaul Lin #define OSC_5MHZ (5*1000000) 806cb144bcSMacpaul Lin #define OSC_CLK (4*OSC_5MHZ) 816cb144bcSMacpaul Lin #define RTC_DIV_COUNT (0.5) /* Why?? */ 826cb144bcSMacpaul Lin 836cb144bcSMacpaul Lin /* 846cb144bcSMacpaul Lin * Serial console configuration 856cb144bcSMacpaul Lin */ 866cb144bcSMacpaul Lin 876cb144bcSMacpaul Lin /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 886cb144bcSMacpaul Lin #define CONFIG_BAUDRATE 38400 896cb144bcSMacpaul Lin #define CONFIG_CONS_INDEX 1 906cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_SERIAL 916cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 926cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_REG_SIZE -4 936cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 946cb144bcSMacpaul Lin 956cb144bcSMacpaul Lin /* 966cb144bcSMacpaul Lin * Ethernet 976cb144bcSMacpaul Lin */ 986cb144bcSMacpaul Lin #define CONFIG_FTMAC100 996cb144bcSMacpaul Lin 1006cb144bcSMacpaul Lin #define CONFIG_BOOTDELAY 3 1016cb144bcSMacpaul Lin 1026cb144bcSMacpaul Lin /* 1036cb144bcSMacpaul Lin * SD (MMC) controller 1046cb144bcSMacpaul Lin */ 1056cb144bcSMacpaul Lin #define CONFIG_MMC 1066cb144bcSMacpaul Lin #define CONFIG_CMD_MMC 1076cb144bcSMacpaul Lin #define CONFIG_GENERIC_MMC 1086cb144bcSMacpaul Lin #define CONFIG_DOS_PARTITION 1096cb144bcSMacpaul Lin #define CONFIG_FTSDC010 1106cb144bcSMacpaul Lin #define CONFIG_FTSDC010_NUMBER 1 11161ccf082Sken kuo #define CONFIG_FTSDC010_SDIO 1126cb144bcSMacpaul Lin #define CONFIG_CMD_FAT 11361ccf082Sken kuo #define CONFIG_CMD_EXT2 1146cb144bcSMacpaul Lin 1156cb144bcSMacpaul Lin /* 1166cb144bcSMacpaul Lin * Command line configuration. 1176cb144bcSMacpaul Lin */ 1186cb144bcSMacpaul Lin #define CONFIG_CMD_CACHE 1196cb144bcSMacpaul Lin #define CONFIG_CMD_DATE 1206cb144bcSMacpaul Lin #define CONFIG_CMD_PING 1216cb144bcSMacpaul Lin 1226cb144bcSMacpaul Lin /* 1236cb144bcSMacpaul Lin * Miscellaneous configurable options 1246cb144bcSMacpaul Lin */ 1256cb144bcSMacpaul Lin #define CONFIG_SYS_LONGHELP /* undef to save memory */ 1266cb144bcSMacpaul Lin #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 1276cb144bcSMacpaul Lin 1286cb144bcSMacpaul Lin /* Print Buffer Size */ 1296cb144bcSMacpaul Lin #define CONFIG_SYS_PBSIZE \ 1306cb144bcSMacpaul Lin (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 1316cb144bcSMacpaul Lin 1326cb144bcSMacpaul Lin /* max number of command args */ 1336cb144bcSMacpaul Lin #define CONFIG_SYS_MAXARGS 16 1346cb144bcSMacpaul Lin 1356cb144bcSMacpaul Lin /* Boot Argument Buffer Size */ 1366cb144bcSMacpaul Lin #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 1376cb144bcSMacpaul Lin 1386cb144bcSMacpaul Lin /* 1396cb144bcSMacpaul Lin * Size of malloc() pool 1406cb144bcSMacpaul Lin */ 1416cb144bcSMacpaul Lin /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 1426cb144bcSMacpaul Lin #define CONFIG_SYS_MALLOC_LEN (512 << 10) 1436cb144bcSMacpaul Lin 1446cb144bcSMacpaul Lin /* 1456cb144bcSMacpaul Lin * AHB Controller configuration 1466cb144bcSMacpaul Lin */ 1476cb144bcSMacpaul Lin #define CONFIG_FTAHBC020S 1486cb144bcSMacpaul Lin 1496cb144bcSMacpaul Lin #ifdef CONFIG_FTAHBC020S 1506cb144bcSMacpaul Lin #include <faraday/ftahbc020s.h> 1516cb144bcSMacpaul Lin 1526cb144bcSMacpaul Lin /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 1536cb144bcSMacpaul Lin #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 1546cb144bcSMacpaul Lin 1556cb144bcSMacpaul Lin /* 1566cb144bcSMacpaul Lin * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 1576cb144bcSMacpaul Lin * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 1586cb144bcSMacpaul Lin * in C language. 1596cb144bcSMacpaul Lin */ 1606cb144bcSMacpaul Lin #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 1616cb144bcSMacpaul Lin (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 1626cb144bcSMacpaul Lin FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 1636cb144bcSMacpaul Lin #endif 1646cb144bcSMacpaul Lin 1656cb144bcSMacpaul Lin /* 1666cb144bcSMacpaul Lin * Watchdog 1676cb144bcSMacpaul Lin */ 1686cb144bcSMacpaul Lin #define CONFIG_FTWDT010_WATCHDOG 1696cb144bcSMacpaul Lin 1706cb144bcSMacpaul Lin /* 1716cb144bcSMacpaul Lin * PMU Power controller configuration 1726cb144bcSMacpaul Lin */ 1736cb144bcSMacpaul Lin #define CONFIG_PMU 1746cb144bcSMacpaul Lin #define CONFIG_FTPMU010_POWER 1756cb144bcSMacpaul Lin 1766cb144bcSMacpaul Lin #ifdef CONFIG_FTPMU010_POWER 1776cb144bcSMacpaul Lin #include <faraday/ftpmu010.h> 1786cb144bcSMacpaul Lin #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 1796cb144bcSMacpaul Lin #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 1806cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 1816cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 1826cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 1836cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_CKE_DCSR | \ 1846cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_DQM_DCSR | \ 1856cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_SDCLK_DCSR) 1866cb144bcSMacpaul Lin #endif 1876cb144bcSMacpaul Lin 1886cb144bcSMacpaul Lin /* 1896cb144bcSMacpaul Lin * SDRAM controller configuration 1906cb144bcSMacpaul Lin */ 1916cb144bcSMacpaul Lin #define CONFIG_FTSDMC021 1926cb144bcSMacpaul Lin 1936cb144bcSMacpaul Lin #ifdef CONFIG_FTSDMC021 1946cb144bcSMacpaul Lin #include <faraday/ftsdmc021.h> 1956cb144bcSMacpaul Lin 1966cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 1976cb144bcSMacpaul Lin FTSDMC021_TP1_TRP(1) | \ 1986cb144bcSMacpaul Lin FTSDMC021_TP1_TRCD(1) | \ 1996cb144bcSMacpaul Lin FTSDMC021_TP1_TRF(3) | \ 2006cb144bcSMacpaul Lin FTSDMC021_TP1_TWR(1) | \ 2016cb144bcSMacpaul Lin FTSDMC021_TP1_TCL(2)) 2026cb144bcSMacpaul Lin 2036cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 2046cb144bcSMacpaul Lin FTSDMC021_TP2_INI_REFT(8) | \ 2056cb144bcSMacpaul Lin FTSDMC021_TP2_REF_INTV(0x180)) 2066cb144bcSMacpaul Lin 2076cb144bcSMacpaul Lin /* 2086cb144bcSMacpaul Lin * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 2096cb144bcSMacpaul Lin * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 2106cb144bcSMacpaul Lin * C language. 2116cb144bcSMacpaul Lin */ 2126cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 2136cb144bcSMacpaul Lin FTSDMC021_CR1_DSZ(3) | \ 2146cb144bcSMacpaul Lin FTSDMC021_CR1_MBW(2) | \ 2156cb144bcSMacpaul Lin FTSDMC021_CR1_BNKSIZE(6)) 2166cb144bcSMacpaul Lin 2176cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 2186cb144bcSMacpaul Lin FTSDMC021_CR2_IREF | \ 2196cb144bcSMacpaul Lin FTSDMC021_CR2_ISMR) 2206cb144bcSMacpaul Lin 2216cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 2226cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 2236cb144bcSMacpaul Lin CONFIG_SYS_FTSDMC021_BANK0_BASE) 2246cb144bcSMacpaul Lin 2253c016704Sken kuo #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 2263c016704Sken kuo (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 2273c016704Sken kuo #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 2283c016704Sken kuo CONFIG_SYS_FTSDMC021_BANK1_BASE) 2296cb144bcSMacpaul Lin #endif 2306cb144bcSMacpaul Lin 2316cb144bcSMacpaul Lin /* 2326cb144bcSMacpaul Lin * Physical Memory Map 2336cb144bcSMacpaul Lin */ 2342e88bb28SKun-Hua Huang #ifdef CONFIG_SKIP_LOWLEVEL_INIT 2356cb144bcSMacpaul Lin #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 2362e88bb28SKun-Hua Huang #else 2372e88bb28SKun-Hua Huang #ifdef CONFIG_MEM_REMAP 2382e88bb28SKun-Hua Huang #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 2392e88bb28SKun-Hua Huang #else 2402e88bb28SKun-Hua Huang #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ 2416cb144bcSMacpaul Lin #endif 2426cb144bcSMacpaul Lin #endif 2432e88bb28SKun-Hua Huang 2443c016704Sken kuo #define PHYS_SDRAM_1 \ 2453c016704Sken kuo (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 2466cb144bcSMacpaul Lin 2473c016704Sken kuo #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 2482e88bb28SKun-Hua Huang 2492e88bb28SKun-Hua Huang #ifdef CONFIG_SKIP_LOWLEVEL_INIT 2502e88bb28SKun-Hua Huang #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 2512e88bb28SKun-Hua Huang #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 2522e88bb28SKun-Hua Huang #else 2532e88bb28SKun-Hua Huang #ifdef CONFIG_MEM_REMAP 2542e88bb28SKun-Hua Huang #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 2552e88bb28SKun-Hua Huang #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 2562e88bb28SKun-Hua Huang #else 2572e88bb28SKun-Hua Huang #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ 2582e88bb28SKun-Hua Huang #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 2592e88bb28SKun-Hua Huang #endif 2602e88bb28SKun-Hua Huang #endif 2616cb144bcSMacpaul Lin 2626cb144bcSMacpaul Lin #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 2636cb144bcSMacpaul Lin 2646cb144bcSMacpaul Lin #ifdef CONFIG_MEM_REMAP 2656cb144bcSMacpaul Lin #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 2666cb144bcSMacpaul Lin GENERATED_GBL_DATA_SIZE) 2676cb144bcSMacpaul Lin #else 2686cb144bcSMacpaul Lin #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 2696cb144bcSMacpaul Lin GENERATED_GBL_DATA_SIZE) 2706cb144bcSMacpaul Lin #endif /* CONFIG_MEM_REMAP */ 2716cb144bcSMacpaul Lin 2726cb144bcSMacpaul Lin /* 2736cb144bcSMacpaul Lin * Load address and memory test area should agree with 274*a187559eSBin Meng * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 2756cb144bcSMacpaul Lin */ 2766cb144bcSMacpaul Lin #define CONFIG_SYS_LOAD_ADDR 0x300000 2776cb144bcSMacpaul Lin 2786cb144bcSMacpaul Lin /* memtest works on 63 MB in DRAM */ 2796cb144bcSMacpaul Lin #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 2806cb144bcSMacpaul Lin #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 2816cb144bcSMacpaul Lin 2826cb144bcSMacpaul Lin /* 2836cb144bcSMacpaul Lin * Static memory controller configuration 2846cb144bcSMacpaul Lin */ 2856cb144bcSMacpaul Lin #define CONFIG_FTSMC020 2866cb144bcSMacpaul Lin 2876cb144bcSMacpaul Lin #ifdef CONFIG_FTSMC020 2886cb144bcSMacpaul Lin #include <faraday/ftsmc020.h> 2896cb144bcSMacpaul Lin 2906cb144bcSMacpaul Lin #define CONFIG_SYS_FTSMC020_CONFIGS { \ 2916cb144bcSMacpaul Lin { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 2926cb144bcSMacpaul Lin { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 2936cb144bcSMacpaul Lin } 2946cb144bcSMacpaul Lin 2956cb144bcSMacpaul Lin #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 2966cb144bcSMacpaul Lin #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 2976cb144bcSMacpaul Lin FTSMC020_BANK_SIZE_32M | \ 2986cb144bcSMacpaul Lin FTSMC020_BANK_MBW_32) 2996cb144bcSMacpaul Lin 3006cb144bcSMacpaul Lin #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 3016cb144bcSMacpaul Lin FTSMC020_TPR_AST(1) | \ 3026cb144bcSMacpaul Lin FTSMC020_TPR_CTW(1) | \ 3036cb144bcSMacpaul Lin FTSMC020_TPR_ATI(1) | \ 3046cb144bcSMacpaul Lin FTSMC020_TPR_AT2(1) | \ 3056cb144bcSMacpaul Lin FTSMC020_TPR_WTC(1) | \ 3066cb144bcSMacpaul Lin FTSMC020_TPR_AHT(1) | \ 3076cb144bcSMacpaul Lin FTSMC020_TPR_TRNA(1)) 3086cb144bcSMacpaul Lin #endif 3096cb144bcSMacpaul Lin 3106cb144bcSMacpaul Lin /* 3116cb144bcSMacpaul Lin * FLASH on ADP_AG101P is connected to BANK0 3126cb144bcSMacpaul Lin * Just disalbe the other BANK to avoid detection error. 3136cb144bcSMacpaul Lin */ 3146cb144bcSMacpaul Lin #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 3156cb144bcSMacpaul Lin FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 3166cb144bcSMacpaul Lin FTSMC020_BANK_SIZE_32M | \ 3176cb144bcSMacpaul Lin FTSMC020_BANK_MBW_32) 3186cb144bcSMacpaul Lin 3196cb144bcSMacpaul Lin #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 3206cb144bcSMacpaul Lin FTSMC020_TPR_CTW(3) | \ 3216cb144bcSMacpaul Lin FTSMC020_TPR_ATI(0xf) | \ 3226cb144bcSMacpaul Lin FTSMC020_TPR_AT2(3) | \ 3236cb144bcSMacpaul Lin FTSMC020_TPR_WTC(3) | \ 3246cb144bcSMacpaul Lin FTSMC020_TPR_AHT(3) | \ 3256cb144bcSMacpaul Lin FTSMC020_TPR_TRNA(0xf)) 3266cb144bcSMacpaul Lin 3276cb144bcSMacpaul Lin #define FTSMC020_BANK1_CONFIG (0x00) 3286cb144bcSMacpaul Lin #define FTSMC020_BANK1_TIMING (0x00) 3296cb144bcSMacpaul Lin #endif /* CONFIG_FTSMC020 */ 3306cb144bcSMacpaul Lin 3316cb144bcSMacpaul Lin /* 3326cb144bcSMacpaul Lin * FLASH and environment organization 3336cb144bcSMacpaul Lin */ 3346cb144bcSMacpaul Lin /* use CFI framework */ 3356cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_CFI 3366cb144bcSMacpaul Lin #define CONFIG_FLASH_CFI_DRIVER 3376cb144bcSMacpaul Lin 3386cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 3396cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 3402e88bb28SKun-Hua Huang #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 3416cb144bcSMacpaul Lin 3426cb144bcSMacpaul Lin /* support JEDEC */ 3436cb144bcSMacpaul Lin 3446cb144bcSMacpaul Lin /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 3456cb144bcSMacpaul Lin #ifdef CONFIG_SKIP_LOWLEVEL_INIT 3462e88bb28SKun-Hua Huang #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 3472e88bb28SKun-Hua Huang #else 3486cb144bcSMacpaul Lin #ifdef CONFIG_MEM_REMAP 3496cb144bcSMacpaul Lin #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 3506cb144bcSMacpaul Lin #else 3516cb144bcSMacpaul Lin #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 3522e88bb28SKun-Hua Huang #endif 3536cb144bcSMacpaul Lin #endif /* CONFIG_MEM_REMAP */ 3546cb144bcSMacpaul Lin 3556cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 3566cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 3576cb144bcSMacpaul Lin #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 3586cb144bcSMacpaul Lin 3596cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 3606cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 3616cb144bcSMacpaul Lin 3626cb144bcSMacpaul Lin /* max number of memory banks */ 3636cb144bcSMacpaul Lin /* 3646cb144bcSMacpaul Lin * There are 4 banks supported for this Controller, 3656cb144bcSMacpaul Lin * but we have only 1 bank connected to flash on board 3666cb144bcSMacpaul Lin */ 3676cb144bcSMacpaul Lin #define CONFIG_SYS_MAX_FLASH_BANKS 1 3682e88bb28SKun-Hua Huang #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 3696cb144bcSMacpaul Lin 3706cb144bcSMacpaul Lin /* max number of sectors on one chip */ 3712e88bb28SKun-Hua Huang #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 3726cb144bcSMacpaul Lin #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 3732e88bb28SKun-Hua Huang #define CONFIG_SYS_MAX_FLASH_SECT 512 3746cb144bcSMacpaul Lin 3756cb144bcSMacpaul Lin /* environments */ 3766cb144bcSMacpaul Lin #define CONFIG_ENV_IS_IN_FLASH 3776cb144bcSMacpaul Lin #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 3786cb144bcSMacpaul Lin #define CONFIG_ENV_SIZE 8192 3796cb144bcSMacpaul Lin #define CONFIG_ENV_OVERWRITE 3806cb144bcSMacpaul Lin 3816cb144bcSMacpaul Lin #endif /* __CONFIG_H */ 382