1*6cb144bcSMacpaul Lin /* 2*6cb144bcSMacpaul Lin * Copyright (C) 2011 Andes Technology Corporation 3*6cb144bcSMacpaul Lin * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4*6cb144bcSMacpaul Lin * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5*6cb144bcSMacpaul Lin * 6*6cb144bcSMacpaul Lin * See file CREDITS for list of people who contributed to this 7*6cb144bcSMacpaul Lin * project. 8*6cb144bcSMacpaul Lin * 9*6cb144bcSMacpaul Lin * This program is free software; you can redistribute it and/or modify 10*6cb144bcSMacpaul Lin * it under the terms of the GNU General Public License as published by 11*6cb144bcSMacpaul Lin * the Free Software Foundation; either version 2 of the License, or 12*6cb144bcSMacpaul Lin * (at your option) any later version. 13*6cb144bcSMacpaul Lin * 14*6cb144bcSMacpaul Lin * This program is distributed in the hope that it will be useful, 15*6cb144bcSMacpaul Lin * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*6cb144bcSMacpaul Lin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*6cb144bcSMacpaul Lin * GNU General Public License for more details. 18*6cb144bcSMacpaul Lin * 19*6cb144bcSMacpaul Lin * You should have received a copy of the GNU General Public License 20*6cb144bcSMacpaul Lin * along with this program; if not, write to the Free Software 21*6cb144bcSMacpaul Lin * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22*6cb144bcSMacpaul Lin */ 23*6cb144bcSMacpaul Lin 24*6cb144bcSMacpaul Lin #ifndef __CONFIG_H 25*6cb144bcSMacpaul Lin #define __CONFIG_H 26*6cb144bcSMacpaul Lin 27*6cb144bcSMacpaul Lin #include <asm/arch/ag101.h> 28*6cb144bcSMacpaul Lin 29*6cb144bcSMacpaul Lin /* 30*6cb144bcSMacpaul Lin * CPU and Board Configuration Options 31*6cb144bcSMacpaul Lin */ 32*6cb144bcSMacpaul Lin #define CONFIG_ADP_AG101P 33*6cb144bcSMacpaul Lin 34*6cb144bcSMacpaul Lin #define CONFIG_USE_INTERRUPT 35*6cb144bcSMacpaul Lin 36*6cb144bcSMacpaul Lin #define CONFIG_SKIP_LOWLEVEL_INIT 37*6cb144bcSMacpaul Lin 38*6cb144bcSMacpaul Lin #ifndef CONFIG_SKIP_LOWLEVEL_INIT 39*6cb144bcSMacpaul Lin #define CONFIG_MEM_REMAP 40*6cb144bcSMacpaul Lin #endif 41*6cb144bcSMacpaul Lin 42*6cb144bcSMacpaul Lin #ifdef CONFIG_SKIP_LOWLEVEL_INIT 43*6cb144bcSMacpaul Lin #define CONFIG_SYS_TEXT_BASE 0x03200000 44*6cb144bcSMacpaul Lin #else 45*6cb144bcSMacpaul Lin #define CONFIG_SYS_TEXT_BASE 0x00000000 46*6cb144bcSMacpaul Lin #endif 47*6cb144bcSMacpaul Lin 48*6cb144bcSMacpaul Lin /* 49*6cb144bcSMacpaul Lin * Timer 50*6cb144bcSMacpaul Lin */ 51*6cb144bcSMacpaul Lin 52*6cb144bcSMacpaul Lin /* 53*6cb144bcSMacpaul Lin * According to the discussion in u-boot mailing list before, 54*6cb144bcSMacpaul Lin * CONFIG_SYS_HZ at 1000 is mandatory. 55*6cb144bcSMacpaul Lin */ 56*6cb144bcSMacpaul Lin #define CONFIG_SYS_HZ 1000 57*6cb144bcSMacpaul Lin #define CONFIG_SYS_CLK_FREQ 39062500 58*6cb144bcSMacpaul Lin #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 59*6cb144bcSMacpaul Lin 60*6cb144bcSMacpaul Lin /* 61*6cb144bcSMacpaul Lin * Use Externel CLOCK or PCLK 62*6cb144bcSMacpaul Lin */ 63*6cb144bcSMacpaul Lin #undef CONFIG_FTRTC010_EXTCLK 64*6cb144bcSMacpaul Lin 65*6cb144bcSMacpaul Lin #ifndef CONFIG_FTRTC010_EXTCLK 66*6cb144bcSMacpaul Lin #define CONFIG_FTRTC010_PCLK 67*6cb144bcSMacpaul Lin #endif 68*6cb144bcSMacpaul Lin 69*6cb144bcSMacpaul Lin #ifdef CONFIG_FTRTC010_EXTCLK 70*6cb144bcSMacpaul Lin #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 71*6cb144bcSMacpaul Lin #else 72*6cb144bcSMacpaul Lin #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 73*6cb144bcSMacpaul Lin #endif 74*6cb144bcSMacpaul Lin 75*6cb144bcSMacpaul Lin #define TIMER_LOAD_VAL 0xffffffff 76*6cb144bcSMacpaul Lin 77*6cb144bcSMacpaul Lin /* 78*6cb144bcSMacpaul Lin * Real Time Clock 79*6cb144bcSMacpaul Lin */ 80*6cb144bcSMacpaul Lin #define CONFIG_RTC_FTRTC010 81*6cb144bcSMacpaul Lin 82*6cb144bcSMacpaul Lin /* 83*6cb144bcSMacpaul Lin * Real Time Clock Divider 84*6cb144bcSMacpaul Lin * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 85*6cb144bcSMacpaul Lin */ 86*6cb144bcSMacpaul Lin #define OSC_5MHZ (5*1000000) 87*6cb144bcSMacpaul Lin #define OSC_CLK (4*OSC_5MHZ) 88*6cb144bcSMacpaul Lin #define RTC_DIV_COUNT (0.5) /* Why?? */ 89*6cb144bcSMacpaul Lin 90*6cb144bcSMacpaul Lin /* 91*6cb144bcSMacpaul Lin * Serial console configuration 92*6cb144bcSMacpaul Lin */ 93*6cb144bcSMacpaul Lin 94*6cb144bcSMacpaul Lin /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 95*6cb144bcSMacpaul Lin #define CONFIG_BAUDRATE 38400 96*6cb144bcSMacpaul Lin #define CONFIG_CONS_INDEX 1 97*6cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550 98*6cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_SERIAL 99*6cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 100*6cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_REG_SIZE -4 101*6cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 102*6cb144bcSMacpaul Lin 103*6cb144bcSMacpaul Lin /* valid baudrates */ 104*6cb144bcSMacpaul Lin #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 105*6cb144bcSMacpaul Lin 106*6cb144bcSMacpaul Lin /* 107*6cb144bcSMacpaul Lin * Ethernet 108*6cb144bcSMacpaul Lin */ 109*6cb144bcSMacpaul Lin #define CONFIG_FTMAC100 110*6cb144bcSMacpaul Lin 111*6cb144bcSMacpaul Lin #define CONFIG_BOOTDELAY 3 112*6cb144bcSMacpaul Lin 113*6cb144bcSMacpaul Lin /* 114*6cb144bcSMacpaul Lin * SD (MMC) controller 115*6cb144bcSMacpaul Lin */ 116*6cb144bcSMacpaul Lin #define CONFIG_MMC 117*6cb144bcSMacpaul Lin #define CONFIG_CMD_MMC 118*6cb144bcSMacpaul Lin #define CONFIG_GENERIC_MMC 119*6cb144bcSMacpaul Lin #define CONFIG_DOS_PARTITION 120*6cb144bcSMacpaul Lin #define CONFIG_FTSDC010 121*6cb144bcSMacpaul Lin #define CONFIG_FTSDC010_NUMBER 1 122*6cb144bcSMacpaul Lin #define CONFIG_CMD_FAT 123*6cb144bcSMacpaul Lin 124*6cb144bcSMacpaul Lin /* 125*6cb144bcSMacpaul Lin * Command line configuration. 126*6cb144bcSMacpaul Lin */ 127*6cb144bcSMacpaul Lin #include <config_cmd_default.h> 128*6cb144bcSMacpaul Lin 129*6cb144bcSMacpaul Lin #define CONFIG_CMD_CACHE 130*6cb144bcSMacpaul Lin #define CONFIG_CMD_DATE 131*6cb144bcSMacpaul Lin #define CONFIG_CMD_PING 132*6cb144bcSMacpaul Lin 133*6cb144bcSMacpaul Lin /* 134*6cb144bcSMacpaul Lin * Miscellaneous configurable options 135*6cb144bcSMacpaul Lin */ 136*6cb144bcSMacpaul Lin #define CONFIG_SYS_LONGHELP /* undef to save memory */ 137*6cb144bcSMacpaul Lin #define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */ 138*6cb144bcSMacpaul Lin #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 139*6cb144bcSMacpaul Lin 140*6cb144bcSMacpaul Lin /* Print Buffer Size */ 141*6cb144bcSMacpaul Lin #define CONFIG_SYS_PBSIZE \ 142*6cb144bcSMacpaul Lin (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 143*6cb144bcSMacpaul Lin 144*6cb144bcSMacpaul Lin /* max number of command args */ 145*6cb144bcSMacpaul Lin #define CONFIG_SYS_MAXARGS 16 146*6cb144bcSMacpaul Lin 147*6cb144bcSMacpaul Lin /* Boot Argument Buffer Size */ 148*6cb144bcSMacpaul Lin #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 149*6cb144bcSMacpaul Lin 150*6cb144bcSMacpaul Lin /* 151*6cb144bcSMacpaul Lin * Stack sizes 152*6cb144bcSMacpaul Lin * 153*6cb144bcSMacpaul Lin * The stack sizes are set up in start.S using the settings below 154*6cb144bcSMacpaul Lin */ 155*6cb144bcSMacpaul Lin #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ 156*6cb144bcSMacpaul Lin 157*6cb144bcSMacpaul Lin /* 158*6cb144bcSMacpaul Lin * Size of malloc() pool 159*6cb144bcSMacpaul Lin */ 160*6cb144bcSMacpaul Lin /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 161*6cb144bcSMacpaul Lin #define CONFIG_SYS_MALLOC_LEN (512 << 10) 162*6cb144bcSMacpaul Lin 163*6cb144bcSMacpaul Lin /* 164*6cb144bcSMacpaul Lin * size in bytes reserved for initial data 165*6cb144bcSMacpaul Lin */ 166*6cb144bcSMacpaul Lin #define CONFIG_SYS_GBL_DATA_SIZE 128 167*6cb144bcSMacpaul Lin 168*6cb144bcSMacpaul Lin /* 169*6cb144bcSMacpaul Lin * AHB Controller configuration 170*6cb144bcSMacpaul Lin */ 171*6cb144bcSMacpaul Lin #define CONFIG_FTAHBC020S 172*6cb144bcSMacpaul Lin 173*6cb144bcSMacpaul Lin #ifdef CONFIG_FTAHBC020S 174*6cb144bcSMacpaul Lin #include <faraday/ftahbc020s.h> 175*6cb144bcSMacpaul Lin 176*6cb144bcSMacpaul Lin /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 177*6cb144bcSMacpaul Lin #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 178*6cb144bcSMacpaul Lin 179*6cb144bcSMacpaul Lin /* 180*6cb144bcSMacpaul Lin * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 181*6cb144bcSMacpaul Lin * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 182*6cb144bcSMacpaul Lin * in C language. 183*6cb144bcSMacpaul Lin */ 184*6cb144bcSMacpaul Lin #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 185*6cb144bcSMacpaul Lin (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 186*6cb144bcSMacpaul Lin FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 187*6cb144bcSMacpaul Lin #endif 188*6cb144bcSMacpaul Lin 189*6cb144bcSMacpaul Lin /* 190*6cb144bcSMacpaul Lin * Watchdog 191*6cb144bcSMacpaul Lin */ 192*6cb144bcSMacpaul Lin #define CONFIG_FTWDT010_WATCHDOG 193*6cb144bcSMacpaul Lin 194*6cb144bcSMacpaul Lin /* 195*6cb144bcSMacpaul Lin * PMU Power controller configuration 196*6cb144bcSMacpaul Lin */ 197*6cb144bcSMacpaul Lin #define CONFIG_PMU 198*6cb144bcSMacpaul Lin #define CONFIG_FTPMU010_POWER 199*6cb144bcSMacpaul Lin 200*6cb144bcSMacpaul Lin #ifdef CONFIG_FTPMU010_POWER 201*6cb144bcSMacpaul Lin #include <faraday/ftpmu010.h> 202*6cb144bcSMacpaul Lin #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 203*6cb144bcSMacpaul Lin #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 204*6cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 205*6cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 206*6cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 207*6cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_CKE_DCSR | \ 208*6cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_DQM_DCSR | \ 209*6cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_SDCLK_DCSR) 210*6cb144bcSMacpaul Lin #endif 211*6cb144bcSMacpaul Lin 212*6cb144bcSMacpaul Lin /* 213*6cb144bcSMacpaul Lin * SDRAM controller configuration 214*6cb144bcSMacpaul Lin */ 215*6cb144bcSMacpaul Lin #define CONFIG_FTSDMC021 216*6cb144bcSMacpaul Lin 217*6cb144bcSMacpaul Lin #ifdef CONFIG_FTSDMC021 218*6cb144bcSMacpaul Lin #include <faraday/ftsdmc021.h> 219*6cb144bcSMacpaul Lin 220*6cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 221*6cb144bcSMacpaul Lin FTSDMC021_TP1_TRP(1) | \ 222*6cb144bcSMacpaul Lin FTSDMC021_TP1_TRCD(1) | \ 223*6cb144bcSMacpaul Lin FTSDMC021_TP1_TRF(3) | \ 224*6cb144bcSMacpaul Lin FTSDMC021_TP1_TWR(1) | \ 225*6cb144bcSMacpaul Lin FTSDMC021_TP1_TCL(2)) 226*6cb144bcSMacpaul Lin 227*6cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 228*6cb144bcSMacpaul Lin FTSDMC021_TP2_INI_REFT(8) | \ 229*6cb144bcSMacpaul Lin FTSDMC021_TP2_REF_INTV(0x180)) 230*6cb144bcSMacpaul Lin 231*6cb144bcSMacpaul Lin /* 232*6cb144bcSMacpaul Lin * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 233*6cb144bcSMacpaul Lin * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 234*6cb144bcSMacpaul Lin * C language. 235*6cb144bcSMacpaul Lin */ 236*6cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 237*6cb144bcSMacpaul Lin FTSDMC021_CR1_DSZ(3) | \ 238*6cb144bcSMacpaul Lin FTSDMC021_CR1_MBW(2) | \ 239*6cb144bcSMacpaul Lin FTSDMC021_CR1_BNKSIZE(6)) 240*6cb144bcSMacpaul Lin 241*6cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 242*6cb144bcSMacpaul Lin FTSDMC021_CR2_IREF | \ 243*6cb144bcSMacpaul Lin FTSDMC021_CR2_ISMR) 244*6cb144bcSMacpaul Lin 245*6cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 246*6cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 247*6cb144bcSMacpaul Lin CONFIG_SYS_FTSDMC021_BANK0_BASE) 248*6cb144bcSMacpaul Lin 249*6cb144bcSMacpaul Lin #endif 250*6cb144bcSMacpaul Lin 251*6cb144bcSMacpaul Lin /* 252*6cb144bcSMacpaul Lin * Physical Memory Map 253*6cb144bcSMacpaul Lin */ 254*6cb144bcSMacpaul Lin #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT) 255*6cb144bcSMacpaul Lin #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 256*6cb144bcSMacpaul Lin #if defined(CONFIG_MEM_REMAP) 257*6cb144bcSMacpaul Lin #define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/ 258*6cb144bcSMacpaul Lin #endif 259*6cb144bcSMacpaul Lin #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ 260*6cb144bcSMacpaul Lin #define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */ 261*6cb144bcSMacpaul Lin #endif 262*6cb144bcSMacpaul Lin 263*6cb144bcSMacpaul Lin #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 264*6cb144bcSMacpaul Lin #define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */ 265*6cb144bcSMacpaul Lin 266*6cb144bcSMacpaul Lin #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 267*6cb144bcSMacpaul Lin 268*6cb144bcSMacpaul Lin #ifdef CONFIG_MEM_REMAP 269*6cb144bcSMacpaul Lin #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 270*6cb144bcSMacpaul Lin GENERATED_GBL_DATA_SIZE) 271*6cb144bcSMacpaul Lin #else 272*6cb144bcSMacpaul Lin #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 273*6cb144bcSMacpaul Lin GENERATED_GBL_DATA_SIZE) 274*6cb144bcSMacpaul Lin #endif /* CONFIG_MEM_REMAP */ 275*6cb144bcSMacpaul Lin 276*6cb144bcSMacpaul Lin /* 277*6cb144bcSMacpaul Lin * Load address and memory test area should agree with 278*6cb144bcSMacpaul Lin * arch/nds32/config.mk. Be careful not to overwrite U-boot itself. 279*6cb144bcSMacpaul Lin */ 280*6cb144bcSMacpaul Lin #define CONFIG_SYS_LOAD_ADDR 0x300000 281*6cb144bcSMacpaul Lin 282*6cb144bcSMacpaul Lin /* memtest works on 63 MB in DRAM */ 283*6cb144bcSMacpaul Lin #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 284*6cb144bcSMacpaul Lin #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 285*6cb144bcSMacpaul Lin 286*6cb144bcSMacpaul Lin /* 287*6cb144bcSMacpaul Lin * Static memory controller configuration 288*6cb144bcSMacpaul Lin */ 289*6cb144bcSMacpaul Lin #define CONFIG_FTSMC020 290*6cb144bcSMacpaul Lin 291*6cb144bcSMacpaul Lin #ifdef CONFIG_FTSMC020 292*6cb144bcSMacpaul Lin #include <faraday/ftsmc020.h> 293*6cb144bcSMacpaul Lin 294*6cb144bcSMacpaul Lin #define CONFIG_SYS_FTSMC020_CONFIGS { \ 295*6cb144bcSMacpaul Lin { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 296*6cb144bcSMacpaul Lin { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 297*6cb144bcSMacpaul Lin } 298*6cb144bcSMacpaul Lin 299*6cb144bcSMacpaul Lin #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 300*6cb144bcSMacpaul Lin #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 301*6cb144bcSMacpaul Lin FTSMC020_BANK_SIZE_32M | \ 302*6cb144bcSMacpaul Lin FTSMC020_BANK_MBW_32) 303*6cb144bcSMacpaul Lin 304*6cb144bcSMacpaul Lin #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 305*6cb144bcSMacpaul Lin FTSMC020_TPR_AST(1) | \ 306*6cb144bcSMacpaul Lin FTSMC020_TPR_CTW(1) | \ 307*6cb144bcSMacpaul Lin FTSMC020_TPR_ATI(1) | \ 308*6cb144bcSMacpaul Lin FTSMC020_TPR_AT2(1) | \ 309*6cb144bcSMacpaul Lin FTSMC020_TPR_WTC(1) | \ 310*6cb144bcSMacpaul Lin FTSMC020_TPR_AHT(1) | \ 311*6cb144bcSMacpaul Lin FTSMC020_TPR_TRNA(1)) 312*6cb144bcSMacpaul Lin #endif 313*6cb144bcSMacpaul Lin 314*6cb144bcSMacpaul Lin /* 315*6cb144bcSMacpaul Lin * FLASH on ADP_AG101P is connected to BANK0 316*6cb144bcSMacpaul Lin * Just disalbe the other BANK to avoid detection error. 317*6cb144bcSMacpaul Lin */ 318*6cb144bcSMacpaul Lin #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 319*6cb144bcSMacpaul Lin FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 320*6cb144bcSMacpaul Lin FTSMC020_BANK_SIZE_32M | \ 321*6cb144bcSMacpaul Lin FTSMC020_BANK_MBW_32) 322*6cb144bcSMacpaul Lin 323*6cb144bcSMacpaul Lin #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 324*6cb144bcSMacpaul Lin FTSMC020_TPR_CTW(3) | \ 325*6cb144bcSMacpaul Lin FTSMC020_TPR_ATI(0xf) | \ 326*6cb144bcSMacpaul Lin FTSMC020_TPR_AT2(3) | \ 327*6cb144bcSMacpaul Lin FTSMC020_TPR_WTC(3) | \ 328*6cb144bcSMacpaul Lin FTSMC020_TPR_AHT(3) | \ 329*6cb144bcSMacpaul Lin FTSMC020_TPR_TRNA(0xf)) 330*6cb144bcSMacpaul Lin 331*6cb144bcSMacpaul Lin #define FTSMC020_BANK1_CONFIG (0x00) 332*6cb144bcSMacpaul Lin #define FTSMC020_BANK1_TIMING (0x00) 333*6cb144bcSMacpaul Lin #endif /* CONFIG_FTSMC020 */ 334*6cb144bcSMacpaul Lin 335*6cb144bcSMacpaul Lin /* 336*6cb144bcSMacpaul Lin * FLASH and environment organization 337*6cb144bcSMacpaul Lin */ 338*6cb144bcSMacpaul Lin /* use CFI framework */ 339*6cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_CFI 340*6cb144bcSMacpaul Lin #define CONFIG_FLASH_CFI_DRIVER 341*6cb144bcSMacpaul Lin 342*6cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 343*6cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 344*6cb144bcSMacpaul Lin 345*6cb144bcSMacpaul Lin /* support JEDEC */ 346*6cb144bcSMacpaul Lin 347*6cb144bcSMacpaul Lin /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 348*6cb144bcSMacpaul Lin #ifdef CONFIG_SKIP_LOWLEVEL_INIT 349*6cb144bcSMacpaul Lin #define PHYS_FLASH_1 0x80400000 /* BANK 1 */ 350*6cb144bcSMacpaul Lin #else /* !CONFIG_SKIP_LOWLEVEL_INIT */ 351*6cb144bcSMacpaul Lin #ifdef CONFIG_MEM_REMAP 352*6cb144bcSMacpaul Lin #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 353*6cb144bcSMacpaul Lin #else 354*6cb144bcSMacpaul Lin #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 355*6cb144bcSMacpaul Lin #endif /* CONFIG_MEM_REMAP */ 356*6cb144bcSMacpaul Lin #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 357*6cb144bcSMacpaul Lin 358*6cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 359*6cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 360*6cb144bcSMacpaul Lin #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 361*6cb144bcSMacpaul Lin 362*6cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 363*6cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 364*6cb144bcSMacpaul Lin 365*6cb144bcSMacpaul Lin /* max number of memory banks */ 366*6cb144bcSMacpaul Lin /* 367*6cb144bcSMacpaul Lin * There are 4 banks supported for this Controller, 368*6cb144bcSMacpaul Lin * but we have only 1 bank connected to flash on board 369*6cb144bcSMacpaul Lin */ 370*6cb144bcSMacpaul Lin #define CONFIG_SYS_MAX_FLASH_BANKS 1 371*6cb144bcSMacpaul Lin 372*6cb144bcSMacpaul Lin /* max number of sectors on one chip */ 373*6cb144bcSMacpaul Lin #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2) 374*6cb144bcSMacpaul Lin #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 375*6cb144bcSMacpaul Lin #define CONFIG_SYS_MAX_FLASH_SECT 128 376*6cb144bcSMacpaul Lin 377*6cb144bcSMacpaul Lin /* environments */ 378*6cb144bcSMacpaul Lin #define CONFIG_ENV_IS_IN_FLASH 379*6cb144bcSMacpaul Lin #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 380*6cb144bcSMacpaul Lin #define CONFIG_ENV_SIZE 8192 381*6cb144bcSMacpaul Lin #define CONFIG_ENV_OVERWRITE 382*6cb144bcSMacpaul Lin 383*6cb144bcSMacpaul Lin #endif /* __CONFIG_H */ 384