16cb144bcSMacpaul Lin /* 26cb144bcSMacpaul Lin * Copyright (C) 2011 Andes Technology Corporation 36cb144bcSMacpaul Lin * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 46cb144bcSMacpaul Lin * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 56cb144bcSMacpaul Lin * 66cb144bcSMacpaul Lin * See file CREDITS for list of people who contributed to this 76cb144bcSMacpaul Lin * project. 86cb144bcSMacpaul Lin * 96cb144bcSMacpaul Lin * This program is free software; you can redistribute it and/or modify 106cb144bcSMacpaul Lin * it under the terms of the GNU General Public License as published by 116cb144bcSMacpaul Lin * the Free Software Foundation; either version 2 of the License, or 126cb144bcSMacpaul Lin * (at your option) any later version. 136cb144bcSMacpaul Lin * 146cb144bcSMacpaul Lin * This program is distributed in the hope that it will be useful, 156cb144bcSMacpaul Lin * but WITHOUT ANY WARRANTY; without even the implied warranty of 166cb144bcSMacpaul Lin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 176cb144bcSMacpaul Lin * GNU General Public License for more details. 186cb144bcSMacpaul Lin * 196cb144bcSMacpaul Lin * You should have received a copy of the GNU General Public License 206cb144bcSMacpaul Lin * along with this program; if not, write to the Free Software 216cb144bcSMacpaul Lin * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 226cb144bcSMacpaul Lin */ 236cb144bcSMacpaul Lin 246cb144bcSMacpaul Lin #ifndef __CONFIG_H 256cb144bcSMacpaul Lin #define __CONFIG_H 266cb144bcSMacpaul Lin 276cb144bcSMacpaul Lin #include <asm/arch/ag101.h> 286cb144bcSMacpaul Lin 296cb144bcSMacpaul Lin /* 306cb144bcSMacpaul Lin * CPU and Board Configuration Options 316cb144bcSMacpaul Lin */ 326cb144bcSMacpaul Lin #define CONFIG_ADP_AG101P 336cb144bcSMacpaul Lin 346cb144bcSMacpaul Lin #define CONFIG_USE_INTERRUPT 356cb144bcSMacpaul Lin 366cb144bcSMacpaul Lin #define CONFIG_SKIP_LOWLEVEL_INIT 376cb144bcSMacpaul Lin 386cb144bcSMacpaul Lin #ifndef CONFIG_SKIP_LOWLEVEL_INIT 396cb144bcSMacpaul Lin #define CONFIG_MEM_REMAP 406cb144bcSMacpaul Lin #endif 416cb144bcSMacpaul Lin 426cb144bcSMacpaul Lin #ifdef CONFIG_SKIP_LOWLEVEL_INIT 436cb144bcSMacpaul Lin #define CONFIG_SYS_TEXT_BASE 0x03200000 446cb144bcSMacpaul Lin #else 456cb144bcSMacpaul Lin #define CONFIG_SYS_TEXT_BASE 0x00000000 466cb144bcSMacpaul Lin #endif 476cb144bcSMacpaul Lin 486cb144bcSMacpaul Lin /* 496cb144bcSMacpaul Lin * Timer 506cb144bcSMacpaul Lin */ 516cb144bcSMacpaul Lin 526cb144bcSMacpaul Lin /* 536cb144bcSMacpaul Lin * According to the discussion in u-boot mailing list before, 546cb144bcSMacpaul Lin * CONFIG_SYS_HZ at 1000 is mandatory. 556cb144bcSMacpaul Lin */ 566cb144bcSMacpaul Lin #define CONFIG_SYS_HZ 1000 576cb144bcSMacpaul Lin #define CONFIG_SYS_CLK_FREQ 39062500 586cb144bcSMacpaul Lin #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 596cb144bcSMacpaul Lin 606cb144bcSMacpaul Lin /* 616cb144bcSMacpaul Lin * Use Externel CLOCK or PCLK 626cb144bcSMacpaul Lin */ 636cb144bcSMacpaul Lin #undef CONFIG_FTRTC010_EXTCLK 646cb144bcSMacpaul Lin 656cb144bcSMacpaul Lin #ifndef CONFIG_FTRTC010_EXTCLK 666cb144bcSMacpaul Lin #define CONFIG_FTRTC010_PCLK 676cb144bcSMacpaul Lin #endif 686cb144bcSMacpaul Lin 696cb144bcSMacpaul Lin #ifdef CONFIG_FTRTC010_EXTCLK 706cb144bcSMacpaul Lin #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 716cb144bcSMacpaul Lin #else 726cb144bcSMacpaul Lin #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 736cb144bcSMacpaul Lin #endif 746cb144bcSMacpaul Lin 756cb144bcSMacpaul Lin #define TIMER_LOAD_VAL 0xffffffff 766cb144bcSMacpaul Lin 776cb144bcSMacpaul Lin /* 786cb144bcSMacpaul Lin * Real Time Clock 796cb144bcSMacpaul Lin */ 806cb144bcSMacpaul Lin #define CONFIG_RTC_FTRTC010 816cb144bcSMacpaul Lin 826cb144bcSMacpaul Lin /* 836cb144bcSMacpaul Lin * Real Time Clock Divider 846cb144bcSMacpaul Lin * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 856cb144bcSMacpaul Lin */ 866cb144bcSMacpaul Lin #define OSC_5MHZ (5*1000000) 876cb144bcSMacpaul Lin #define OSC_CLK (4*OSC_5MHZ) 886cb144bcSMacpaul Lin #define RTC_DIV_COUNT (0.5) /* Why?? */ 896cb144bcSMacpaul Lin 906cb144bcSMacpaul Lin /* 916cb144bcSMacpaul Lin * Serial console configuration 926cb144bcSMacpaul Lin */ 936cb144bcSMacpaul Lin 946cb144bcSMacpaul Lin /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 956cb144bcSMacpaul Lin #define CONFIG_BAUDRATE 38400 966cb144bcSMacpaul Lin #define CONFIG_CONS_INDEX 1 976cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550 986cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_SERIAL 996cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 1006cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_REG_SIZE -4 1016cb144bcSMacpaul Lin #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 1026cb144bcSMacpaul Lin 1036cb144bcSMacpaul Lin /* 1046cb144bcSMacpaul Lin * Ethernet 1056cb144bcSMacpaul Lin */ 1066cb144bcSMacpaul Lin #define CONFIG_FTMAC100 1076cb144bcSMacpaul Lin 1086cb144bcSMacpaul Lin #define CONFIG_BOOTDELAY 3 1096cb144bcSMacpaul Lin 1106cb144bcSMacpaul Lin /* 1116cb144bcSMacpaul Lin * SD (MMC) controller 1126cb144bcSMacpaul Lin */ 1136cb144bcSMacpaul Lin #define CONFIG_MMC 1146cb144bcSMacpaul Lin #define CONFIG_CMD_MMC 1156cb144bcSMacpaul Lin #define CONFIG_GENERIC_MMC 1166cb144bcSMacpaul Lin #define CONFIG_DOS_PARTITION 1176cb144bcSMacpaul Lin #define CONFIG_FTSDC010 1186cb144bcSMacpaul Lin #define CONFIG_FTSDC010_NUMBER 1 1196cb144bcSMacpaul Lin #define CONFIG_CMD_FAT 1206cb144bcSMacpaul Lin 1216cb144bcSMacpaul Lin /* 1226cb144bcSMacpaul Lin * Command line configuration. 1236cb144bcSMacpaul Lin */ 1246cb144bcSMacpaul Lin #include <config_cmd_default.h> 1256cb144bcSMacpaul Lin 1266cb144bcSMacpaul Lin #define CONFIG_CMD_CACHE 1276cb144bcSMacpaul Lin #define CONFIG_CMD_DATE 1286cb144bcSMacpaul Lin #define CONFIG_CMD_PING 1296cb144bcSMacpaul Lin 1306cb144bcSMacpaul Lin /* 1316cb144bcSMacpaul Lin * Miscellaneous configurable options 1326cb144bcSMacpaul Lin */ 1336cb144bcSMacpaul Lin #define CONFIG_SYS_LONGHELP /* undef to save memory */ 1346cb144bcSMacpaul Lin #define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */ 1356cb144bcSMacpaul Lin #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 1366cb144bcSMacpaul Lin 1376cb144bcSMacpaul Lin /* Print Buffer Size */ 1386cb144bcSMacpaul Lin #define CONFIG_SYS_PBSIZE \ 1396cb144bcSMacpaul Lin (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 1406cb144bcSMacpaul Lin 1416cb144bcSMacpaul Lin /* max number of command args */ 1426cb144bcSMacpaul Lin #define CONFIG_SYS_MAXARGS 16 1436cb144bcSMacpaul Lin 1446cb144bcSMacpaul Lin /* Boot Argument Buffer Size */ 1456cb144bcSMacpaul Lin #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 1466cb144bcSMacpaul Lin 1476cb144bcSMacpaul Lin /* 1486cb144bcSMacpaul Lin * Size of malloc() pool 1496cb144bcSMacpaul Lin */ 1506cb144bcSMacpaul Lin /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 1516cb144bcSMacpaul Lin #define CONFIG_SYS_MALLOC_LEN (512 << 10) 1526cb144bcSMacpaul Lin 1536cb144bcSMacpaul Lin /* 1546cb144bcSMacpaul Lin * size in bytes reserved for initial data 1556cb144bcSMacpaul Lin */ 1566cb144bcSMacpaul Lin #define CONFIG_SYS_GBL_DATA_SIZE 128 1576cb144bcSMacpaul Lin 1586cb144bcSMacpaul Lin /* 1596cb144bcSMacpaul Lin * AHB Controller configuration 1606cb144bcSMacpaul Lin */ 1616cb144bcSMacpaul Lin #define CONFIG_FTAHBC020S 1626cb144bcSMacpaul Lin 1636cb144bcSMacpaul Lin #ifdef CONFIG_FTAHBC020S 1646cb144bcSMacpaul Lin #include <faraday/ftahbc020s.h> 1656cb144bcSMacpaul Lin 1666cb144bcSMacpaul Lin /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 1676cb144bcSMacpaul Lin #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 1686cb144bcSMacpaul Lin 1696cb144bcSMacpaul Lin /* 1706cb144bcSMacpaul Lin * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 1716cb144bcSMacpaul Lin * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 1726cb144bcSMacpaul Lin * in C language. 1736cb144bcSMacpaul Lin */ 1746cb144bcSMacpaul Lin #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 1756cb144bcSMacpaul Lin (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 1766cb144bcSMacpaul Lin FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 1776cb144bcSMacpaul Lin #endif 1786cb144bcSMacpaul Lin 1796cb144bcSMacpaul Lin /* 1806cb144bcSMacpaul Lin * Watchdog 1816cb144bcSMacpaul Lin */ 1826cb144bcSMacpaul Lin #define CONFIG_FTWDT010_WATCHDOG 1836cb144bcSMacpaul Lin 1846cb144bcSMacpaul Lin /* 1856cb144bcSMacpaul Lin * PMU Power controller configuration 1866cb144bcSMacpaul Lin */ 1876cb144bcSMacpaul Lin #define CONFIG_PMU 1886cb144bcSMacpaul Lin #define CONFIG_FTPMU010_POWER 1896cb144bcSMacpaul Lin 1906cb144bcSMacpaul Lin #ifdef CONFIG_FTPMU010_POWER 1916cb144bcSMacpaul Lin #include <faraday/ftpmu010.h> 1926cb144bcSMacpaul Lin #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 1936cb144bcSMacpaul Lin #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 1946cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 1956cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 1966cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 1976cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_CKE_DCSR | \ 1986cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_DQM_DCSR | \ 1996cb144bcSMacpaul Lin FTPMU010_SDRAMHTC_SDCLK_DCSR) 2006cb144bcSMacpaul Lin #endif 2016cb144bcSMacpaul Lin 2026cb144bcSMacpaul Lin /* 2036cb144bcSMacpaul Lin * SDRAM controller configuration 2046cb144bcSMacpaul Lin */ 2056cb144bcSMacpaul Lin #define CONFIG_FTSDMC021 2066cb144bcSMacpaul Lin 2076cb144bcSMacpaul Lin #ifdef CONFIG_FTSDMC021 2086cb144bcSMacpaul Lin #include <faraday/ftsdmc021.h> 2096cb144bcSMacpaul Lin 2106cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 2116cb144bcSMacpaul Lin FTSDMC021_TP1_TRP(1) | \ 2126cb144bcSMacpaul Lin FTSDMC021_TP1_TRCD(1) | \ 2136cb144bcSMacpaul Lin FTSDMC021_TP1_TRF(3) | \ 2146cb144bcSMacpaul Lin FTSDMC021_TP1_TWR(1) | \ 2156cb144bcSMacpaul Lin FTSDMC021_TP1_TCL(2)) 2166cb144bcSMacpaul Lin 2176cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 2186cb144bcSMacpaul Lin FTSDMC021_TP2_INI_REFT(8) | \ 2196cb144bcSMacpaul Lin FTSDMC021_TP2_REF_INTV(0x180)) 2206cb144bcSMacpaul Lin 2216cb144bcSMacpaul Lin /* 2226cb144bcSMacpaul Lin * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 2236cb144bcSMacpaul Lin * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 2246cb144bcSMacpaul Lin * C language. 2256cb144bcSMacpaul Lin */ 2266cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 2276cb144bcSMacpaul Lin FTSDMC021_CR1_DSZ(3) | \ 2286cb144bcSMacpaul Lin FTSDMC021_CR1_MBW(2) | \ 2296cb144bcSMacpaul Lin FTSDMC021_CR1_BNKSIZE(6)) 2306cb144bcSMacpaul Lin 2316cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 2326cb144bcSMacpaul Lin FTSDMC021_CR2_IREF | \ 2336cb144bcSMacpaul Lin FTSDMC021_CR2_ISMR) 2346cb144bcSMacpaul Lin 2356cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 2366cb144bcSMacpaul Lin #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 2376cb144bcSMacpaul Lin CONFIG_SYS_FTSDMC021_BANK0_BASE) 2386cb144bcSMacpaul Lin 239*3c016704Sken kuo #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 240*3c016704Sken kuo (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 241*3c016704Sken kuo #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 242*3c016704Sken kuo CONFIG_SYS_FTSDMC021_BANK1_BASE) 2436cb144bcSMacpaul Lin #endif 2446cb144bcSMacpaul Lin 2456cb144bcSMacpaul Lin /* 2466cb144bcSMacpaul Lin * Physical Memory Map 2476cb144bcSMacpaul Lin */ 2486cb144bcSMacpaul Lin #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT) 2496cb144bcSMacpaul Lin #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 2506cb144bcSMacpaul Lin #if defined(CONFIG_MEM_REMAP) 2516cb144bcSMacpaul Lin #define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/ 2526cb144bcSMacpaul Lin #endif 2536cb144bcSMacpaul Lin #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ 2546cb144bcSMacpaul Lin #define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */ 2556cb144bcSMacpaul Lin #endif 256*3c016704Sken kuo #define PHYS_SDRAM_1 \ 257*3c016704Sken kuo (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 2586cb144bcSMacpaul Lin 259*3c016704Sken kuo #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 2606cb144bcSMacpaul Lin #define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */ 261*3c016704Sken kuo #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 2626cb144bcSMacpaul Lin 2636cb144bcSMacpaul Lin #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 2646cb144bcSMacpaul Lin 2656cb144bcSMacpaul Lin #ifdef CONFIG_MEM_REMAP 2666cb144bcSMacpaul Lin #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 2676cb144bcSMacpaul Lin GENERATED_GBL_DATA_SIZE) 2686cb144bcSMacpaul Lin #else 2696cb144bcSMacpaul Lin #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 2706cb144bcSMacpaul Lin GENERATED_GBL_DATA_SIZE) 2716cb144bcSMacpaul Lin #endif /* CONFIG_MEM_REMAP */ 2726cb144bcSMacpaul Lin 2736cb144bcSMacpaul Lin /* 2746cb144bcSMacpaul Lin * Load address and memory test area should agree with 2756cb144bcSMacpaul Lin * arch/nds32/config.mk. Be careful not to overwrite U-boot itself. 2766cb144bcSMacpaul Lin */ 2776cb144bcSMacpaul Lin #define CONFIG_SYS_LOAD_ADDR 0x300000 2786cb144bcSMacpaul Lin 2796cb144bcSMacpaul Lin /* memtest works on 63 MB in DRAM */ 2806cb144bcSMacpaul Lin #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 2816cb144bcSMacpaul Lin #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 2826cb144bcSMacpaul Lin 2836cb144bcSMacpaul Lin /* 2846cb144bcSMacpaul Lin * Static memory controller configuration 2856cb144bcSMacpaul Lin */ 2866cb144bcSMacpaul Lin #define CONFIG_FTSMC020 2876cb144bcSMacpaul Lin 2886cb144bcSMacpaul Lin #ifdef CONFIG_FTSMC020 2896cb144bcSMacpaul Lin #include <faraday/ftsmc020.h> 2906cb144bcSMacpaul Lin 2916cb144bcSMacpaul Lin #define CONFIG_SYS_FTSMC020_CONFIGS { \ 2926cb144bcSMacpaul Lin { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 2936cb144bcSMacpaul Lin { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 2946cb144bcSMacpaul Lin } 2956cb144bcSMacpaul Lin 2966cb144bcSMacpaul Lin #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 2976cb144bcSMacpaul Lin #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 2986cb144bcSMacpaul Lin FTSMC020_BANK_SIZE_32M | \ 2996cb144bcSMacpaul Lin FTSMC020_BANK_MBW_32) 3006cb144bcSMacpaul Lin 3016cb144bcSMacpaul Lin #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 3026cb144bcSMacpaul Lin FTSMC020_TPR_AST(1) | \ 3036cb144bcSMacpaul Lin FTSMC020_TPR_CTW(1) | \ 3046cb144bcSMacpaul Lin FTSMC020_TPR_ATI(1) | \ 3056cb144bcSMacpaul Lin FTSMC020_TPR_AT2(1) | \ 3066cb144bcSMacpaul Lin FTSMC020_TPR_WTC(1) | \ 3076cb144bcSMacpaul Lin FTSMC020_TPR_AHT(1) | \ 3086cb144bcSMacpaul Lin FTSMC020_TPR_TRNA(1)) 3096cb144bcSMacpaul Lin #endif 3106cb144bcSMacpaul Lin 3116cb144bcSMacpaul Lin /* 3126cb144bcSMacpaul Lin * FLASH on ADP_AG101P is connected to BANK0 3136cb144bcSMacpaul Lin * Just disalbe the other BANK to avoid detection error. 3146cb144bcSMacpaul Lin */ 3156cb144bcSMacpaul Lin #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 3166cb144bcSMacpaul Lin FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 3176cb144bcSMacpaul Lin FTSMC020_BANK_SIZE_32M | \ 3186cb144bcSMacpaul Lin FTSMC020_BANK_MBW_32) 3196cb144bcSMacpaul Lin 3206cb144bcSMacpaul Lin #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 3216cb144bcSMacpaul Lin FTSMC020_TPR_CTW(3) | \ 3226cb144bcSMacpaul Lin FTSMC020_TPR_ATI(0xf) | \ 3236cb144bcSMacpaul Lin FTSMC020_TPR_AT2(3) | \ 3246cb144bcSMacpaul Lin FTSMC020_TPR_WTC(3) | \ 3256cb144bcSMacpaul Lin FTSMC020_TPR_AHT(3) | \ 3266cb144bcSMacpaul Lin FTSMC020_TPR_TRNA(0xf)) 3276cb144bcSMacpaul Lin 3286cb144bcSMacpaul Lin #define FTSMC020_BANK1_CONFIG (0x00) 3296cb144bcSMacpaul Lin #define FTSMC020_BANK1_TIMING (0x00) 3306cb144bcSMacpaul Lin #endif /* CONFIG_FTSMC020 */ 3316cb144bcSMacpaul Lin 3326cb144bcSMacpaul Lin /* 3336cb144bcSMacpaul Lin * FLASH and environment organization 3346cb144bcSMacpaul Lin */ 3356cb144bcSMacpaul Lin /* use CFI framework */ 3366cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_CFI 3376cb144bcSMacpaul Lin #define CONFIG_FLASH_CFI_DRIVER 3386cb144bcSMacpaul Lin 3396cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 3406cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 3416cb144bcSMacpaul Lin 3426cb144bcSMacpaul Lin /* support JEDEC */ 3436cb144bcSMacpaul Lin 3446cb144bcSMacpaul Lin /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 3456cb144bcSMacpaul Lin #ifdef CONFIG_SKIP_LOWLEVEL_INIT 3466cb144bcSMacpaul Lin #define PHYS_FLASH_1 0x80400000 /* BANK 1 */ 3476cb144bcSMacpaul Lin #else /* !CONFIG_SKIP_LOWLEVEL_INIT */ 3486cb144bcSMacpaul Lin #ifdef CONFIG_MEM_REMAP 3496cb144bcSMacpaul Lin #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 3506cb144bcSMacpaul Lin #else 3516cb144bcSMacpaul Lin #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 3526cb144bcSMacpaul Lin #endif /* CONFIG_MEM_REMAP */ 3536cb144bcSMacpaul Lin #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 3546cb144bcSMacpaul Lin 3556cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 3566cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 3576cb144bcSMacpaul Lin #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 3586cb144bcSMacpaul Lin 3596cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 3606cb144bcSMacpaul Lin #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 3616cb144bcSMacpaul Lin 3626cb144bcSMacpaul Lin /* max number of memory banks */ 3636cb144bcSMacpaul Lin /* 3646cb144bcSMacpaul Lin * There are 4 banks supported for this Controller, 3656cb144bcSMacpaul Lin * but we have only 1 bank connected to flash on board 3666cb144bcSMacpaul Lin */ 3676cb144bcSMacpaul Lin #define CONFIG_SYS_MAX_FLASH_BANKS 1 3686cb144bcSMacpaul Lin 3696cb144bcSMacpaul Lin /* max number of sectors on one chip */ 3706cb144bcSMacpaul Lin #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2) 3716cb144bcSMacpaul Lin #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 3726cb144bcSMacpaul Lin #define CONFIG_SYS_MAX_FLASH_SECT 128 3736cb144bcSMacpaul Lin 3746cb144bcSMacpaul Lin /* environments */ 3756cb144bcSMacpaul Lin #define CONFIG_ENV_IS_IN_FLASH 3766cb144bcSMacpaul Lin #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 3776cb144bcSMacpaul Lin #define CONFIG_ENV_SIZE 8192 3786cb144bcSMacpaul Lin #define CONFIG_ENV_OVERWRITE 3796cb144bcSMacpaul Lin 3806cb144bcSMacpaul Lin #endif /* __CONFIG_H */ 381