1 /* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch-ae3xx/ae3xx.h> 13 14 /* 15 * CPU and Board Configuration Options 16 */ 17 #define CONFIG_USE_INTERRUPT 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 21 #define CONFIG_SKIP_TRUNOFF_WATCHDOG 22 23 #define CONFIG_CMDLINE_EDITING 24 25 #define CONFIG_ARCH_MAP_SYSMEM 26 27 #define CONFIG_BOOTP_SEND_HOSTNAME 28 #define CONFIG_BOOTP_SERVERIP 29 30 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 31 #ifdef CONFIG_OF_CONTROL 32 #undef CONFIG_OF_SEPARATE 33 #define CONFIG_OF_EMBED 34 #endif 35 #endif 36 37 /* 38 * Timer 39 */ 40 #define CONFIG_SYS_CLK_FREQ 39062500 41 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 42 43 /* 44 * Use Externel CLOCK or PCLK 45 */ 46 #undef CONFIG_FTRTC010_EXTCLK 47 48 #ifndef CONFIG_FTRTC010_EXTCLK 49 #define CONFIG_FTRTC010_PCLK 50 #endif 51 52 #ifdef CONFIG_FTRTC010_EXTCLK 53 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 54 #else 55 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 56 #endif 57 58 #define TIMER_LOAD_VAL 0xffffffff 59 60 /* 61 * Real Time Clock 62 */ 63 #define CONFIG_RTC_FTRTC010 64 65 /* 66 * Real Time Clock Divider 67 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 68 */ 69 #define OSC_5MHZ (5*1000000) 70 #define OSC_CLK (4*OSC_5MHZ) 71 #define RTC_DIV_COUNT (0.5) /* Why?? */ 72 73 /* 74 * Serial console configuration 75 */ 76 77 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 78 #define CONFIG_CONS_INDEX 1 79 #define CONFIG_SYS_NS16550_SERIAL 80 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 81 #ifndef CONFIG_DM_SERIAL 82 #define CONFIG_SYS_NS16550_REG_SIZE -4 83 #endif 84 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 85 86 /* 87 * SD (MMC) controller 88 */ 89 #define CONFIG_FTSDC010_NUMBER 1 90 #define CONFIG_FTSDC010_SDIO 91 92 /* 93 * Miscellaneous configurable options 94 */ 95 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 96 97 /* 98 * Size of malloc() pool 99 */ 100 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 101 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 102 103 /* 104 * Physical Memory Map 105 */ 106 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 107 108 #define PHYS_SDRAM_1 \ 109 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 110 111 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 112 113 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 114 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 115 116 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 117 118 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 119 GENERATED_GBL_DATA_SIZE) 120 121 /* 122 * Load address and memory test area should agree with 123 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 124 */ 125 #define CONFIG_SYS_LOAD_ADDR 0x300000 126 127 /* memtest works on 63 MB in DRAM */ 128 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 129 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 130 131 /* 132 * Static memory controller configuration 133 */ 134 #define CONFIG_FTSMC020 135 136 #ifdef CONFIG_FTSMC020 137 #include <faraday/ftsmc020.h> 138 139 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 140 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 141 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 142 } 143 144 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 145 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 146 FTSMC020_BANK_SIZE_32M | \ 147 FTSMC020_BANK_MBW_32) 148 149 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 150 FTSMC020_TPR_AST(1) | \ 151 FTSMC020_TPR_CTW(1) | \ 152 FTSMC020_TPR_ATI(1) | \ 153 FTSMC020_TPR_AT2(1) | \ 154 FTSMC020_TPR_WTC(1) | \ 155 FTSMC020_TPR_AHT(1) | \ 156 FTSMC020_TPR_TRNA(1)) 157 #endif 158 159 /* 160 * FLASH on ADP_AG101P is connected to BANK0 161 * Just disalbe the other BANK to avoid detection error. 162 */ 163 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 164 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 165 FTSMC020_BANK_SIZE_32M | \ 166 FTSMC020_BANK_MBW_32) 167 168 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 169 FTSMC020_TPR_CTW(3) | \ 170 FTSMC020_TPR_ATI(0xf) | \ 171 FTSMC020_TPR_AT2(3) | \ 172 FTSMC020_TPR_WTC(3) | \ 173 FTSMC020_TPR_AHT(3) | \ 174 FTSMC020_TPR_TRNA(0xf)) 175 176 #define FTSMC020_BANK1_CONFIG (0x00) 177 #define FTSMC020_BANK1_TIMING (0x00) 178 #endif /* CONFIG_FTSMC020 */ 179 180 /* 181 * FLASH and environment organization 182 */ 183 /* use CFI framework */ 184 #define CONFIG_SYS_FLASH_CFI 185 #define CONFIG_FLASH_CFI_DRIVER 186 187 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 188 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 189 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 190 191 /* support JEDEC */ 192 #ifdef CONFIG_CFI_FLASH 193 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 194 #endif 195 196 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 197 #define PHYS_FLASH_1 0x88000000 /* BANK 0 */ 198 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 199 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 200 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 201 202 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 203 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 204 205 /* max number of memory banks */ 206 /* 207 * There are 4 banks supported for this Controller, 208 * but we have only 1 bank connected to flash on board 209 */ 210 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 211 #define CONFIG_SYS_MAX_FLASH_BANKS 1 212 #endif 213 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 214 215 /* max number of sectors on one chip */ 216 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 217 #define CONFIG_SYS_MAX_FLASH_SECT 512 218 219 /* environments */ 220 #define CONFIG_ENV_SPI_BUS 0 221 #define CONFIG_ENV_SPI_CS 0 222 #define CONFIG_ENV_SPI_MAX_HZ 50000000 223 #define CONFIG_ENV_SPI_MODE 0 224 #define CONFIG_ENV_SECT_SIZE 0x1000 225 #define CONFIG_ENV_OFFSET 0x140000 226 #define CONFIG_ENV_SIZE 8192 227 #define CONFIG_ENV_OVERWRITE 228 229 230 /* SPI FLASH */ 231 #define CONFIG_SF_DEFAULT_BUS 0 232 #define CONFIG_SF_DEFAULT_CS 0 233 #define CONFIG_SF_DEFAULT_SPEED 1000000 234 #define CONFIG_SF_DEFAULT_MODE 0 235 236 /* 237 * For booting Linux, the board info and command line data 238 * have to be in the first 16 MB of memory, since this is 239 * the maximum mapped by the Linux kernel during initialization. 240 */ 241 242 /* Initial Memory map for Linux*/ 243 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) 244 /* Increase max gunzip size */ 245 #define CONFIG_SYS_BOOTM_LEN (64 << 20) 246 247 #endif /* __CONFIG_H */ 248