1 /* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch-ae3xx/ae3xx.h> 13 14 /* 15 * CPU and Board Configuration Options 16 */ 17 #define CONFIG_USE_INTERRUPT 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 21 #define CONFIG_SKIP_TRUNOFF_WATCHDOG 22 23 #define CONFIG_CMDLINE_EDITING 24 #define CONFIG_PANIC_HANG 25 26 #define CONFIG_ARCH_MAP_SYSMEM 27 28 #define CONFIG_BOOTP_SEND_HOSTNAME 29 #define CONFIG_BOOTP_SERVERIP 30 31 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 32 #define CONFIG_SYS_TEXT_BASE 0x00500000 33 #ifdef CONFIG_OF_CONTROL 34 #undef CONFIG_OF_SEPARATE 35 #define CONFIG_OF_EMBED 36 #endif 37 #else 38 39 #define CONFIG_SYS_TEXT_BASE 0x80000000 40 #endif 41 42 /* 43 * Timer 44 */ 45 #define CONFIG_SYS_CLK_FREQ 39062500 46 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 47 48 /* 49 * Use Externel CLOCK or PCLK 50 */ 51 #undef CONFIG_FTRTC010_EXTCLK 52 53 #ifndef CONFIG_FTRTC010_EXTCLK 54 #define CONFIG_FTRTC010_PCLK 55 #endif 56 57 #ifdef CONFIG_FTRTC010_EXTCLK 58 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 59 #else 60 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 61 #endif 62 63 #define TIMER_LOAD_VAL 0xffffffff 64 65 /* 66 * Real Time Clock 67 */ 68 #define CONFIG_RTC_FTRTC010 69 70 /* 71 * Real Time Clock Divider 72 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 73 */ 74 #define OSC_5MHZ (5*1000000) 75 #define OSC_CLK (4*OSC_5MHZ) 76 #define RTC_DIV_COUNT (0.5) /* Why?? */ 77 78 /* 79 * Serial console configuration 80 */ 81 82 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 83 #define CONFIG_CONS_INDEX 1 84 #define CONFIG_SYS_NS16550_SERIAL 85 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 86 #ifndef CONFIG_DM_SERIAL 87 #define CONFIG_SYS_NS16550_REG_SIZE -4 88 #endif 89 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 90 91 /* 92 * SD (MMC) controller 93 */ 94 #define CONFIG_FTSDC010 95 #define CONFIG_FTSDC010_NUMBER 1 96 #define CONFIG_FTSDC010_SDIO 97 98 /* 99 * Miscellaneous configurable options 100 */ 101 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 102 103 /* 104 * Size of malloc() pool 105 */ 106 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 107 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 108 109 /* 110 * Physical Memory Map 111 */ 112 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 113 114 #define PHYS_SDRAM_1 \ 115 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 116 117 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 118 119 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 120 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 121 122 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 123 124 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 125 GENERATED_GBL_DATA_SIZE) 126 127 /* 128 * Load address and memory test area should agree with 129 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 130 */ 131 #define CONFIG_SYS_LOAD_ADDR 0x300000 132 133 /* memtest works on 63 MB in DRAM */ 134 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 135 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 136 137 /* 138 * Static memory controller configuration 139 */ 140 #define CONFIG_FTSMC020 141 142 #ifdef CONFIG_FTSMC020 143 #include <faraday/ftsmc020.h> 144 145 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 146 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 147 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 148 } 149 150 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 151 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 152 FTSMC020_BANK_SIZE_32M | \ 153 FTSMC020_BANK_MBW_32) 154 155 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 156 FTSMC020_TPR_AST(1) | \ 157 FTSMC020_TPR_CTW(1) | \ 158 FTSMC020_TPR_ATI(1) | \ 159 FTSMC020_TPR_AT2(1) | \ 160 FTSMC020_TPR_WTC(1) | \ 161 FTSMC020_TPR_AHT(1) | \ 162 FTSMC020_TPR_TRNA(1)) 163 #endif 164 165 /* 166 * FLASH on ADP_AG101P is connected to BANK0 167 * Just disalbe the other BANK to avoid detection error. 168 */ 169 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 170 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 171 FTSMC020_BANK_SIZE_32M | \ 172 FTSMC020_BANK_MBW_32) 173 174 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 175 FTSMC020_TPR_CTW(3) | \ 176 FTSMC020_TPR_ATI(0xf) | \ 177 FTSMC020_TPR_AT2(3) | \ 178 FTSMC020_TPR_WTC(3) | \ 179 FTSMC020_TPR_AHT(3) | \ 180 FTSMC020_TPR_TRNA(0xf)) 181 182 #define FTSMC020_BANK1_CONFIG (0x00) 183 #define FTSMC020_BANK1_TIMING (0x00) 184 #endif /* CONFIG_FTSMC020 */ 185 186 /* 187 * FLASH and environment organization 188 */ 189 /* use CFI framework */ 190 #define CONFIG_SYS_FLASH_CFI 191 #define CONFIG_FLASH_CFI_DRIVER 192 193 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 194 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 195 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 196 197 /* support JEDEC */ 198 #ifdef CONFIG_CFI_FLASH 199 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 200 #endif 201 202 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 203 #define PHYS_FLASH_1 0x88000000 /* BANK 0 */ 204 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 205 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 206 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 207 208 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 209 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 210 211 /* max number of memory banks */ 212 /* 213 * There are 4 banks supported for this Controller, 214 * but we have only 1 bank connected to flash on board 215 */ 216 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 217 #define CONFIG_SYS_MAX_FLASH_BANKS 1 218 #endif 219 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 220 221 /* max number of sectors on one chip */ 222 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 223 #define CONFIG_SYS_MAX_FLASH_SECT 512 224 225 /* environments */ 226 #define CONFIG_ENV_SPI_BUS 0 227 #define CONFIG_ENV_SPI_CS 0 228 #define CONFIG_ENV_SPI_MAX_HZ 50000000 229 #define CONFIG_ENV_SPI_MODE 0 230 #define CONFIG_ENV_SECT_SIZE 0x1000 231 #define CONFIG_ENV_OFFSET 0x140000 232 #define CONFIG_ENV_SIZE 8192 233 #define CONFIG_ENV_OVERWRITE 234 235 236 /* SPI FLASH */ 237 #define CONFIG_SF_DEFAULT_BUS 0 238 #define CONFIG_SF_DEFAULT_CS 0 239 #define CONFIG_SF_DEFAULT_SPEED 1000000 240 #define CONFIG_SF_DEFAULT_MODE 0 241 242 /* 243 * For booting Linux, the board info and command line data 244 * have to be in the first 16 MB of memory, since this is 245 * the maximum mapped by the Linux kernel during initialization. 246 */ 247 248 /* Initial Memory map for Linux*/ 249 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) 250 /* Increase max gunzip size */ 251 #define CONFIG_SYS_BOOTM_LEN (64 << 20) 252 253 #endif /* __CONFIG_H */ 254