1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2011 Andes Technology Corporation 4 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 5 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 #include <asm/arch-ae3xx/ae3xx.h> 12 13 /* 14 * CPU and Board Configuration Options 15 */ 16 #define CONFIG_USE_INTERRUPT 17 18 #define CONFIG_SKIP_LOWLEVEL_INIT 19 20 #define CONFIG_SKIP_TRUNOFF_WATCHDOG 21 22 #define CONFIG_ARCH_MAP_SYSMEM 23 24 #define CONFIG_BOOTP_SEND_HOSTNAME 25 #define CONFIG_BOOTP_SERVERIP 26 27 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 28 #ifdef CONFIG_OF_CONTROL 29 #undef CONFIG_OF_SEPARATE 30 #define CONFIG_OF_EMBED 31 #endif 32 #endif 33 34 /* 35 * Timer 36 */ 37 #define CONFIG_SYS_CLK_FREQ 39062500 38 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 39 40 /* 41 * Use Externel CLOCK or PCLK 42 */ 43 #undef CONFIG_FTRTC010_EXTCLK 44 45 #ifndef CONFIG_FTRTC010_EXTCLK 46 #define CONFIG_FTRTC010_PCLK 47 #endif 48 49 #ifdef CONFIG_FTRTC010_EXTCLK 50 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 51 #else 52 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 53 #endif 54 55 #define TIMER_LOAD_VAL 0xffffffff 56 57 /* 58 * Real Time Clock 59 */ 60 #define CONFIG_RTC_FTRTC010 61 62 /* 63 * Real Time Clock Divider 64 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 65 */ 66 #define OSC_5MHZ (5*1000000) 67 #define OSC_CLK (4*OSC_5MHZ) 68 #define RTC_DIV_COUNT (0.5) /* Why?? */ 69 70 /* 71 * Serial console configuration 72 */ 73 74 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 75 #define CONFIG_SYS_NS16550_SERIAL 76 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 77 #ifndef CONFIG_DM_SERIAL 78 #define CONFIG_SYS_NS16550_REG_SIZE -4 79 #endif 80 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 81 82 /* 83 * Miscellaneous configurable options 84 */ 85 86 /* 87 * Size of malloc() pool 88 */ 89 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 90 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 91 92 /* 93 * Physical Memory Map 94 */ 95 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 96 97 #define PHYS_SDRAM_1 \ 98 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 99 100 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 101 102 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 103 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 104 105 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 106 107 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 108 GENERATED_GBL_DATA_SIZE) 109 110 /* 111 * Load address and memory test area should agree with 112 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 113 */ 114 #define CONFIG_SYS_LOAD_ADDR 0x300000 115 116 /* memtest works on 63 MB in DRAM */ 117 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 118 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 119 120 /* 121 * Static memory controller configuration 122 */ 123 #define CONFIG_FTSMC020 124 125 #ifdef CONFIG_FTSMC020 126 #include <faraday/ftsmc020.h> 127 128 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 129 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 130 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 131 } 132 133 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 134 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 135 FTSMC020_BANK_SIZE_32M | \ 136 FTSMC020_BANK_MBW_32) 137 138 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 139 FTSMC020_TPR_AST(1) | \ 140 FTSMC020_TPR_CTW(1) | \ 141 FTSMC020_TPR_ATI(1) | \ 142 FTSMC020_TPR_AT2(1) | \ 143 FTSMC020_TPR_WTC(1) | \ 144 FTSMC020_TPR_AHT(1) | \ 145 FTSMC020_TPR_TRNA(1)) 146 #endif 147 148 /* 149 * FLASH on ADP_AG101P is connected to BANK0 150 * Just disalbe the other BANK to avoid detection error. 151 */ 152 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 153 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 154 FTSMC020_BANK_SIZE_32M | \ 155 FTSMC020_BANK_MBW_32) 156 157 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 158 FTSMC020_TPR_CTW(3) | \ 159 FTSMC020_TPR_ATI(0xf) | \ 160 FTSMC020_TPR_AT2(3) | \ 161 FTSMC020_TPR_WTC(3) | \ 162 FTSMC020_TPR_AHT(3) | \ 163 FTSMC020_TPR_TRNA(0xf)) 164 165 #define FTSMC020_BANK1_CONFIG (0x00) 166 #define FTSMC020_BANK1_TIMING (0x00) 167 #endif /* CONFIG_FTSMC020 */ 168 169 /* 170 * FLASH and environment organization 171 */ 172 /* use CFI framework */ 173 #define CONFIG_SYS_FLASH_CFI 174 #define CONFIG_FLASH_CFI_DRIVER 175 176 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 177 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 178 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 179 180 /* support JEDEC */ 181 #ifdef CONFIG_CFI_FLASH 182 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 183 #endif 184 185 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 186 #define PHYS_FLASH_1 0x88000000 /* BANK 0 */ 187 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 188 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 189 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 190 191 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 192 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 193 194 /* max number of memory banks */ 195 /* 196 * There are 4 banks supported for this Controller, 197 * but we have only 1 bank connected to flash on board 198 */ 199 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 200 #define CONFIG_SYS_MAX_FLASH_BANKS 1 201 #endif 202 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 203 204 /* max number of sectors on one chip */ 205 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 206 #define CONFIG_SYS_MAX_FLASH_SECT 512 207 208 /* environments */ 209 #define CONFIG_ENV_SPI_BUS 0 210 #define CONFIG_ENV_SPI_CS 0 211 #define CONFIG_ENV_SPI_MAX_HZ 50000000 212 #define CONFIG_ENV_SPI_MODE 0 213 #define CONFIG_ENV_SECT_SIZE 0x1000 214 #define CONFIG_ENV_OFFSET 0x140000 215 #define CONFIG_ENV_SIZE 8192 216 #define CONFIG_ENV_OVERWRITE 217 218 219 /* SPI FLASH */ 220 #define CONFIG_SF_DEFAULT_BUS 0 221 #define CONFIG_SF_DEFAULT_CS 0 222 #define CONFIG_SF_DEFAULT_SPEED 1000000 223 #define CONFIG_SF_DEFAULT_MODE 0 224 225 /* 226 * For booting Linux, the board info and command line data 227 * have to be in the first 16 MB of memory, since this is 228 * the maximum mapped by the Linux kernel during initialization. 229 */ 230 231 /* Initial Memory map for Linux*/ 232 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) 233 /* Increase max gunzip size */ 234 #define CONFIG_SYS_BOOTM_LEN (64 << 20) 235 236 #endif /* __CONFIG_H */ 237