1b841b6e9Srick /* 2b841b6e9Srick * Copyright (C) 2011 Andes Technology Corporation 3b841b6e9Srick * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4b841b6e9Srick * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5b841b6e9Srick * 6b841b6e9Srick * SPDX-License-Identifier: GPL-2.0+ 7b841b6e9Srick */ 8b841b6e9Srick 9b841b6e9Srick #ifndef __CONFIG_H 10b841b6e9Srick #define __CONFIG_H 11b841b6e9Srick 12b841b6e9Srick #include <asm/arch-ae3xx/ae3xx.h> 13b841b6e9Srick 14b841b6e9Srick /* 15b841b6e9Srick * CPU and Board Configuration Options 16b841b6e9Srick */ 17b841b6e9Srick #define CONFIG_USE_INTERRUPT 18b841b6e9Srick 19b841b6e9Srick #define CONFIG_SKIP_LOWLEVEL_INIT 20b841b6e9Srick 21b841b6e9Srick #define CONFIG_SKIP_TRUNOFF_WATCHDOG 22b841b6e9Srick 23b841b6e9Srick #define CONFIG_CMDLINE_EDITING 24b841b6e9Srick #define CONFIG_PANIC_HANG 25b841b6e9Srick 26*e336b73dSrick #define CONFIG_ARCH_MAP_SYSMEM 27b841b6e9Srick 28b841b6e9Srick #define CONFIG_BOOTP_SEND_HOSTNAME 29b841b6e9Srick #define CONFIG_BOOTP_SERVERIP 30b841b6e9Srick 31b841b6e9Srick #ifdef CONFIG_SKIP_LOWLEVEL_INIT 32b841b6e9Srick #define CONFIG_SYS_TEXT_BASE 0x00500000 33b841b6e9Srick #ifdef CONFIG_OF_CONTROL 34b841b6e9Srick #undef CONFIG_OF_SEPARATE 35b841b6e9Srick #define CONFIG_OF_EMBED 36b841b6e9Srick #endif 37b841b6e9Srick #else 38b841b6e9Srick 39b841b6e9Srick #define CONFIG_SYS_TEXT_BASE 0x80000000 40b841b6e9Srick #endif 41b841b6e9Srick 42b841b6e9Srick /* 43b841b6e9Srick * Timer 44b841b6e9Srick */ 45b841b6e9Srick #define CONFIG_SYS_CLK_FREQ 39062500 46b841b6e9Srick #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 47b841b6e9Srick 48b841b6e9Srick /* 49b841b6e9Srick * Use Externel CLOCK or PCLK 50b841b6e9Srick */ 51b841b6e9Srick #undef CONFIG_FTRTC010_EXTCLK 52b841b6e9Srick 53b841b6e9Srick #ifndef CONFIG_FTRTC010_EXTCLK 54b841b6e9Srick #define CONFIG_FTRTC010_PCLK 55b841b6e9Srick #endif 56b841b6e9Srick 57b841b6e9Srick #ifdef CONFIG_FTRTC010_EXTCLK 58b841b6e9Srick #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 59b841b6e9Srick #else 60b841b6e9Srick #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 61b841b6e9Srick #endif 62b841b6e9Srick 63b841b6e9Srick #define TIMER_LOAD_VAL 0xffffffff 64b841b6e9Srick 65b841b6e9Srick /* 66b841b6e9Srick * Real Time Clock 67b841b6e9Srick */ 68b841b6e9Srick #define CONFIG_RTC_FTRTC010 69b841b6e9Srick 70b841b6e9Srick /* 71b841b6e9Srick * Real Time Clock Divider 72b841b6e9Srick * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 73b841b6e9Srick */ 74b841b6e9Srick #define OSC_5MHZ (5*1000000) 75b841b6e9Srick #define OSC_CLK (4*OSC_5MHZ) 76b841b6e9Srick #define RTC_DIV_COUNT (0.5) /* Why?? */ 77b841b6e9Srick 78b841b6e9Srick /* 79b841b6e9Srick * Serial console configuration 80b841b6e9Srick */ 81b841b6e9Srick 82b841b6e9Srick /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 83b841b6e9Srick #define CONFIG_CONS_INDEX 1 84b841b6e9Srick #define CONFIG_SYS_NS16550_SERIAL 85b841b6e9Srick #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 86b841b6e9Srick #ifndef CONFIG_DM_SERIAL 87b841b6e9Srick #define CONFIG_SYS_NS16550_REG_SIZE -4 88b841b6e9Srick #endif 89b841b6e9Srick #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 90b841b6e9Srick 91b841b6e9Srick /* 92b841b6e9Srick * SD (MMC) controller 93b841b6e9Srick */ 94b841b6e9Srick #define CONFIG_FTSDC010 95b841b6e9Srick #define CONFIG_FTSDC010_NUMBER 1 96b841b6e9Srick #define CONFIG_FTSDC010_SDIO 97b841b6e9Srick 98b841b6e9Srick /* 99b841b6e9Srick * Miscellaneous configurable options 100b841b6e9Srick */ 101b841b6e9Srick #define CONFIG_SYS_LONGHELP /* undef to save memory */ 102b841b6e9Srick 103b841b6e9Srick /* 104b841b6e9Srick * Size of malloc() pool 105b841b6e9Srick */ 106b841b6e9Srick /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 107b841b6e9Srick #define CONFIG_SYS_MALLOC_LEN (512 << 10) 108b841b6e9Srick 109b841b6e9Srick /* 110b841b6e9Srick * Physical Memory Map 111b841b6e9Srick */ 112b841b6e9Srick #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 113b841b6e9Srick 114b841b6e9Srick #define PHYS_SDRAM_1 \ 115b841b6e9Srick (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 116b841b6e9Srick 117b841b6e9Srick #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 118b841b6e9Srick 119b841b6e9Srick #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 120b841b6e9Srick #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 121b841b6e9Srick 122b841b6e9Srick #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 123b841b6e9Srick 124b841b6e9Srick #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 125b841b6e9Srick GENERATED_GBL_DATA_SIZE) 126b841b6e9Srick 127b841b6e9Srick /* 128b841b6e9Srick * Load address and memory test area should agree with 129b841b6e9Srick * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 130b841b6e9Srick */ 131b841b6e9Srick #define CONFIG_SYS_LOAD_ADDR 0x300000 132b841b6e9Srick 133b841b6e9Srick /* memtest works on 63 MB in DRAM */ 134b841b6e9Srick #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 135b841b6e9Srick #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 136b841b6e9Srick 137b841b6e9Srick /* 138b841b6e9Srick * Static memory controller configuration 139b841b6e9Srick */ 140b841b6e9Srick #define CONFIG_FTSMC020 141b841b6e9Srick 142b841b6e9Srick #ifdef CONFIG_FTSMC020 143b841b6e9Srick #include <faraday/ftsmc020.h> 144b841b6e9Srick 145b841b6e9Srick #define CONFIG_SYS_FTSMC020_CONFIGS { \ 146b841b6e9Srick { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 147b841b6e9Srick { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 148b841b6e9Srick } 149b841b6e9Srick 150b841b6e9Srick #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 151b841b6e9Srick #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 152b841b6e9Srick FTSMC020_BANK_SIZE_32M | \ 153b841b6e9Srick FTSMC020_BANK_MBW_32) 154b841b6e9Srick 155b841b6e9Srick #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 156b841b6e9Srick FTSMC020_TPR_AST(1) | \ 157b841b6e9Srick FTSMC020_TPR_CTW(1) | \ 158b841b6e9Srick FTSMC020_TPR_ATI(1) | \ 159b841b6e9Srick FTSMC020_TPR_AT2(1) | \ 160b841b6e9Srick FTSMC020_TPR_WTC(1) | \ 161b841b6e9Srick FTSMC020_TPR_AHT(1) | \ 162b841b6e9Srick FTSMC020_TPR_TRNA(1)) 163b841b6e9Srick #endif 164b841b6e9Srick 165b841b6e9Srick /* 166b841b6e9Srick * FLASH on ADP_AG101P is connected to BANK0 167b841b6e9Srick * Just disalbe the other BANK to avoid detection error. 168b841b6e9Srick */ 169b841b6e9Srick #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 170b841b6e9Srick FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 171b841b6e9Srick FTSMC020_BANK_SIZE_32M | \ 172b841b6e9Srick FTSMC020_BANK_MBW_32) 173b841b6e9Srick 174b841b6e9Srick #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 175b841b6e9Srick FTSMC020_TPR_CTW(3) | \ 176b841b6e9Srick FTSMC020_TPR_ATI(0xf) | \ 177b841b6e9Srick FTSMC020_TPR_AT2(3) | \ 178b841b6e9Srick FTSMC020_TPR_WTC(3) | \ 179b841b6e9Srick FTSMC020_TPR_AHT(3) | \ 180b841b6e9Srick FTSMC020_TPR_TRNA(0xf)) 181b841b6e9Srick 182b841b6e9Srick #define FTSMC020_BANK1_CONFIG (0x00) 183b841b6e9Srick #define FTSMC020_BANK1_TIMING (0x00) 184b841b6e9Srick #endif /* CONFIG_FTSMC020 */ 185b841b6e9Srick 186b841b6e9Srick /* 187b841b6e9Srick * FLASH and environment organization 188b841b6e9Srick */ 189b841b6e9Srick /* use CFI framework */ 190b841b6e9Srick #define CONFIG_SYS_FLASH_CFI 191b841b6e9Srick #define CONFIG_FLASH_CFI_DRIVER 192b841b6e9Srick 193b841b6e9Srick #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 194b841b6e9Srick #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 195b841b6e9Srick #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 196b841b6e9Srick 197b841b6e9Srick /* support JEDEC */ 198b841b6e9Srick #ifdef CONFIG_CFI_FLASH 199b841b6e9Srick #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 200b841b6e9Srick #endif 201b841b6e9Srick 202b841b6e9Srick /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 203b841b6e9Srick #define PHYS_FLASH_1 0x88000000 /* BANK 0 */ 204b841b6e9Srick #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 205b841b6e9Srick #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 206b841b6e9Srick #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 207b841b6e9Srick 208b841b6e9Srick #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 209b841b6e9Srick #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 210b841b6e9Srick 211b841b6e9Srick /* max number of memory banks */ 212b841b6e9Srick /* 213b841b6e9Srick * There are 4 banks supported for this Controller, 214b841b6e9Srick * but we have only 1 bank connected to flash on board 215b841b6e9Srick */ 216b841b6e9Srick #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 217b841b6e9Srick #define CONFIG_SYS_MAX_FLASH_BANKS 1 218b841b6e9Srick #endif 219b841b6e9Srick #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 220b841b6e9Srick 221b841b6e9Srick /* max number of sectors on one chip */ 222b841b6e9Srick #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 223b841b6e9Srick #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 224b841b6e9Srick #define CONFIG_SYS_MAX_FLASH_SECT 512 225b841b6e9Srick 226b841b6e9Srick /* environments */ 227b841b6e9Srick #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 228b841b6e9Srick #define CONFIG_ENV_SIZE 8192 229b841b6e9Srick #define CONFIG_ENV_OVERWRITE 230b841b6e9Srick 231b841b6e9Srick /* 232b841b6e9Srick * For booting Linux, the board info and command line data 233b841b6e9Srick * have to be in the first 16 MB of memory, since this is 234b841b6e9Srick * the maximum mapped by the Linux kernel during initialization. 235b841b6e9Srick */ 236b841b6e9Srick 237b841b6e9Srick /* Initial Memory map for Linux*/ 238b841b6e9Srick #define CONFIG_SYS_BOOTMAPSZ (64 << 20) 239b841b6e9Srick /* Increase max gunzip size */ 240b841b6e9Srick #define CONFIG_SYS_BOOTM_LEN (64 << 20) 241b841b6e9Srick 242b841b6e9Srick #endif /* __CONFIG_H */ 243