1*b841b6e9Srick /* 2*b841b6e9Srick * Copyright (C) 2011 Andes Technology Corporation 3*b841b6e9Srick * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4*b841b6e9Srick * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5*b841b6e9Srick * 6*b841b6e9Srick * SPDX-License-Identifier: GPL-2.0+ 7*b841b6e9Srick */ 8*b841b6e9Srick 9*b841b6e9Srick #ifndef __CONFIG_H 10*b841b6e9Srick #define __CONFIG_H 11*b841b6e9Srick 12*b841b6e9Srick #include <asm/arch-ae3xx/ae3xx.h> 13*b841b6e9Srick 14*b841b6e9Srick /* 15*b841b6e9Srick * CPU and Board Configuration Options 16*b841b6e9Srick */ 17*b841b6e9Srick #define CONFIG_USE_INTERRUPT 18*b841b6e9Srick 19*b841b6e9Srick #define CONFIG_SKIP_LOWLEVEL_INIT 20*b841b6e9Srick 21*b841b6e9Srick #define CONFIG_SKIP_TRUNOFF_WATCHDOG 22*b841b6e9Srick 23*b841b6e9Srick #define CONFIG_CMDLINE_EDITING 24*b841b6e9Srick #define CONFIG_PANIC_HANG 25*b841b6e9Srick 26*b841b6e9Srick #define CONFIG_SYS_ICACHE_OFF 27*b841b6e9Srick #define CONFIG_SYS_DCACHE_OFF 28*b841b6e9Srick 29*b841b6e9Srick #define CONFIG_BOOTP_SEND_HOSTNAME 30*b841b6e9Srick #define CONFIG_BOOTP_SERVERIP 31*b841b6e9Srick 32*b841b6e9Srick #ifdef CONFIG_SKIP_LOWLEVEL_INIT 33*b841b6e9Srick #define CONFIG_SYS_TEXT_BASE 0x00500000 34*b841b6e9Srick #ifdef CONFIG_OF_CONTROL 35*b841b6e9Srick #undef CONFIG_OF_SEPARATE 36*b841b6e9Srick #define CONFIG_OF_EMBED 37*b841b6e9Srick #endif 38*b841b6e9Srick #else 39*b841b6e9Srick 40*b841b6e9Srick #define CONFIG_SYS_TEXT_BASE 0x80000000 41*b841b6e9Srick #endif 42*b841b6e9Srick 43*b841b6e9Srick /* 44*b841b6e9Srick * Timer 45*b841b6e9Srick */ 46*b841b6e9Srick #define CONFIG_SYS_CLK_FREQ 39062500 47*b841b6e9Srick #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 48*b841b6e9Srick 49*b841b6e9Srick /* 50*b841b6e9Srick * Use Externel CLOCK or PCLK 51*b841b6e9Srick */ 52*b841b6e9Srick #undef CONFIG_FTRTC010_EXTCLK 53*b841b6e9Srick 54*b841b6e9Srick #ifndef CONFIG_FTRTC010_EXTCLK 55*b841b6e9Srick #define CONFIG_FTRTC010_PCLK 56*b841b6e9Srick #endif 57*b841b6e9Srick 58*b841b6e9Srick #ifdef CONFIG_FTRTC010_EXTCLK 59*b841b6e9Srick #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 60*b841b6e9Srick #else 61*b841b6e9Srick #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 62*b841b6e9Srick #endif 63*b841b6e9Srick 64*b841b6e9Srick #define TIMER_LOAD_VAL 0xffffffff 65*b841b6e9Srick 66*b841b6e9Srick /* 67*b841b6e9Srick * Real Time Clock 68*b841b6e9Srick */ 69*b841b6e9Srick #define CONFIG_RTC_FTRTC010 70*b841b6e9Srick 71*b841b6e9Srick /* 72*b841b6e9Srick * Real Time Clock Divider 73*b841b6e9Srick * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 74*b841b6e9Srick */ 75*b841b6e9Srick #define OSC_5MHZ (5*1000000) 76*b841b6e9Srick #define OSC_CLK (4*OSC_5MHZ) 77*b841b6e9Srick #define RTC_DIV_COUNT (0.5) /* Why?? */ 78*b841b6e9Srick 79*b841b6e9Srick /* 80*b841b6e9Srick * Serial console configuration 81*b841b6e9Srick */ 82*b841b6e9Srick 83*b841b6e9Srick /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 84*b841b6e9Srick #define CONFIG_CONS_INDEX 1 85*b841b6e9Srick #define CONFIG_SYS_NS16550_SERIAL 86*b841b6e9Srick #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 87*b841b6e9Srick #ifndef CONFIG_DM_SERIAL 88*b841b6e9Srick #define CONFIG_SYS_NS16550_REG_SIZE -4 89*b841b6e9Srick #endif 90*b841b6e9Srick #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 91*b841b6e9Srick 92*b841b6e9Srick /* 93*b841b6e9Srick * Ethernet 94*b841b6e9Srick */ 95*b841b6e9Srick #define CONFIG_FTMAC100 96*b841b6e9Srick 97*b841b6e9Srick /* 98*b841b6e9Srick * SD (MMC) controller 99*b841b6e9Srick */ 100*b841b6e9Srick #define CONFIG_FTSDC010 101*b841b6e9Srick #define CONFIG_FTSDC010_NUMBER 1 102*b841b6e9Srick #define CONFIG_FTSDC010_SDIO 103*b841b6e9Srick 104*b841b6e9Srick /* 105*b841b6e9Srick * Miscellaneous configurable options 106*b841b6e9Srick */ 107*b841b6e9Srick #define CONFIG_SYS_LONGHELP /* undef to save memory */ 108*b841b6e9Srick #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 109*b841b6e9Srick 110*b841b6e9Srick /* Print Buffer Size */ 111*b841b6e9Srick #define CONFIG_SYS_PBSIZE \ 112*b841b6e9Srick (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 113*b841b6e9Srick 114*b841b6e9Srick /* max number of command args */ 115*b841b6e9Srick #define CONFIG_SYS_MAXARGS 16 116*b841b6e9Srick 117*b841b6e9Srick /* Boot Argument Buffer Size */ 118*b841b6e9Srick #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 119*b841b6e9Srick 120*b841b6e9Srick /* 121*b841b6e9Srick * Size of malloc() pool 122*b841b6e9Srick */ 123*b841b6e9Srick /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 124*b841b6e9Srick #define CONFIG_SYS_MALLOC_LEN (512 << 10) 125*b841b6e9Srick 126*b841b6e9Srick /* 127*b841b6e9Srick * Physical Memory Map 128*b841b6e9Srick */ 129*b841b6e9Srick #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 130*b841b6e9Srick 131*b841b6e9Srick #define PHYS_SDRAM_1 \ 132*b841b6e9Srick (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 133*b841b6e9Srick 134*b841b6e9Srick #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 135*b841b6e9Srick 136*b841b6e9Srick #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 137*b841b6e9Srick #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 138*b841b6e9Srick 139*b841b6e9Srick #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 140*b841b6e9Srick 141*b841b6e9Srick #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 142*b841b6e9Srick GENERATED_GBL_DATA_SIZE) 143*b841b6e9Srick 144*b841b6e9Srick /* 145*b841b6e9Srick * Load address and memory test area should agree with 146*b841b6e9Srick * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 147*b841b6e9Srick */ 148*b841b6e9Srick #define CONFIG_SYS_LOAD_ADDR 0x300000 149*b841b6e9Srick 150*b841b6e9Srick /* memtest works on 63 MB in DRAM */ 151*b841b6e9Srick #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 152*b841b6e9Srick #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 153*b841b6e9Srick 154*b841b6e9Srick /* 155*b841b6e9Srick * Static memory controller configuration 156*b841b6e9Srick */ 157*b841b6e9Srick #define CONFIG_FTSMC020 158*b841b6e9Srick 159*b841b6e9Srick #ifdef CONFIG_FTSMC020 160*b841b6e9Srick #include <faraday/ftsmc020.h> 161*b841b6e9Srick 162*b841b6e9Srick #define CONFIG_SYS_FTSMC020_CONFIGS { \ 163*b841b6e9Srick { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 164*b841b6e9Srick { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 165*b841b6e9Srick } 166*b841b6e9Srick 167*b841b6e9Srick #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 168*b841b6e9Srick #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 169*b841b6e9Srick FTSMC020_BANK_SIZE_32M | \ 170*b841b6e9Srick FTSMC020_BANK_MBW_32) 171*b841b6e9Srick 172*b841b6e9Srick #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 173*b841b6e9Srick FTSMC020_TPR_AST(1) | \ 174*b841b6e9Srick FTSMC020_TPR_CTW(1) | \ 175*b841b6e9Srick FTSMC020_TPR_ATI(1) | \ 176*b841b6e9Srick FTSMC020_TPR_AT2(1) | \ 177*b841b6e9Srick FTSMC020_TPR_WTC(1) | \ 178*b841b6e9Srick FTSMC020_TPR_AHT(1) | \ 179*b841b6e9Srick FTSMC020_TPR_TRNA(1)) 180*b841b6e9Srick #endif 181*b841b6e9Srick 182*b841b6e9Srick /* 183*b841b6e9Srick * FLASH on ADP_AG101P is connected to BANK0 184*b841b6e9Srick * Just disalbe the other BANK to avoid detection error. 185*b841b6e9Srick */ 186*b841b6e9Srick #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 187*b841b6e9Srick FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 188*b841b6e9Srick FTSMC020_BANK_SIZE_32M | \ 189*b841b6e9Srick FTSMC020_BANK_MBW_32) 190*b841b6e9Srick 191*b841b6e9Srick #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 192*b841b6e9Srick FTSMC020_TPR_CTW(3) | \ 193*b841b6e9Srick FTSMC020_TPR_ATI(0xf) | \ 194*b841b6e9Srick FTSMC020_TPR_AT2(3) | \ 195*b841b6e9Srick FTSMC020_TPR_WTC(3) | \ 196*b841b6e9Srick FTSMC020_TPR_AHT(3) | \ 197*b841b6e9Srick FTSMC020_TPR_TRNA(0xf)) 198*b841b6e9Srick 199*b841b6e9Srick #define FTSMC020_BANK1_CONFIG (0x00) 200*b841b6e9Srick #define FTSMC020_BANK1_TIMING (0x00) 201*b841b6e9Srick #endif /* CONFIG_FTSMC020 */ 202*b841b6e9Srick 203*b841b6e9Srick /* 204*b841b6e9Srick * FLASH and environment organization 205*b841b6e9Srick */ 206*b841b6e9Srick /* use CFI framework */ 207*b841b6e9Srick #define CONFIG_SYS_FLASH_CFI 208*b841b6e9Srick #define CONFIG_FLASH_CFI_DRIVER 209*b841b6e9Srick 210*b841b6e9Srick #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 211*b841b6e9Srick #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 212*b841b6e9Srick #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 213*b841b6e9Srick 214*b841b6e9Srick /* support JEDEC */ 215*b841b6e9Srick #ifdef CONFIG_CFI_FLASH 216*b841b6e9Srick #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 217*b841b6e9Srick #endif 218*b841b6e9Srick 219*b841b6e9Srick /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 220*b841b6e9Srick #define PHYS_FLASH_1 0x88000000 /* BANK 0 */ 221*b841b6e9Srick #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 222*b841b6e9Srick #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 223*b841b6e9Srick #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 224*b841b6e9Srick 225*b841b6e9Srick #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 226*b841b6e9Srick #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 227*b841b6e9Srick 228*b841b6e9Srick /* max number of memory banks */ 229*b841b6e9Srick /* 230*b841b6e9Srick * There are 4 banks supported for this Controller, 231*b841b6e9Srick * but we have only 1 bank connected to flash on board 232*b841b6e9Srick */ 233*b841b6e9Srick #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 234*b841b6e9Srick #define CONFIG_SYS_MAX_FLASH_BANKS 1 235*b841b6e9Srick #endif 236*b841b6e9Srick #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 237*b841b6e9Srick 238*b841b6e9Srick /* max number of sectors on one chip */ 239*b841b6e9Srick #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 240*b841b6e9Srick #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 241*b841b6e9Srick #define CONFIG_SYS_MAX_FLASH_SECT 512 242*b841b6e9Srick 243*b841b6e9Srick /* environments */ 244*b841b6e9Srick #define CONFIG_ENV_IS_IN_FLASH 245*b841b6e9Srick #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 246*b841b6e9Srick #define CONFIG_ENV_SIZE 8192 247*b841b6e9Srick #define CONFIG_ENV_OVERWRITE 248*b841b6e9Srick 249*b841b6e9Srick /* 250*b841b6e9Srick * For booting Linux, the board info and command line data 251*b841b6e9Srick * have to be in the first 16 MB of memory, since this is 252*b841b6e9Srick * the maximum mapped by the Linux kernel during initialization. 253*b841b6e9Srick */ 254*b841b6e9Srick 255*b841b6e9Srick /* Initial Memory map for Linux*/ 256*b841b6e9Srick #define CONFIG_SYS_BOOTMAPSZ (64 << 20) 257*b841b6e9Srick /* Increase max gunzip size */ 258*b841b6e9Srick #define CONFIG_SYS_BOOTM_LEN (64 << 20) 259*b841b6e9Srick 260*b841b6e9Srick #endif /* __CONFIG_H */ 261