1 /* 2 * Copyright 2013-2015 Arcturus Networks, Inc. 3 * http://www.arcturusnetworks.com/products/ucp1020/ 4 * based on include/configs/p1_p2_rdb_pc.h 5 * original copyright follows: 6 * Copyright 2009-2011 Freescale Semiconductor, Inc. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * QorIQ uCP1020-xx boards configuration file 13 */ 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 18 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 19 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 20 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 21 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 22 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 23 24 #if defined(CONFIG_TARTGET_UCP1020T1) 25 26 #define CONFIG_UCP1020_REV_1_3 27 28 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" 29 30 #define CONFIG_TSEC_ENET 31 #define CONFIG_TSEC1 32 #define CONFIG_TSEC3 33 #define CONFIG_HAS_ETH0 34 #define CONFIG_HAS_ETH1 35 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF 36 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE 37 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD 38 #define CONFIG_IPADDR 10.80.41.229 39 #define CONFIG_SERVERIP 10.80.41.227 40 #define CONFIG_NETMASK 255.255.252.0 41 #define CONFIG_ETHPRIME "eTSEC3" 42 43 #ifndef CONFIG_SPI_FLASH 44 #endif 45 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 46 47 #define CONFIG_SYS_L2_SIZE (256 << 10) 48 49 #define CONFIG_LAST_STAGE_INIT 50 51 #endif 52 53 #if defined(CONFIG_TARGET_UCP1020) 54 55 #define CONFIG_UCP1020 56 #define CONFIG_UCP1020_REV_1_3 57 58 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" 59 60 #define CONFIG_TSEC_ENET 61 #define CONFIG_TSEC1 62 #define CONFIG_TSEC2 63 #define CONFIG_TSEC3 64 #define CONFIG_HAS_ETH0 65 #define CONFIG_HAS_ETH1 66 #define CONFIG_HAS_ETH2 67 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF 68 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE 69 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD 70 #define CONFIG_IPADDR 192.168.1.81 71 #define CONFIG_IPADDR1 192.168.1.82 72 #define CONFIG_IPADDR2 192.168.1.83 73 #define CONFIG_SERVERIP 192.168.1.80 74 #define CONFIG_GATEWAYIP 102.168.1.1 75 #define CONFIG_NETMASK 255.255.255.0 76 #define CONFIG_ETHPRIME "eTSEC1" 77 78 #ifndef CONFIG_SPI_FLASH 79 #endif 80 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 81 82 #define CONFIG_SYS_L2_SIZE (256 << 10) 83 84 #define CONFIG_LAST_STAGE_INIT 85 86 #endif 87 88 #ifdef CONFIG_SDCARD 89 #define CONFIG_RAMBOOT_SDCARD 90 #define CONFIG_SYS_RAMBOOT 91 #define CONFIG_SYS_EXTRA_ENV_RELOC 92 #define CONFIG_SYS_TEXT_BASE 0x11000000 93 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 94 #endif 95 96 #ifdef CONFIG_SPIFLASH 97 #define CONFIG_RAMBOOT_SPIFLASH 98 #define CONFIG_SYS_RAMBOOT 99 #define CONFIG_SYS_EXTRA_ENV_RELOC 100 #define CONFIG_SYS_TEXT_BASE 0x11000000 101 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 102 #endif 103 104 #ifndef CONFIG_SYS_TEXT_BASE 105 #define CONFIG_SYS_TEXT_BASE 0xeff80000 106 #endif 107 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000 108 109 #ifndef CONFIG_RESET_VECTOR_ADDRESS 110 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 111 #endif 112 113 #ifndef CONFIG_SYS_MONITOR_BASE 114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 115 #endif 116 117 #define CONFIG_MP 118 119 #define CONFIG_ENV_OVERWRITE 120 121 #define CONFIG_CMD_SATA 122 #define CONFIG_SATA_SIL 123 #define CONFIG_SYS_SATA_MAX_DEVICE 2 124 #define CONFIG_LIBATA 125 #define CONFIG_LBA48 126 127 #define CONFIG_SYS_CLK_FREQ 66666666 128 #define CONFIG_DDR_CLK_FREQ 66666666 129 130 #define CONFIG_HWCONFIG 131 132 /* 133 * These can be toggled for performance analysis, otherwise use default. 134 */ 135 #define CONFIG_L2_CACHE 136 #define CONFIG_BTB 137 138 #define CONFIG_ENABLE_36BIT_PHYS 139 140 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 141 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 142 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 143 144 #define CONFIG_SYS_CCSRBAR 0xffe00000 145 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 146 147 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 148 SPL code*/ 149 #ifdef CONFIG_SPL_BUILD 150 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 151 #endif 152 153 /* DDR Setup */ 154 #define CONFIG_DDR_ECC_ENABLE 155 #ifndef CONFIG_DDR_ECC_ENABLE 156 #define CONFIG_SYS_DDR_RAW_TIMING 157 #define CONFIG_DDR_SPD 158 #endif 159 #define CONFIG_SYS_SPD_BUS_NUM 1 160 #undef CONFIG_FSL_DDR_INTERACTIVE 161 162 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 163 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 164 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 165 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 166 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 167 168 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 169 170 /* Default settings for DDR3 */ 171 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 172 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 173 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 174 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 175 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 176 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 177 178 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 179 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 180 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 181 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 182 183 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 184 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 185 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 186 #define CONFIG_SYS_DDR_RCW_1 0x00000000 187 #define CONFIG_SYS_DDR_RCW_2 0x00000000 188 #ifdef CONFIG_DDR_ECC_ENABLE 189 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */ 190 #else 191 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 192 #endif 193 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 194 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 195 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 196 197 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 198 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 199 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 200 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 201 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 202 #define CONFIG_SYS_DDR_MODE_1 0x40461520 203 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 204 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 205 206 #undef CONFIG_CLOCKS_IN_MHZ 207 208 /* 209 * Memory map 210 * 211 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 212 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2) 213 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 214 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable 215 * (early boot only) 216 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 217 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 218 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 219 */ 220 221 /* 222 * Local Bus Definitions 223 */ 224 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 225 #define CONFIG_SYS_FLASH_BASE 0xec000000 226 227 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 228 229 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 230 | BR_PS_16 | BR_V) 231 232 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 233 234 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 235 #define CONFIG_SYS_FLASH_QUIET_TEST 236 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 237 238 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 239 240 #undef CONFIG_SYS_FLASH_CHECKSUM 241 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 242 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 243 244 #define CONFIG_FLASH_CFI_DRIVER 245 #define CONFIG_SYS_FLASH_CFI 246 #define CONFIG_SYS_FLASH_EMPTY_INFO 247 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 248 249 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 250 251 #define CONFIG_SYS_INIT_RAM_LOCK 252 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 253 /* Initial L1 address */ 254 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 255 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 256 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 257 /* Size of used area in RAM */ 258 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 259 260 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 261 GENERATED_GBL_DATA_SIZE) 262 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 263 264 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ 265 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 266 267 #define CONFIG_SYS_PMC_BASE 0xff980000 268 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 269 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 270 BR_PS_8 | BR_V) 271 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 272 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 273 OR_GPCM_EAD) 274 275 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 276 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 277 #ifdef CONFIG_NAND_FSL_ELBC 278 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 279 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 280 #endif 281 282 /* Serial Port - controlled on board with jumper J8 283 * open - index 2 284 * shorted - index 1 285 */ 286 #define CONFIG_CONS_INDEX 1 287 #undef CONFIG_SERIAL_SOFTWARE_FIFO 288 #define CONFIG_SYS_NS16550_SERIAL 289 #define CONFIG_SYS_NS16550_REG_SIZE 1 290 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 291 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 292 #define CONFIG_NS16550_MIN_FUNCTIONS 293 #endif 294 295 #define CONFIG_SYS_BAUDRATE_TABLE \ 296 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 297 298 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 299 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 300 301 /* I2C */ 302 #define CONFIG_SYS_I2C 303 #define CONFIG_SYS_I2C_FSL 304 #define CONFIG_SYS_FSL_I2C_SPEED 400000 305 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 306 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 307 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 308 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 309 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 310 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 311 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 312 313 #define CONFIG_RTC_DS1337 314 #define CONFIG_SYS_RTC_DS1337_NOOSC 315 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 316 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 317 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C 318 #define CONFIG_SYS_I2C_IDT6V49205B 0x69 319 320 /* 321 * eSPI - Enhanced SPI 322 */ 323 #define CONFIG_HARD_SPI 324 325 #define CONFIG_SF_DEFAULT_SPEED 10000000 326 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 327 328 #if defined(CONFIG_PCI) 329 /* 330 * General PCI 331 * Memory space is mapped 1-1, but I/O space must start from 0. 332 */ 333 334 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 335 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9" 336 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 337 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 338 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 339 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 340 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 341 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 342 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 343 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 344 345 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 346 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10" 347 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 348 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 349 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 350 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 351 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 352 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 353 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 354 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 355 356 #define CONFIG_CMD_PCI 357 358 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 359 #endif /* CONFIG_PCI */ 360 361 /* 362 * Environment 363 */ 364 #ifdef CONFIG_ENV_FIT_UCBOOT 365 366 #define CONFIG_ENV_IS_IN_FLASH 367 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000) 368 #define CONFIG_ENV_SIZE 0x20000 369 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 370 371 #else 372 373 #define CONFIG_ENV_SPI_BUS 0 374 #define CONFIG_ENV_SPI_CS 0 375 #define CONFIG_ENV_SPI_MAX_HZ 10000000 376 #define CONFIG_ENV_SPI_MODE 0 377 378 #ifdef CONFIG_RAMBOOT_SPIFLASH 379 380 #define CONFIG_ENV_IS_IN_SPI_FLASH 381 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */ 382 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */ 383 #define CONFIG_ENV_SECT_SIZE 0x1000 384 385 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 386 /* Address and size of Redundant Environment Sector */ 387 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 388 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 389 #endif 390 391 #elif defined(CONFIG_RAMBOOT_SDCARD) 392 #define CONFIG_ENV_IS_IN_MMC 393 #define CONFIG_FSL_FIXED_MMC_LOCATION 394 #define CONFIG_ENV_SIZE 0x2000 395 #define CONFIG_SYS_MMC_ENV_DEV 0 396 397 #elif defined(CONFIG_SYS_RAMBOOT) 398 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 399 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 400 #define CONFIG_ENV_SIZE 0x2000 401 402 #else 403 #define CONFIG_ENV_IS_IN_FLASH 404 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE) 405 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 406 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 407 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000) 408 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 409 /* Address and size of Redundant Environment Sector */ 410 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 411 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 412 #endif 413 414 #endif 415 416 #endif /* CONFIG_ENV_FIT_UCBOOT */ 417 418 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 419 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 420 421 /* 422 * Command line configuration. 423 */ 424 #define CONFIG_CMD_IRQ 425 #define CONFIG_CMD_IRQ 426 #define CONFIG_CMD_REGINFO 427 428 /* 429 * USB 430 */ 431 #define CONFIG_HAS_FSL_DR_USB 432 433 #if defined(CONFIG_HAS_FSL_DR_USB) 434 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 435 436 #ifdef CONFIG_USB_EHCI_HCD 437 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 438 #define CONFIG_USB_EHCI_FSL 439 #endif 440 #endif 441 442 #undef CONFIG_WATCHDOG /* watchdog disabled */ 443 444 #ifdef CONFIG_MMC 445 #define CONFIG_FSL_ESDHC 446 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 447 #define CONFIG_MMC_SPI 448 #define CONFIG_CMD_MMC_SPI 449 #endif 450 451 /* Misc Extra Settings */ 452 #undef CONFIG_WATCHDOG /* watchdog disabled */ 453 454 /* 455 * Miscellaneous configurable options 456 */ 457 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 458 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 459 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 460 #if defined(CONFIG_CMD_KGDB) 461 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 462 #else 463 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 464 #endif 465 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 466 /* Print Buffer Size */ 467 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 468 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 469 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ 470 471 /* 472 * For booting Linux, the board info and command line data 473 * have to be in the first 64 MB of memory, since this is 474 * the maximum mapped by the Linux kernel during initialization. 475 */ 476 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 477 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 478 479 #if defined(CONFIG_CMD_KGDB) 480 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 481 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 482 #endif 483 484 /* 485 * Environment Configuration 486 */ 487 488 #if defined(CONFIG_TSEC_ENET) 489 490 #if defined(CONFIG_UCP1020_REV_1_2) 491 #define CONFIG_PHY_MICREL_KSZ9021 492 #elif defined(CONFIG_UCP1020_REV_1_3) 493 #define CONFIG_PHY_MICREL_KSZ9031 494 #else 495 #error "UCP1020 module revision is not defined !!!" 496 #endif 497 498 #define CONFIG_BOOTP_SERVERIP 499 500 #define CONFIG_MII /* MII PHY management */ 501 #define CONFIG_TSEC1_NAME "eTSEC1" 502 #define CONFIG_TSEC2_NAME "eTSEC2" 503 #define CONFIG_TSEC3_NAME "eTSEC3" 504 505 #define TSEC1_PHY_ADDR 4 506 #define TSEC2_PHY_ADDR 0 507 #define TSEC2_PHY_ADDR_SGMII 0x00 508 #define TSEC3_PHY_ADDR 6 509 510 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 511 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 512 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 513 514 #define TSEC1_PHYIDX 0 515 #define TSEC2_PHYIDX 0 516 #define TSEC3_PHYIDX 0 517 518 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 519 520 #endif 521 522 #define CONFIG_HOSTNAME UCP1020 523 #define CONFIG_ROOTPATH "/opt/nfsroot" 524 #define CONFIG_BOOTFILE "uImage" 525 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 526 527 /* default location for tftp and bootm */ 528 #define CONFIG_LOADADDR 1000000 529 530 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 531 532 #if defined(CONFIG_DONGLE) 533 534 #define CONFIG_EXTRA_ENV_SETTINGS \ 535 "bootcmd=run prog_spi_mbrbootcramfs\0" \ 536 "bootfile=uImage\0" \ 537 "consoledev=ttyS0\0" \ 538 "cramfsfile=image.cramfs\0" \ 539 "dtbaddr=0x00c00000\0" \ 540 "dtbfile=image.dtb\0" \ 541 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 542 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 543 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 544 "fileaddr=0x01000000\0" \ 545 "filesize=0x00080000\0" \ 546 "flashmbr=sf probe 0; " \ 547 "tftp $loadaddr $mbr; " \ 548 "sf erase $mbr_offset +$filesize; " \ 549 "sf write $loadaddr $mbr_offset $filesize\0" \ 550 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 551 "protect off $nor_recoveryaddr +$filesize; " \ 552 "erase $nor_recoveryaddr +$filesize; " \ 553 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 554 "protect on $nor_recoveryaddr +$filesize\0 " \ 555 "flashuboot=tftp $ubootaddr $ubootfile; " \ 556 "protect off $nor_ubootaddr +$filesize; " \ 557 "erase $nor_ubootaddr +$filesize; " \ 558 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 559 "protect on $nor_ubootaddr +$filesize\0 " \ 560 "flashworking=tftp $workingaddr $cramfsfile; " \ 561 "protect off $nor_workingaddr +$filesize; " \ 562 "erase $nor_workingaddr +$filesize; " \ 563 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 564 "protect on $nor_workingaddr +$filesize\0 " \ 565 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 566 "kerneladdr=0x01100000\0" \ 567 "kernelfile=uImage\0" \ 568 "loadaddr=0x01000000\0" \ 569 "mbr=uCP1020d.mbr\0" \ 570 "mbr_offset=0x00000000\0" \ 571 "mmbr=uCP1020Quiet.mbr\0" \ 572 "mmcpart=0:2\0" \ 573 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 574 "mmc erase 1 1; " \ 575 "mmc write $loadaddr 1 1\0" \ 576 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \ 577 "mmc erase 0x40 0x400; " \ 578 "mmc write $loadaddr 0x40 0x400\0" \ 579 "netdev=eth0\0" \ 580 "nor_recoveryaddr=0xEC0A0000\0" \ 581 "nor_ubootaddr=0xEFF80000\0" \ 582 "nor_workingaddr=0xECFA0000\0" \ 583 "norbootrecovery=setenv bootargs $recoverybootargs" \ 584 " console=$consoledev,$baudrate $othbootargs; " \ 585 "run norloadrecovery; " \ 586 "bootm $kerneladdr - $dtbaddr\0" \ 587 "norbootworking=setenv bootargs $workingbootargs" \ 588 " console=$consoledev,$baudrate $othbootargs; " \ 589 "run norloadworking; " \ 590 "bootm $kerneladdr - $dtbaddr\0" \ 591 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 592 "setenv cramfsaddr $nor_recoveryaddr; " \ 593 "cramfsload $dtbaddr $dtbfile; " \ 594 "cramfsload $kerneladdr $kernelfile\0" \ 595 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 596 "setenv cramfsaddr $nor_workingaddr; " \ 597 "cramfsload $dtbaddr $dtbfile; " \ 598 "cramfsload $kerneladdr $kernelfile\0" \ 599 "prog_spi_mbr=run spi__mbr\0" \ 600 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \ 601 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \ 602 "run spi__cramfs\0" \ 603 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 604 " console=$consoledev,$baudrate $othbootargs; " \ 605 "tftp $rootfsaddr $rootfsfile; " \ 606 "tftp $loadaddr $kernelfile; " \ 607 "tftp $dtbaddr $dtbfile; " \ 608 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 609 "ramdisk_size=120000\0" \ 610 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 611 "recoveryaddr=0x02F00000\0" \ 612 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 613 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 614 "mw.l 0xffe0f008 0x00400000\0" \ 615 "rootfsaddr=0x02F00000\0" \ 616 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 617 "rootpath=/opt/nfsroot\0" \ 618 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 619 "protect off 0xeC000000 +$filesize; " \ 620 "erase 0xEC000000 +$filesize; " \ 621 "cp.b $loadaddr 0xEC000000 $filesize; " \ 622 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 623 "protect on 0xeC000000 +$filesize\0" \ 624 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 625 "protect off 0xeFF80000 +$filesize; " \ 626 "erase 0xEFF80000 +$filesize; " \ 627 "cp.b $loadaddr 0xEFF80000 $filesize; " \ 628 "cmp.b $loadaddr 0xEFF80000 $filesize; " \ 629 "protect on 0xeFF80000 +$filesize\0" \ 630 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \ 631 "sf probe 0; sf erase 0x8000 +$filesize; " \ 632 "sf write $loadaddr 0x8000 $filesize\0" \ 633 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \ 634 "protect off 0xec0a0000 +$filesize; " \ 635 "erase 0xeC0A0000 +$filesize; " \ 636 "cp.b $loadaddr 0xeC0A0000 $filesize; " \ 637 "protect on 0xec0a0000 +$filesize\0" \ 638 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 639 "sf probe 1; sf erase 0 +$filesize; " \ 640 "sf write $loadaddr 0 $filesize\0" \ 641 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 642 "sf probe 0; sf erase 0 +$filesize; " \ 643 "sf write $loadaddr 0 $filesize\0" \ 644 "tftpflash=tftpboot $loadaddr $uboot; " \ 645 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 646 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 647 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 648 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 649 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 650 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 651 "ubootaddr=0x01000000\0" \ 652 "ubootfile=u-boot.bin\0" \ 653 "ubootd=u-boot4dongle.bin\0" \ 654 "upgrade=run flashworking\0" \ 655 "usb_phy_type=ulpi\0 " \ 656 "workingaddr=0x02F00000\0" \ 657 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 658 659 #else 660 661 #if defined(CONFIG_UCP1020T1) 662 663 #define CONFIG_EXTRA_ENV_SETTINGS \ 664 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ 665 "bootfile=uImage\0" \ 666 "consoledev=ttyS0\0" \ 667 "cramfsfile=image.cramfs\0" \ 668 "dtbaddr=0x00c00000\0" \ 669 "dtbfile=image.dtb\0" \ 670 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 671 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 672 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 673 "fileaddr=0x01000000\0" \ 674 "filesize=0x00080000\0" \ 675 "flashmbr=sf probe 0; " \ 676 "tftp $loadaddr $mbr; " \ 677 "sf erase $mbr_offset +$filesize; " \ 678 "sf write $loadaddr $mbr_offset $filesize\0" \ 679 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 680 "protect off $nor_recoveryaddr +$filesize; " \ 681 "erase $nor_recoveryaddr +$filesize; " \ 682 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 683 "protect on $nor_recoveryaddr +$filesize\0 " \ 684 "flashuboot=tftp $ubootaddr $ubootfile; " \ 685 "protect off $nor_ubootaddr +$filesize; " \ 686 "erase $nor_ubootaddr +$filesize; " \ 687 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 688 "protect on $nor_ubootaddr +$filesize\0 " \ 689 "flashworking=tftp $workingaddr $cramfsfile; " \ 690 "protect off $nor_workingaddr +$filesize; " \ 691 "erase $nor_workingaddr +$filesize; " \ 692 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 693 "protect on $nor_workingaddr +$filesize\0 " \ 694 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 695 "kerneladdr=0x01100000\0" \ 696 "kernelfile=uImage\0" \ 697 "loadaddr=0x01000000\0" \ 698 "mbr=uCP1020.mbr\0" \ 699 "mbr_offset=0x00000000\0" \ 700 "netdev=eth0\0" \ 701 "nor_recoveryaddr=0xEC0A0000\0" \ 702 "nor_ubootaddr=0xEFF80000\0" \ 703 "nor_workingaddr=0xECFA0000\0" \ 704 "norbootrecovery=setenv bootargs $recoverybootargs" \ 705 " console=$consoledev,$baudrate $othbootargs; " \ 706 "run norloadrecovery; " \ 707 "bootm $kerneladdr - $dtbaddr\0" \ 708 "norbootworking=setenv bootargs $workingbootargs" \ 709 " console=$consoledev,$baudrate $othbootargs; " \ 710 "run norloadworking; " \ 711 "bootm $kerneladdr - $dtbaddr\0" \ 712 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 713 "setenv cramfsaddr $nor_recoveryaddr; " \ 714 "cramfsload $dtbaddr $dtbfile; " \ 715 "cramfsload $kerneladdr $kernelfile\0" \ 716 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 717 "setenv cramfsaddr $nor_workingaddr; " \ 718 "cramfsload $dtbaddr $dtbfile; " \ 719 "cramfsload $kerneladdr $kernelfile\0" \ 720 "othbootargs=quiet\0" \ 721 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 722 " console=$consoledev,$baudrate $othbootargs; " \ 723 "tftp $rootfsaddr $rootfsfile; " \ 724 "tftp $loadaddr $kernelfile; " \ 725 "tftp $dtbaddr $dtbfile; " \ 726 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 727 "ramdisk_size=120000\0" \ 728 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 729 "recoveryaddr=0x02F00000\0" \ 730 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 731 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 732 "mw.l 0xffe0f008 0x00400000\0" \ 733 "rootfsaddr=0x02F00000\0" \ 734 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 735 "rootpath=/opt/nfsroot\0" \ 736 "silent=1\0" \ 737 "tftpflash=tftpboot $loadaddr $uboot; " \ 738 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 739 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 740 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 741 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 742 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 743 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 744 "ubootaddr=0x01000000\0" \ 745 "ubootfile=u-boot.bin\0" \ 746 "upgrade=run flashworking\0" \ 747 "workingaddr=0x02F00000\0" \ 748 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 749 750 #else /* For Arcturus Modules */ 751 752 #define CONFIG_EXTRA_ENV_SETTINGS \ 753 "bootcmd=run norkernel\0" \ 754 "bootfile=uImage\0" \ 755 "consoledev=ttyS0\0" \ 756 "dtbaddr=0x00c00000\0" \ 757 "dtbfile=image.dtb\0" \ 758 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 759 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 760 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 761 "fileaddr=0x01000000\0" \ 762 "filesize=0x00080000\0" \ 763 "flashmbr=sf probe 0; " \ 764 "tftp $loadaddr $mbr; " \ 765 "sf erase $mbr_offset +$filesize; " \ 766 "sf write $loadaddr $mbr_offset $filesize\0" \ 767 "flashuboot=tftp $loadaddr $ubootfile; " \ 768 "protect off $nor_ubootaddr0 +$filesize; " \ 769 "erase $nor_ubootaddr0 +$filesize; " \ 770 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \ 771 "protect on $nor_ubootaddr0 +$filesize; " \ 772 "protect off $nor_ubootaddr1 +$filesize; " \ 773 "erase $nor_ubootaddr1 +$filesize; " \ 774 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \ 775 "protect on $nor_ubootaddr1 +$filesize\0 " \ 776 "format0=protect off $part0base +$part0size; " \ 777 "erase $part0base +$part0size\0" \ 778 "format1=protect off $part1base +$part1size; " \ 779 "erase $part1base +$part1size\0" \ 780 "format2=protect off $part2base +$part2size; " \ 781 "erase $part2base +$part2size\0" \ 782 "format3=protect off $part3base +$part3size; " \ 783 "erase $part3base +$part3size\0" \ 784 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 785 "kerneladdr=0x01100000\0" \ 786 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \ 787 "kernelfile=uImage\0" \ 788 "loadaddr=0x01000000\0" \ 789 "mbr=uCP1020.mbr\0" \ 790 "mbr_offset=0x00000000\0" \ 791 "netdev=eth0\0" \ 792 "nor_ubootaddr0=0xEC000000\0" \ 793 "nor_ubootaddr1=0xEFF80000\0" \ 794 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \ 795 "run norkernelload; " \ 796 "bootm $kerneladdr - $dtbaddr\0" \ 797 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \ 798 "setenv cramfsaddr $part0base; " \ 799 "cramfsload $dtbaddr $dtbfile; " \ 800 "cramfsload $kerneladdr $kernelfile\0" \ 801 "part0base=0xEC100000\0" \ 802 "part0size=0x00700000\0" \ 803 "part1base=0xEC800000\0" \ 804 "part1size=0x02000000\0" \ 805 "part2base=0xEE800000\0" \ 806 "part2size=0x00800000\0" \ 807 "part3base=0xEF000000\0" \ 808 "part3size=0x00F80000\0" \ 809 "partENVbase=0xEC080000\0" \ 810 "partENVsize=0x00080000\0" \ 811 "program0=tftp part0-000000.bin; " \ 812 "protect off $part0base +$filesize; " \ 813 "erase $part0base +$filesize; " \ 814 "cp.b $loadaddr $part0base $filesize; " \ 815 "echo Verifying...; " \ 816 "cmp.b $loadaddr $part0base $filesize\0" \ 817 "program1=tftp part1-000000.bin; " \ 818 "protect off $part1base +$filesize; " \ 819 "erase $part1base +$filesize; " \ 820 "cp.b $loadaddr $part1base $filesize; " \ 821 "echo Verifying...; " \ 822 "cmp.b $loadaddr $part1base $filesize\0" \ 823 "program2=tftp part2-000000.bin; " \ 824 "protect off $part2base +$filesize; " \ 825 "erase $part2base +$filesize; " \ 826 "cp.b $loadaddr $part2base $filesize; " \ 827 "echo Verifying...; " \ 828 "cmp.b $loadaddr $part2base $filesize\0" \ 829 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 830 " console=$consoledev,$baudrate $othbootargs; " \ 831 "tftp $rootfsaddr $rootfsfile; " \ 832 "tftp $loadaddr $kernelfile; " \ 833 "tftp $dtbaddr $dtbfile; " \ 834 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 835 "ramdisk_size=120000\0" \ 836 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 837 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 838 "mw.l 0xffe0f008 0x00400000\0" \ 839 "rootfsaddr=0x02F00000\0" \ 840 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 841 "rootpath=/opt/nfsroot\0" \ 842 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 843 "sf probe 0; sf erase 0 +$filesize; " \ 844 "sf write $loadaddr 0 $filesize\0" \ 845 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 846 "protect off 0xeC000000 +$filesize; " \ 847 "erase 0xEC000000 +$filesize; " \ 848 "cp.b $loadaddr 0xEC000000 $filesize; " \ 849 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 850 "protect on 0xeC000000 +$filesize\0" \ 851 "tftpflash=tftpboot $loadaddr $uboot; " \ 852 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 853 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 854 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 855 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 856 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 857 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 858 "ubootfile=u-boot.bin\0" \ 859 "upgrade=run flashuboot\0" \ 860 "usb_phy_type=ulpi\0 " \ 861 "boot_nfs= " \ 862 "setenv bootargs root=/dev/nfs rw " \ 863 "nfsroot=$serverip:$rootpath " \ 864 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 865 "console=$consoledev,$baudrate $othbootargs;" \ 866 "tftp $loadaddr $bootfile;" \ 867 "tftp $fdtaddr $fdtfile;" \ 868 "bootm $loadaddr - $fdtaddr\0" \ 869 "boot_hd = " \ 870 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 871 "console=$consoledev,$baudrate $othbootargs;" \ 872 "usb start;" \ 873 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 874 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 875 "bootm $loadaddr - $fdtaddr\0" \ 876 "boot_usb_fat = " \ 877 "setenv bootargs root=/dev/ram rw " \ 878 "console=$consoledev,$baudrate $othbootargs " \ 879 "ramdisk_size=$ramdisk_size;" \ 880 "usb start;" \ 881 "fatload usb 0:2 $loadaddr $bootfile;" \ 882 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 883 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 884 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 885 "boot_usb_ext2 = " \ 886 "setenv bootargs root=/dev/ram rw " \ 887 "console=$consoledev,$baudrate $othbootargs " \ 888 "ramdisk_size=$ramdisk_size;" \ 889 "usb start;" \ 890 "ext2load usb 0:4 $loadaddr $bootfile;" \ 891 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 892 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 893 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 894 "boot_nor = " \ 895 "setenv bootargs root=/dev/$jffs2nor rw " \ 896 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 897 "bootm $norbootaddr - $norfdtaddr\0 " \ 898 "boot_ram = " \ 899 "setenv bootargs root=/dev/ram rw " \ 900 "console=$consoledev,$baudrate $othbootargs " \ 901 "ramdisk_size=$ramdisk_size;" \ 902 "tftp $ramdiskaddr $ramdiskfile;" \ 903 "tftp $loadaddr $bootfile;" \ 904 "tftp $fdtaddr $fdtfile;" \ 905 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" 906 907 #endif 908 #endif 909 910 #endif /* __CONFIG_H */ 911