1 /* 2 * Copyright 2013-2015 Arcturus Networks, Inc. 3 * http://www.arcturusnetworks.com/products/ucp1020/ 4 * based on include/configs/p1_p2_rdb_pc.h 5 * original copyright follows: 6 * Copyright 2009-2011 Freescale Semiconductor, Inc. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * QorIQ uCP1020-xx boards configuration file 13 */ 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 #define CONFIG_DISPLAY_BOARDINFO 18 19 #define CONFIG_FSL_ELBC 20 #define CONFIG_PCI 21 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 22 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 23 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 24 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 25 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 26 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 27 28 #if defined(CONFIG_TARTGET_UCP1020T1) 29 30 #define CONFIG_UCP1020_REV_1_3 31 32 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" 33 #define CONFIG_P1020 34 35 #define CONFIG_TSEC_ENET 36 #define CONFIG_TSEC1 37 #define CONFIG_TSEC3 38 #define CONFIG_HAS_ETH0 39 #define CONFIG_HAS_ETH1 40 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF 41 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE 42 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD 43 #define CONFIG_IPADDR 10.80.41.229 44 #define CONFIG_SERVERIP 10.80.41.227 45 #define CONFIG_NETMASK 255.255.252.0 46 #define CONFIG_ETHPRIME "eTSEC3" 47 48 #ifndef CONFIG_SPI_FLASH 49 #endif 50 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 51 52 #define CONFIG_MMC 53 #define CONFIG_SYS_L2_SIZE (256 << 10) 54 55 #define CONFIG_LAST_STAGE_INIT 56 57 #if !defined(CONFIG_DONGLE) 58 #define CONFIG_SILENT_CONSOLE 59 #endif 60 61 #endif 62 63 #if defined(CONFIG_TARGET_UCP1020) 64 65 #define CONFIG_UCP1020 66 #define CONFIG_UCP1020_REV_1_3 67 68 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" 69 #define CONFIG_P1020 70 71 #define CONFIG_TSEC_ENET 72 #define CONFIG_TSEC1 73 #define CONFIG_TSEC2 74 #define CONFIG_TSEC3 75 #define CONFIG_HAS_ETH0 76 #define CONFIG_HAS_ETH1 77 #define CONFIG_HAS_ETH2 78 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF 79 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE 80 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD 81 #define CONFIG_IPADDR 192.168.1.81 82 #define CONFIG_IPADDR1 192.168.1.82 83 #define CONFIG_IPADDR2 192.168.1.83 84 #define CONFIG_SERVERIP 192.168.1.80 85 #define CONFIG_GATEWAYIP 102.168.1.1 86 #define CONFIG_NETMASK 255.255.255.0 87 #define CONFIG_ETHPRIME "eTSEC1" 88 89 #ifndef CONFIG_SPI_FLASH 90 #endif 91 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 92 93 #define CONFIG_MMC 94 #define CONFIG_SYS_L2_SIZE (256 << 10) 95 96 #define CONFIG_LAST_STAGE_INIT 97 98 #endif 99 100 #ifdef CONFIG_SDCARD 101 #define CONFIG_RAMBOOT_SDCARD 102 #define CONFIG_SYS_RAMBOOT 103 #define CONFIG_SYS_EXTRA_ENV_RELOC 104 #define CONFIG_SYS_TEXT_BASE 0x11000000 105 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 106 #endif 107 108 #ifdef CONFIG_SPIFLASH 109 #define CONFIG_RAMBOOT_SPIFLASH 110 #define CONFIG_SYS_RAMBOOT 111 #define CONFIG_SYS_EXTRA_ENV_RELOC 112 #define CONFIG_SYS_TEXT_BASE 0x11000000 113 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 114 #endif 115 116 #ifndef CONFIG_SYS_TEXT_BASE 117 #define CONFIG_SYS_TEXT_BASE 0xeff80000 118 #endif 119 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000 120 121 #ifndef CONFIG_RESET_VECTOR_ADDRESS 122 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 123 #endif 124 125 #ifndef CONFIG_SYS_MONITOR_BASE 126 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 127 #endif 128 129 /* High Level Configuration Options */ 130 #define CONFIG_BOOKE 131 #define CONFIG_E500 132 /* #define CONFIG_MPC85xx */ 133 134 #define CONFIG_MP 135 136 #define CONFIG_FSL_LAW 137 138 #define CONFIG_ENV_OVERWRITE 139 140 #define CONFIG_CMD_SATA 141 #define CONFIG_SATA_SIL 142 #define CONFIG_SYS_SATA_MAX_DEVICE 2 143 #define CONFIG_LIBATA 144 #define CONFIG_LBA48 145 146 #define CONFIG_SYS_CLK_FREQ 66666666 147 #define CONFIG_DDR_CLK_FREQ 66666666 148 149 #define CONFIG_HWCONFIG 150 151 #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ 152 #define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */ 153 #define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */ 154 /* 155 * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details). 156 * there will be one entry in this array for each two (dummy) sensors in 157 * CONFIG_DTT_SENSORS. 158 * 159 * For uCP1020 module: 160 * - only one ADM1021/NCT72 161 * - i2c addr 0x41 162 * - conversion rate 0x02 = 0.25 conversions/second 163 * - ALERT output disabled 164 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg 165 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg 166 */ 167 #define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, \ 168 0x02, 0, 1, 0, 85, 1, 0, 85} } 169 170 #define CONFIG_CMD_DTT 171 172 /* 173 * These can be toggled for performance analysis, otherwise use default. 174 */ 175 #define CONFIG_L2_CACHE 176 #define CONFIG_BTB 177 178 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 179 180 #define CONFIG_ENABLE_36BIT_PHYS 181 182 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 183 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 184 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 185 186 #define CONFIG_SYS_CCSRBAR 0xffe00000 187 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 188 189 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 190 SPL code*/ 191 #ifdef CONFIG_SPL_BUILD 192 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 193 #endif 194 195 /* DDR Setup */ 196 #define CONFIG_DDR_ECC_ENABLE 197 #define CONFIG_SYS_FSL_DDR3 198 #ifndef CONFIG_DDR_ECC_ENABLE 199 #define CONFIG_SYS_DDR_RAW_TIMING 200 #define CONFIG_DDR_SPD 201 #endif 202 #define CONFIG_SYS_SPD_BUS_NUM 1 203 #undef CONFIG_FSL_DDR_INTERACTIVE 204 205 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 206 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 207 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 208 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 209 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 210 211 #define CONFIG_NUM_DDR_CONTROLLERS 1 212 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 213 214 /* Default settings for DDR3 */ 215 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 216 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 217 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 218 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 219 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 220 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 221 222 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 223 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 224 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 225 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 226 227 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 228 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 229 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 230 #define CONFIG_SYS_DDR_RCW_1 0x00000000 231 #define CONFIG_SYS_DDR_RCW_2 0x00000000 232 #ifdef CONFIG_DDR_ECC_ENABLE 233 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */ 234 #else 235 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 236 #endif 237 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 238 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 239 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 240 241 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 242 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 243 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 244 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 245 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 246 #define CONFIG_SYS_DDR_MODE_1 0x40461520 247 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 248 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 249 250 #undef CONFIG_CLOCKS_IN_MHZ 251 252 /* 253 * Memory map 254 * 255 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 256 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2) 257 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 258 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable 259 * (early boot only) 260 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 261 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 262 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 263 */ 264 265 /* 266 * Local Bus Definitions 267 */ 268 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 269 #define CONFIG_SYS_FLASH_BASE 0xec000000 270 271 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 272 273 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 274 | BR_PS_16 | BR_V) 275 276 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 277 278 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 279 #define CONFIG_SYS_FLASH_QUIET_TEST 280 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 281 282 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 283 284 #undef CONFIG_SYS_FLASH_CHECKSUM 285 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 286 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 287 288 #define CONFIG_FLASH_CFI_DRIVER 289 #define CONFIG_SYS_FLASH_CFI 290 #define CONFIG_SYS_FLASH_EMPTY_INFO 291 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 292 293 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 294 295 #define CONFIG_SYS_INIT_RAM_LOCK 296 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 297 /* Initial L1 address */ 298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 301 /* Size of used area in RAM */ 302 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 303 304 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 305 GENERATED_GBL_DATA_SIZE) 306 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 307 308 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ 309 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 310 311 #define CONFIG_SYS_PMC_BASE 0xff980000 312 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 313 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 314 BR_PS_8 | BR_V) 315 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 316 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 317 OR_GPCM_EAD) 318 319 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 320 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 321 #ifdef CONFIG_NAND_FSL_ELBC 322 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 323 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 324 #endif 325 326 /* Serial Port - controlled on board with jumper J8 327 * open - index 2 328 * shorted - index 1 329 */ 330 #define CONFIG_CONS_INDEX 1 331 #undef CONFIG_SERIAL_SOFTWARE_FIFO 332 #define CONFIG_SYS_NS16550 333 #define CONFIG_SYS_NS16550_SERIAL 334 #define CONFIG_SYS_NS16550_REG_SIZE 1 335 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 336 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 337 #define CONFIG_NS16550_MIN_FUNCTIONS 338 #endif 339 340 #define CONFIG_SYS_BAUDRATE_TABLE \ 341 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 342 343 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 344 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 345 346 /* Use the HUSH parser */ 347 #define CONFIG_SYS_HUSH_PARSER 348 349 /* 350 * Pass open firmware flat tree 351 */ 352 #define CONFIG_OF_LIBFDT 353 #define CONFIG_OF_BOARD_SETUP 354 #define CONFIG_OF_STDOUT_VIA_ALIAS 355 356 /* new uImage format support */ 357 #define CONFIG_FIT 358 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 359 360 /* I2C */ 361 #define CONFIG_SYS_I2C 362 #define CONFIG_SYS_I2C_FSL 363 #define CONFIG_SYS_FSL_I2C_SPEED 400000 364 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 365 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 366 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 367 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 368 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 369 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 370 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 371 372 #define CONFIG_RTC_DS1337 373 #define CONFIG_SYS_RTC_DS1337_NOOSC 374 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 375 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 376 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C 377 #define CONFIG_SYS_I2C_IDT6V49205B 0x69 378 379 /* 380 * eSPI - Enhanced SPI 381 */ 382 #define CONFIG_HARD_SPI 383 #define CONFIG_FSL_ESPI 384 385 #define CONFIG_SPI_FLASH_SST 1 386 #define CONFIG_SPI_FLASH_STMICRO 1 387 #define CONFIG_SPI_FLASH_WINBOND 1 388 #define CONFIG_CMD_SF 1 389 #define CONFIG_CMD_SPI 1 390 #define CONFIG_SF_DEFAULT_SPEED 10000000 391 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 392 393 #if defined(CONFIG_PCI) 394 /* 395 * General PCI 396 * Memory space is mapped 1-1, but I/O space must start from 0. 397 */ 398 399 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 400 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9" 401 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 402 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 403 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 404 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 405 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 406 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 407 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 408 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 409 410 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 411 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10" 412 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 413 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 414 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 415 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 416 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 417 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 418 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 419 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 420 421 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 422 #define CONFIG_CMD_PCI 423 424 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 425 #define CONFIG_DOS_PARTITION 426 #endif /* CONFIG_PCI */ 427 428 /* 429 * Environment 430 */ 431 #ifdef CONFIG_ENV_FIT_UCBOOT 432 433 #define CONFIG_ENV_IS_IN_FLASH 434 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000) 435 #define CONFIG_ENV_SIZE 0x20000 436 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 437 438 #else 439 440 #define CONFIG_ENV_SPI_BUS 0 441 #define CONFIG_ENV_SPI_CS 0 442 #define CONFIG_ENV_SPI_MAX_HZ 10000000 443 #define CONFIG_ENV_SPI_MODE 0 444 445 #ifdef CONFIG_RAMBOOT_SPIFLASH 446 447 #define CONFIG_ENV_IS_IN_SPI_FLASH 448 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */ 449 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */ 450 #define CONFIG_ENV_SECT_SIZE 0x1000 451 452 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 453 /* Address and size of Redundant Environment Sector */ 454 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 455 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 456 #endif 457 458 #elif defined(CONFIG_RAMBOOT_SDCARD) 459 #define CONFIG_ENV_IS_IN_MMC 460 #define CONFIG_FSL_FIXED_MMC_LOCATION 461 #define CONFIG_ENV_SIZE 0x2000 462 #define CONFIG_SYS_MMC_ENV_DEV 0 463 464 #elif defined(CONFIG_SYS_RAMBOOT) 465 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 466 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 467 #define CONFIG_ENV_SIZE 0x2000 468 469 #else 470 #define CONFIG_ENV_IS_IN_FLASH 471 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE) 472 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 473 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 474 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000) 475 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 476 /* Address and size of Redundant Environment Sector */ 477 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 478 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 479 #endif 480 481 #endif 482 483 #endif /* CONFIG_ENV_FIT_UCBOOT */ 484 485 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 486 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 487 488 /* 489 * Command line configuration. 490 */ 491 #define CONFIG_CMD_IRQ 492 #define CONFIG_CMD_PING 493 #define CONFIG_CMD_I2C 494 #define CONFIG_CMD_MII 495 #define CONFIG_CMD_DATE 496 #define CONFIG_CMD_I2C 497 #define CONFIG_CMD_IRQ 498 #define CONFIG_CMD_MII 499 #define CONFIG_CMD_PING 500 #define CONFIG_CMD_REGINFO 501 #define CONFIG_CMD_ERRATA 502 #define CONFIG_CMD_CRAMFS 503 #define CONFIG_CRAMFS_CMDLINE 504 505 /* 506 * USB 507 */ 508 #define CONFIG_HAS_FSL_DR_USB 509 510 #if defined(CONFIG_HAS_FSL_DR_USB) 511 #define CONFIG_USB_EHCI 512 513 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 514 515 #ifdef CONFIG_USB_EHCI 516 #define CONFIG_CMD_USB 517 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 518 #define CONFIG_USB_EHCI_FSL 519 #define CONFIG_USB_STORAGE 520 #endif 521 #endif 522 523 #undef CONFIG_WATCHDOG /* watchdog disabled */ 524 525 #ifdef CONFIG_MMC 526 #define CONFIG_FSL_ESDHC 527 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 528 #define CONFIG_CMD_MMC 529 #define CONFIG_MMC_SPI 530 #define CONFIG_CMD_MMC_SPI 531 #define CONFIG_GENERIC_MMC 532 #endif 533 534 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA) 535 #define CONFIG_CMD_EXT2 536 #define CONFIG_CMD_FAT 537 #define CONFIG_DOS_PARTITION 538 #endif 539 540 /* Misc Extra Settings */ 541 #undef CONFIG_WATCHDOG /* watchdog disabled */ 542 543 /* 544 * Miscellaneous configurable options 545 */ 546 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 547 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 548 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 549 #if defined(CONFIG_CMD_KGDB) 550 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 551 #else 552 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 553 #endif 554 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 555 /* Print Buffer Size */ 556 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 557 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 558 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ 559 560 /* 561 * For booting Linux, the board info and command line data 562 * have to be in the first 64 MB of memory, since this is 563 * the maximum mapped by the Linux kernel during initialization. 564 */ 565 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 566 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 567 568 #if defined(CONFIG_CMD_KGDB) 569 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 570 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 571 #endif 572 573 /* 574 * Environment Configuration 575 */ 576 577 #if defined(CONFIG_TSEC_ENET) 578 579 #if defined(CONFIG_UCP1020_REV_1_2) 580 #define CONFIG_PHY_MICREL_KSZ9021 581 #elif defined(CONFIG_UCP1020_REV_1_3) 582 #define CONFIG_PHY_MICREL_KSZ9031 583 #else 584 #error "UCP1020 module revision is not defined !!!" 585 #endif 586 587 #define CONFIG_CMD_DHCP 588 #define CONFIG_BOOTP_SERVERIP 589 590 #define CONFIG_MII /* MII PHY management */ 591 #define CONFIG_TSEC1_NAME "eTSEC1" 592 #define CONFIG_TSEC2_NAME "eTSEC2" 593 #define CONFIG_TSEC3_NAME "eTSEC3" 594 595 #define TSEC1_PHY_ADDR 4 596 #define TSEC2_PHY_ADDR 0 597 #define TSEC2_PHY_ADDR_SGMII 0x00 598 #define TSEC3_PHY_ADDR 6 599 600 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 601 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 602 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 603 604 #define TSEC1_PHYIDX 0 605 #define TSEC2_PHYIDX 0 606 #define TSEC3_PHYIDX 0 607 608 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 609 610 #endif 611 612 #define CONFIG_HOSTNAME UCP1020 613 #define CONFIG_ROOTPATH "/opt/nfsroot" 614 #define CONFIG_BOOTFILE "uImage" 615 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 616 617 /* default location for tftp and bootm */ 618 #define CONFIG_LOADADDR 1000000 619 620 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 621 622 #define CONFIG_BAUDRATE 115200 623 624 #if defined(CONFIG_DONGLE) 625 626 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ 627 #define CONFIG_EXTRA_ENV_SETTINGS \ 628 "bootcmd=run prog_spi_mbrbootcramfs\0" \ 629 "bootfile=uImage\0" \ 630 "consoledev=ttyS0\0" \ 631 "cramfsfile=image.cramfs\0" \ 632 "dtbaddr=0x00c00000\0" \ 633 "dtbfile=image.dtb\0" \ 634 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 635 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 636 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 637 "fileaddr=0x01000000\0" \ 638 "filesize=0x00080000\0" \ 639 "flashmbr=sf probe 0; " \ 640 "tftp $loadaddr $mbr; " \ 641 "sf erase $mbr_offset +$filesize; " \ 642 "sf write $loadaddr $mbr_offset $filesize\0" \ 643 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 644 "protect off $nor_recoveryaddr +$filesize; " \ 645 "erase $nor_recoveryaddr +$filesize; " \ 646 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 647 "protect on $nor_recoveryaddr +$filesize\0 " \ 648 "flashuboot=tftp $ubootaddr $ubootfile; " \ 649 "protect off $nor_ubootaddr +$filesize; " \ 650 "erase $nor_ubootaddr +$filesize; " \ 651 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 652 "protect on $nor_ubootaddr +$filesize\0 " \ 653 "flashworking=tftp $workingaddr $cramfsfile; " \ 654 "protect off $nor_workingaddr +$filesize; " \ 655 "erase $nor_workingaddr +$filesize; " \ 656 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 657 "protect on $nor_workingaddr +$filesize\0 " \ 658 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 659 "kerneladdr=0x01100000\0" \ 660 "kernelfile=uImage\0" \ 661 "loadaddr=0x01000000\0" \ 662 "mbr=uCP1020d.mbr\0" \ 663 "mbr_offset=0x00000000\0" \ 664 "mmbr=uCP1020Quiet.mbr\0" \ 665 "mmcpart=0:2\0" \ 666 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 667 "mmc erase 1 1; " \ 668 "mmc write $loadaddr 1 1\0" \ 669 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \ 670 "mmc erase 0x40 0x400; " \ 671 "mmc write $loadaddr 0x40 0x400\0" \ 672 "netdev=eth0\0" \ 673 "nor_recoveryaddr=0xEC0A0000\0" \ 674 "nor_ubootaddr=0xEFF80000\0" \ 675 "nor_workingaddr=0xECFA0000\0" \ 676 "norbootrecovery=setenv bootargs $recoverybootargs" \ 677 " console=$consoledev,$baudrate $othbootargs; " \ 678 "run norloadrecovery; " \ 679 "bootm $kerneladdr - $dtbaddr\0" \ 680 "norbootworking=setenv bootargs $workingbootargs" \ 681 " console=$consoledev,$baudrate $othbootargs; " \ 682 "run norloadworking; " \ 683 "bootm $kerneladdr - $dtbaddr\0" \ 684 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 685 "setenv cramfsaddr $nor_recoveryaddr; " \ 686 "cramfsload $dtbaddr $dtbfile; " \ 687 "cramfsload $kerneladdr $kernelfile\0" \ 688 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 689 "setenv cramfsaddr $nor_workingaddr; " \ 690 "cramfsload $dtbaddr $dtbfile; " \ 691 "cramfsload $kerneladdr $kernelfile\0" \ 692 "prog_spi_mbr=run spi__mbr\0" \ 693 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \ 694 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \ 695 "run spi__cramfs\0" \ 696 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 697 " console=$consoledev,$baudrate $othbootargs; " \ 698 "tftp $rootfsaddr $rootfsfile; " \ 699 "tftp $loadaddr $kernelfile; " \ 700 "tftp $dtbaddr $dtbfile; " \ 701 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 702 "ramdisk_size=120000\0" \ 703 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 704 "recoveryaddr=0x02F00000\0" \ 705 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 706 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 707 "mw.l 0xffe0f008 0x00400000\0" \ 708 "rootfsaddr=0x02F00000\0" \ 709 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 710 "rootpath=/opt/nfsroot\0" \ 711 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 712 "protect off 0xeC000000 +$filesize; " \ 713 "erase 0xEC000000 +$filesize; " \ 714 "cp.b $loadaddr 0xEC000000 $filesize; " \ 715 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 716 "protect on 0xeC000000 +$filesize\0" \ 717 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 718 "protect off 0xeFF80000 +$filesize; " \ 719 "erase 0xEFF80000 +$filesize; " \ 720 "cp.b $loadaddr 0xEFF80000 $filesize; " \ 721 "cmp.b $loadaddr 0xEFF80000 $filesize; " \ 722 "protect on 0xeFF80000 +$filesize\0" \ 723 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \ 724 "sf probe 0; sf erase 0x8000 +$filesize; " \ 725 "sf write $loadaddr 0x8000 $filesize\0" \ 726 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \ 727 "protect off 0xec0a0000 +$filesize; " \ 728 "erase 0xeC0A0000 +$filesize; " \ 729 "cp.b $loadaddr 0xeC0A0000 $filesize; " \ 730 "protect on 0xec0a0000 +$filesize\0" \ 731 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 732 "sf probe 1; sf erase 0 +$filesize; " \ 733 "sf write $loadaddr 0 $filesize\0" \ 734 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 735 "sf probe 0; sf erase 0 +$filesize; " \ 736 "sf write $loadaddr 0 $filesize\0" \ 737 "tftpflash=tftpboot $loadaddr $uboot; " \ 738 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 739 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 740 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 741 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 742 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 743 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 744 "ubootaddr=0x01000000\0" \ 745 "ubootfile=u-boot.bin\0" \ 746 "ubootd=u-boot4dongle.bin\0" \ 747 "upgrade=run flashworking\0" \ 748 "usb_phy_type=ulpi\0 " \ 749 "workingaddr=0x02F00000\0" \ 750 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 751 752 #else 753 754 #if defined(CONFIG_UCP1020T1) 755 756 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */ 757 #define CONFIG_EXTRA_ENV_SETTINGS \ 758 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ 759 "bootfile=uImage\0" \ 760 "consoledev=ttyS0\0" \ 761 "cramfsfile=image.cramfs\0" \ 762 "dtbaddr=0x00c00000\0" \ 763 "dtbfile=image.dtb\0" \ 764 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 765 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 766 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 767 "fileaddr=0x01000000\0" \ 768 "filesize=0x00080000\0" \ 769 "flashmbr=sf probe 0; " \ 770 "tftp $loadaddr $mbr; " \ 771 "sf erase $mbr_offset +$filesize; " \ 772 "sf write $loadaddr $mbr_offset $filesize\0" \ 773 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 774 "protect off $nor_recoveryaddr +$filesize; " \ 775 "erase $nor_recoveryaddr +$filesize; " \ 776 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 777 "protect on $nor_recoveryaddr +$filesize\0 " \ 778 "flashuboot=tftp $ubootaddr $ubootfile; " \ 779 "protect off $nor_ubootaddr +$filesize; " \ 780 "erase $nor_ubootaddr +$filesize; " \ 781 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 782 "protect on $nor_ubootaddr +$filesize\0 " \ 783 "flashworking=tftp $workingaddr $cramfsfile; " \ 784 "protect off $nor_workingaddr +$filesize; " \ 785 "erase $nor_workingaddr +$filesize; " \ 786 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 787 "protect on $nor_workingaddr +$filesize\0 " \ 788 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 789 "kerneladdr=0x01100000\0" \ 790 "kernelfile=uImage\0" \ 791 "loadaddr=0x01000000\0" \ 792 "mbr=uCP1020.mbr\0" \ 793 "mbr_offset=0x00000000\0" \ 794 "netdev=eth0\0" \ 795 "nor_recoveryaddr=0xEC0A0000\0" \ 796 "nor_ubootaddr=0xEFF80000\0" \ 797 "nor_workingaddr=0xECFA0000\0" \ 798 "norbootrecovery=setenv bootargs $recoverybootargs" \ 799 " console=$consoledev,$baudrate $othbootargs; " \ 800 "run norloadrecovery; " \ 801 "bootm $kerneladdr - $dtbaddr\0" \ 802 "norbootworking=setenv bootargs $workingbootargs" \ 803 " console=$consoledev,$baudrate $othbootargs; " \ 804 "run norloadworking; " \ 805 "bootm $kerneladdr - $dtbaddr\0" \ 806 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 807 "setenv cramfsaddr $nor_recoveryaddr; " \ 808 "cramfsload $dtbaddr $dtbfile; " \ 809 "cramfsload $kerneladdr $kernelfile\0" \ 810 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 811 "setenv cramfsaddr $nor_workingaddr; " \ 812 "cramfsload $dtbaddr $dtbfile; " \ 813 "cramfsload $kerneladdr $kernelfile\0" \ 814 "othbootargs=quiet\0" \ 815 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 816 " console=$consoledev,$baudrate $othbootargs; " \ 817 "tftp $rootfsaddr $rootfsfile; " \ 818 "tftp $loadaddr $kernelfile; " \ 819 "tftp $dtbaddr $dtbfile; " \ 820 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 821 "ramdisk_size=120000\0" \ 822 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 823 "recoveryaddr=0x02F00000\0" \ 824 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 825 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 826 "mw.l 0xffe0f008 0x00400000\0" \ 827 "rootfsaddr=0x02F00000\0" \ 828 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 829 "rootpath=/opt/nfsroot\0" \ 830 "silent=1\0" \ 831 "tftpflash=tftpboot $loadaddr $uboot; " \ 832 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 833 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 834 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 835 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 836 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 837 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 838 "ubootaddr=0x01000000\0" \ 839 "ubootfile=u-boot.bin\0" \ 840 "upgrade=run flashworking\0" \ 841 "workingaddr=0x02F00000\0" \ 842 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 843 844 #else /* For Arcturus Modules */ 845 846 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */ 847 #define CONFIG_EXTRA_ENV_SETTINGS \ 848 "bootcmd=run norkernel\0" \ 849 "bootfile=uImage\0" \ 850 "consoledev=ttyS0\0" \ 851 "dtbaddr=0x00c00000\0" \ 852 "dtbfile=image.dtb\0" \ 853 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 854 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 855 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 856 "fileaddr=0x01000000\0" \ 857 "filesize=0x00080000\0" \ 858 "flashmbr=sf probe 0; " \ 859 "tftp $loadaddr $mbr; " \ 860 "sf erase $mbr_offset +$filesize; " \ 861 "sf write $loadaddr $mbr_offset $filesize\0" \ 862 "flashuboot=tftp $loadaddr $ubootfile; " \ 863 "protect off $nor_ubootaddr0 +$filesize; " \ 864 "erase $nor_ubootaddr0 +$filesize; " \ 865 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \ 866 "protect on $nor_ubootaddr0 +$filesize; " \ 867 "protect off $nor_ubootaddr1 +$filesize; " \ 868 "erase $nor_ubootaddr1 +$filesize; " \ 869 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \ 870 "protect on $nor_ubootaddr1 +$filesize\0 " \ 871 "format0=protect off $part0base +$part0size; " \ 872 "erase $part0base +$part0size\0" \ 873 "format1=protect off $part1base +$part1size; " \ 874 "erase $part1base +$part1size\0" \ 875 "format2=protect off $part2base +$part2size; " \ 876 "erase $part2base +$part2size\0" \ 877 "format3=protect off $part3base +$part3size; " \ 878 "erase $part3base +$part3size\0" \ 879 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 880 "kerneladdr=0x01100000\0" \ 881 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \ 882 "kernelfile=uImage\0" \ 883 "loadaddr=0x01000000\0" \ 884 "mbr=uCP1020.mbr\0" \ 885 "mbr_offset=0x00000000\0" \ 886 "netdev=eth0\0" \ 887 "nor_ubootaddr0=0xEC000000\0" \ 888 "nor_ubootaddr1=0xEFF80000\0" \ 889 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \ 890 "run norkernelload; " \ 891 "bootm $kerneladdr - $dtbaddr\0" \ 892 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \ 893 "setenv cramfsaddr $part0base; " \ 894 "cramfsload $dtbaddr $dtbfile; " \ 895 "cramfsload $kerneladdr $kernelfile\0" \ 896 "part0base=0xEC100000\0" \ 897 "part0size=0x00700000\0" \ 898 "part1base=0xEC800000\0" \ 899 "part1size=0x02000000\0" \ 900 "part2base=0xEE800000\0" \ 901 "part2size=0x00800000\0" \ 902 "part3base=0xEF000000\0" \ 903 "part3size=0x00F80000\0" \ 904 "partENVbase=0xEC080000\0" \ 905 "partENVsize=0x00080000\0" \ 906 "program0=tftp part0-000000.bin; " \ 907 "protect off $part0base +$filesize; " \ 908 "erase $part0base +$filesize; " \ 909 "cp.b $loadaddr $part0base $filesize; " \ 910 "echo Verifying...; " \ 911 "cmp.b $loadaddr $part0base $filesize\0" \ 912 "program1=tftp part1-000000.bin; " \ 913 "protect off $part1base +$filesize; " \ 914 "erase $part1base +$filesize; " \ 915 "cp.b $loadaddr $part1base $filesize; " \ 916 "echo Verifying...; " \ 917 "cmp.b $loadaddr $part1base $filesize\0" \ 918 "program2=tftp part2-000000.bin; " \ 919 "protect off $part2base +$filesize; " \ 920 "erase $part2base +$filesize; " \ 921 "cp.b $loadaddr $part2base $filesize; " \ 922 "echo Verifying...; " \ 923 "cmp.b $loadaddr $part2base $filesize\0" \ 924 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 925 " console=$consoledev,$baudrate $othbootargs; " \ 926 "tftp $rootfsaddr $rootfsfile; " \ 927 "tftp $loadaddr $kernelfile; " \ 928 "tftp $dtbaddr $dtbfile; " \ 929 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 930 "ramdisk_size=120000\0" \ 931 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 932 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 933 "mw.l 0xffe0f008 0x00400000\0" \ 934 "rootfsaddr=0x02F00000\0" \ 935 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 936 "rootpath=/opt/nfsroot\0" \ 937 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 938 "sf probe 0; sf erase 0 +$filesize; " \ 939 "sf write $loadaddr 0 $filesize\0" \ 940 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 941 "protect off 0xeC000000 +$filesize; " \ 942 "erase 0xEC000000 +$filesize; " \ 943 "cp.b $loadaddr 0xEC000000 $filesize; " \ 944 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 945 "protect on 0xeC000000 +$filesize\0" \ 946 "tftpflash=tftpboot $loadaddr $uboot; " \ 947 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 948 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 949 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 950 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 951 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 952 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 953 "ubootfile=u-boot.bin\0" \ 954 "upgrade=run flashuboot\0" \ 955 "usb_phy_type=ulpi\0 " \ 956 "boot_nfs= " \ 957 "setenv bootargs root=/dev/nfs rw " \ 958 "nfsroot=$serverip:$rootpath " \ 959 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 960 "console=$consoledev,$baudrate $othbootargs;" \ 961 "tftp $loadaddr $bootfile;" \ 962 "tftp $fdtaddr $fdtfile;" \ 963 "bootm $loadaddr - $fdtaddr\0" \ 964 "boot_hd = " \ 965 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 966 "console=$consoledev,$baudrate $othbootargs;" \ 967 "usb start;" \ 968 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 969 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 970 "bootm $loadaddr - $fdtaddr\0" \ 971 "boot_usb_fat = " \ 972 "setenv bootargs root=/dev/ram rw " \ 973 "console=$consoledev,$baudrate $othbootargs " \ 974 "ramdisk_size=$ramdisk_size;" \ 975 "usb start;" \ 976 "fatload usb 0:2 $loadaddr $bootfile;" \ 977 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 978 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 979 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 980 "boot_usb_ext2 = " \ 981 "setenv bootargs root=/dev/ram rw " \ 982 "console=$consoledev,$baudrate $othbootargs " \ 983 "ramdisk_size=$ramdisk_size;" \ 984 "usb start;" \ 985 "ext2load usb 0:4 $loadaddr $bootfile;" \ 986 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 987 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 988 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 989 "boot_nor = " \ 990 "setenv bootargs root=/dev/$jffs2nor rw " \ 991 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 992 "bootm $norbootaddr - $norfdtaddr\0 " \ 993 "boot_ram = " \ 994 "setenv bootargs root=/dev/ram rw " \ 995 "console=$consoledev,$baudrate $othbootargs " \ 996 "ramdisk_size=$ramdisk_size;" \ 997 "tftp $ramdiskaddr $ramdiskfile;" \ 998 "tftp $loadaddr $bootfile;" \ 999 "tftp $fdtaddr $fdtfile;" \ 1000 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" 1001 1002 #endif 1003 #endif 1004 1005 #endif /* __CONFIG_H */ 1006