1 /* 2 * Copyright 2013-2015 Arcturus Networks, Inc. 3 * http://www.arcturusnetworks.com/products/ucp1020/ 4 * based on include/configs/p1_p2_rdb_pc.h 5 * original copyright follows: 6 * Copyright 2009-2011 Freescale Semiconductor, Inc. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * QorIQ uCP1020-xx boards configuration file 13 */ 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 18 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 19 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 20 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 21 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 22 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 23 24 #if defined(CONFIG_TARTGET_UCP1020T1) 25 26 #define CONFIG_UCP1020_REV_1_3 27 28 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" 29 30 #define CONFIG_TSEC_ENET 31 #define CONFIG_TSEC1 32 #define CONFIG_TSEC3 33 #define CONFIG_HAS_ETH0 34 #define CONFIG_HAS_ETH1 35 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF 36 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE 37 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD 38 #define CONFIG_IPADDR 10.80.41.229 39 #define CONFIG_SERVERIP 10.80.41.227 40 #define CONFIG_NETMASK 255.255.252.0 41 #define CONFIG_ETHPRIME "eTSEC3" 42 43 #ifndef CONFIG_SPI_FLASH 44 #endif 45 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 46 47 #define CONFIG_SYS_L2_SIZE (256 << 10) 48 49 #define CONFIG_LAST_STAGE_INIT 50 51 #endif 52 53 #if defined(CONFIG_TARGET_UCP1020) 54 55 #define CONFIG_UCP1020 56 #define CONFIG_UCP1020_REV_1_3 57 58 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" 59 60 #define CONFIG_TSEC_ENET 61 #define CONFIG_TSEC1 62 #define CONFIG_TSEC2 63 #define CONFIG_TSEC3 64 #define CONFIG_HAS_ETH0 65 #define CONFIG_HAS_ETH1 66 #define CONFIG_HAS_ETH2 67 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF 68 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE 69 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD 70 #define CONFIG_IPADDR 192.168.1.81 71 #define CONFIG_IPADDR1 192.168.1.82 72 #define CONFIG_IPADDR2 192.168.1.83 73 #define CONFIG_SERVERIP 192.168.1.80 74 #define CONFIG_GATEWAYIP 102.168.1.1 75 #define CONFIG_NETMASK 255.255.255.0 76 #define CONFIG_ETHPRIME "eTSEC1" 77 78 #ifndef CONFIG_SPI_FLASH 79 #endif 80 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 81 82 #define CONFIG_SYS_L2_SIZE (256 << 10) 83 84 #define CONFIG_LAST_STAGE_INIT 85 86 #endif 87 88 #ifdef CONFIG_SDCARD 89 #define CONFIG_RAMBOOT_SDCARD 90 #define CONFIG_SYS_RAMBOOT 91 #define CONFIG_SYS_EXTRA_ENV_RELOC 92 #define CONFIG_SYS_TEXT_BASE 0x11000000 93 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 94 #endif 95 96 #ifdef CONFIG_SPIFLASH 97 #define CONFIG_RAMBOOT_SPIFLASH 98 #define CONFIG_SYS_RAMBOOT 99 #define CONFIG_SYS_EXTRA_ENV_RELOC 100 #define CONFIG_SYS_TEXT_BASE 0x11000000 101 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 102 #endif 103 104 #ifndef CONFIG_SYS_TEXT_BASE 105 #define CONFIG_SYS_TEXT_BASE 0xeff80000 106 #endif 107 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000 108 109 #ifndef CONFIG_RESET_VECTOR_ADDRESS 110 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 111 #endif 112 113 #ifndef CONFIG_SYS_MONITOR_BASE 114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 115 #endif 116 117 #define CONFIG_MP 118 119 #define CONFIG_ENV_OVERWRITE 120 121 #define CONFIG_SATA_SIL 122 #define CONFIG_SYS_SATA_MAX_DEVICE 2 123 #define CONFIG_LIBATA 124 #define CONFIG_LBA48 125 126 #define CONFIG_SYS_CLK_FREQ 66666666 127 #define CONFIG_DDR_CLK_FREQ 66666666 128 129 #define CONFIG_HWCONFIG 130 131 /* 132 * These can be toggled for performance analysis, otherwise use default. 133 */ 134 #define CONFIG_L2_CACHE 135 #define CONFIG_BTB 136 137 #define CONFIG_ENABLE_36BIT_PHYS 138 139 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 140 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 141 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 142 143 #define CONFIG_SYS_CCSRBAR 0xffe00000 144 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 145 146 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 147 SPL code*/ 148 #ifdef CONFIG_SPL_BUILD 149 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 150 #endif 151 152 /* DDR Setup */ 153 #define CONFIG_DDR_ECC_ENABLE 154 #ifndef CONFIG_DDR_ECC_ENABLE 155 #define CONFIG_SYS_DDR_RAW_TIMING 156 #define CONFIG_DDR_SPD 157 #endif 158 #define CONFIG_SYS_SPD_BUS_NUM 1 159 #undef CONFIG_FSL_DDR_INTERACTIVE 160 161 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 162 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 163 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 164 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 165 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 166 167 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 168 169 /* Default settings for DDR3 */ 170 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 171 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 172 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 173 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 174 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 175 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 176 177 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 178 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 179 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 180 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 181 182 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 183 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 184 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 185 #define CONFIG_SYS_DDR_RCW_1 0x00000000 186 #define CONFIG_SYS_DDR_RCW_2 0x00000000 187 #ifdef CONFIG_DDR_ECC_ENABLE 188 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */ 189 #else 190 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 191 #endif 192 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 193 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 194 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 195 196 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 197 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 198 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 199 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 200 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 201 #define CONFIG_SYS_DDR_MODE_1 0x40461520 202 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 203 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 204 205 #undef CONFIG_CLOCKS_IN_MHZ 206 207 /* 208 * Memory map 209 * 210 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 211 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2) 212 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 213 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable 214 * (early boot only) 215 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 216 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 217 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 218 */ 219 220 /* 221 * Local Bus Definitions 222 */ 223 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 224 #define CONFIG_SYS_FLASH_BASE 0xec000000 225 226 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 227 228 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 229 | BR_PS_16 | BR_V) 230 231 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 232 233 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 234 #define CONFIG_SYS_FLASH_QUIET_TEST 235 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 236 237 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 238 239 #undef CONFIG_SYS_FLASH_CHECKSUM 240 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 241 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 242 243 #define CONFIG_FLASH_CFI_DRIVER 244 #define CONFIG_SYS_FLASH_CFI 245 #define CONFIG_SYS_FLASH_EMPTY_INFO 246 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 247 248 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 249 250 #define CONFIG_SYS_INIT_RAM_LOCK 251 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 252 /* Initial L1 address */ 253 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 254 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 255 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 256 /* Size of used area in RAM */ 257 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 258 259 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 260 GENERATED_GBL_DATA_SIZE) 261 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 262 263 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ 264 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 265 266 #define CONFIG_SYS_PMC_BASE 0xff980000 267 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 268 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 269 BR_PS_8 | BR_V) 270 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 271 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 272 OR_GPCM_EAD) 273 274 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 275 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 276 #ifdef CONFIG_NAND_FSL_ELBC 277 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 278 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 279 #endif 280 281 /* Serial Port - controlled on board with jumper J8 282 * open - index 2 283 * shorted - index 1 284 */ 285 #define CONFIG_CONS_INDEX 1 286 #undef CONFIG_SERIAL_SOFTWARE_FIFO 287 #define CONFIG_SYS_NS16550_SERIAL 288 #define CONFIG_SYS_NS16550_REG_SIZE 1 289 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 290 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 291 #define CONFIG_NS16550_MIN_FUNCTIONS 292 #endif 293 294 #define CONFIG_SYS_BAUDRATE_TABLE \ 295 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 296 297 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 298 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 299 300 /* I2C */ 301 #define CONFIG_SYS_I2C 302 #define CONFIG_SYS_I2C_FSL 303 #define CONFIG_SYS_FSL_I2C_SPEED 400000 304 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 305 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 306 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 307 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 308 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 309 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 310 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 311 312 #define CONFIG_RTC_DS1337 313 #define CONFIG_RTC_DS1337_NOOSC 314 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 315 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 316 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C 317 #define CONFIG_SYS_I2C_IDT6V49205B 0x69 318 319 /* 320 * eSPI - Enhanced SPI 321 */ 322 #define CONFIG_HARD_SPI 323 324 #define CONFIG_SF_DEFAULT_SPEED 10000000 325 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 326 327 #if defined(CONFIG_PCI) 328 /* 329 * General PCI 330 * Memory space is mapped 1-1, but I/O space must start from 0. 331 */ 332 333 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 334 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9" 335 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 336 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 337 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 338 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 339 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 340 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 341 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 342 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 343 344 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 345 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10" 346 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 347 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 348 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 349 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 350 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 351 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 352 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 353 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 354 355 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 356 #endif /* CONFIG_PCI */ 357 358 /* 359 * Environment 360 */ 361 #ifdef CONFIG_ENV_FIT_UCBOOT 362 363 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000) 364 #define CONFIG_ENV_SIZE 0x20000 365 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 366 367 #else 368 369 #define CONFIG_ENV_SPI_BUS 0 370 #define CONFIG_ENV_SPI_CS 0 371 #define CONFIG_ENV_SPI_MAX_HZ 10000000 372 #define CONFIG_ENV_SPI_MODE 0 373 374 #ifdef CONFIG_RAMBOOT_SPIFLASH 375 376 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */ 377 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */ 378 #define CONFIG_ENV_SECT_SIZE 0x1000 379 380 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 381 /* Address and size of Redundant Environment Sector */ 382 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 383 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 384 #endif 385 386 #elif defined(CONFIG_RAMBOOT_SDCARD) 387 #define CONFIG_FSL_FIXED_MMC_LOCATION 388 #define CONFIG_ENV_SIZE 0x2000 389 #define CONFIG_SYS_MMC_ENV_DEV 0 390 391 #elif defined(CONFIG_SYS_RAMBOOT) 392 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 393 #define CONFIG_ENV_SIZE 0x2000 394 395 #else 396 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE) 397 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 398 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 399 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000) 400 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 401 /* Address and size of Redundant Environment Sector */ 402 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 403 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 404 #endif 405 406 #endif 407 408 #endif /* CONFIG_ENV_FIT_UCBOOT */ 409 410 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 411 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 412 413 /* 414 * USB 415 */ 416 #define CONFIG_HAS_FSL_DR_USB 417 418 #if defined(CONFIG_HAS_FSL_DR_USB) 419 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 420 421 #ifdef CONFIG_USB_EHCI_HCD 422 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 423 #define CONFIG_USB_EHCI_FSL 424 #endif 425 #endif 426 427 #undef CONFIG_WATCHDOG /* watchdog disabled */ 428 429 #ifdef CONFIG_MMC 430 #define CONFIG_FSL_ESDHC 431 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 432 #define CONFIG_MMC_SPI 433 #endif 434 435 /* Misc Extra Settings */ 436 #undef CONFIG_WATCHDOG /* watchdog disabled */ 437 438 /* 439 * Miscellaneous configurable options 440 */ 441 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 442 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 443 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 444 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ 445 446 /* 447 * For booting Linux, the board info and command line data 448 * have to be in the first 64 MB of memory, since this is 449 * the maximum mapped by the Linux kernel during initialization. 450 */ 451 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 452 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 453 454 #if defined(CONFIG_CMD_KGDB) 455 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 456 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 457 #endif 458 459 /* 460 * Environment Configuration 461 */ 462 463 #if defined(CONFIG_TSEC_ENET) 464 465 #if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3) 466 #else 467 #error "UCP1020 module revision is not defined !!!" 468 #endif 469 470 #define CONFIG_BOOTP_SERVERIP 471 472 #define CONFIG_MII /* MII PHY management */ 473 #define CONFIG_TSEC1_NAME "eTSEC1" 474 #define CONFIG_TSEC2_NAME "eTSEC2" 475 #define CONFIG_TSEC3_NAME "eTSEC3" 476 477 #define TSEC1_PHY_ADDR 4 478 #define TSEC2_PHY_ADDR 0 479 #define TSEC2_PHY_ADDR_SGMII 0x00 480 #define TSEC3_PHY_ADDR 6 481 482 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 483 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 484 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 485 486 #define TSEC1_PHYIDX 0 487 #define TSEC2_PHYIDX 0 488 #define TSEC3_PHYIDX 0 489 490 #endif 491 492 #define CONFIG_HOSTNAME UCP1020 493 #define CONFIG_ROOTPATH "/opt/nfsroot" 494 #define CONFIG_BOOTFILE "uImage" 495 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 496 497 /* default location for tftp and bootm */ 498 #define CONFIG_LOADADDR 1000000 499 500 #if defined(CONFIG_DONGLE) 501 502 #define CONFIG_EXTRA_ENV_SETTINGS \ 503 "bootcmd=run prog_spi_mbrbootcramfs\0" \ 504 "bootfile=uImage\0" \ 505 "consoledev=ttyS0\0" \ 506 "cramfsfile=image.cramfs\0" \ 507 "dtbaddr=0x00c00000\0" \ 508 "dtbfile=image.dtb\0" \ 509 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 510 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 511 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 512 "fileaddr=0x01000000\0" \ 513 "filesize=0x00080000\0" \ 514 "flashmbr=sf probe 0; " \ 515 "tftp $loadaddr $mbr; " \ 516 "sf erase $mbr_offset +$filesize; " \ 517 "sf write $loadaddr $mbr_offset $filesize\0" \ 518 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 519 "protect off $nor_recoveryaddr +$filesize; " \ 520 "erase $nor_recoveryaddr +$filesize; " \ 521 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 522 "protect on $nor_recoveryaddr +$filesize\0 " \ 523 "flashuboot=tftp $ubootaddr $ubootfile; " \ 524 "protect off $nor_ubootaddr +$filesize; " \ 525 "erase $nor_ubootaddr +$filesize; " \ 526 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 527 "protect on $nor_ubootaddr +$filesize\0 " \ 528 "flashworking=tftp $workingaddr $cramfsfile; " \ 529 "protect off $nor_workingaddr +$filesize; " \ 530 "erase $nor_workingaddr +$filesize; " \ 531 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 532 "protect on $nor_workingaddr +$filesize\0 " \ 533 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 534 "kerneladdr=0x01100000\0" \ 535 "kernelfile=uImage\0" \ 536 "loadaddr=0x01000000\0" \ 537 "mbr=uCP1020d.mbr\0" \ 538 "mbr_offset=0x00000000\0" \ 539 "mmbr=uCP1020Quiet.mbr\0" \ 540 "mmcpart=0:2\0" \ 541 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 542 "mmc erase 1 1; " \ 543 "mmc write $loadaddr 1 1\0" \ 544 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \ 545 "mmc erase 0x40 0x400; " \ 546 "mmc write $loadaddr 0x40 0x400\0" \ 547 "netdev=eth0\0" \ 548 "nor_recoveryaddr=0xEC0A0000\0" \ 549 "nor_ubootaddr=0xEFF80000\0" \ 550 "nor_workingaddr=0xECFA0000\0" \ 551 "norbootrecovery=setenv bootargs $recoverybootargs" \ 552 " console=$consoledev,$baudrate $othbootargs; " \ 553 "run norloadrecovery; " \ 554 "bootm $kerneladdr - $dtbaddr\0" \ 555 "norbootworking=setenv bootargs $workingbootargs" \ 556 " console=$consoledev,$baudrate $othbootargs; " \ 557 "run norloadworking; " \ 558 "bootm $kerneladdr - $dtbaddr\0" \ 559 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 560 "setenv cramfsaddr $nor_recoveryaddr; " \ 561 "cramfsload $dtbaddr $dtbfile; " \ 562 "cramfsload $kerneladdr $kernelfile\0" \ 563 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 564 "setenv cramfsaddr $nor_workingaddr; " \ 565 "cramfsload $dtbaddr $dtbfile; " \ 566 "cramfsload $kerneladdr $kernelfile\0" \ 567 "prog_spi_mbr=run spi__mbr\0" \ 568 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \ 569 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \ 570 "run spi__cramfs\0" \ 571 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 572 " console=$consoledev,$baudrate $othbootargs; " \ 573 "tftp $rootfsaddr $rootfsfile; " \ 574 "tftp $loadaddr $kernelfile; " \ 575 "tftp $dtbaddr $dtbfile; " \ 576 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 577 "ramdisk_size=120000\0" \ 578 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 579 "recoveryaddr=0x02F00000\0" \ 580 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 581 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 582 "mw.l 0xffe0f008 0x00400000\0" \ 583 "rootfsaddr=0x02F00000\0" \ 584 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 585 "rootpath=/opt/nfsroot\0" \ 586 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 587 "protect off 0xeC000000 +$filesize; " \ 588 "erase 0xEC000000 +$filesize; " \ 589 "cp.b $loadaddr 0xEC000000 $filesize; " \ 590 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 591 "protect on 0xeC000000 +$filesize\0" \ 592 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 593 "protect off 0xeFF80000 +$filesize; " \ 594 "erase 0xEFF80000 +$filesize; " \ 595 "cp.b $loadaddr 0xEFF80000 $filesize; " \ 596 "cmp.b $loadaddr 0xEFF80000 $filesize; " \ 597 "protect on 0xeFF80000 +$filesize\0" \ 598 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \ 599 "sf probe 0; sf erase 0x8000 +$filesize; " \ 600 "sf write $loadaddr 0x8000 $filesize\0" \ 601 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \ 602 "protect off 0xec0a0000 +$filesize; " \ 603 "erase 0xeC0A0000 +$filesize; " \ 604 "cp.b $loadaddr 0xeC0A0000 $filesize; " \ 605 "protect on 0xec0a0000 +$filesize\0" \ 606 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 607 "sf probe 1; sf erase 0 +$filesize; " \ 608 "sf write $loadaddr 0 $filesize\0" \ 609 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 610 "sf probe 0; sf erase 0 +$filesize; " \ 611 "sf write $loadaddr 0 $filesize\0" \ 612 "tftpflash=tftpboot $loadaddr $uboot; " \ 613 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 614 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 615 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 616 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 617 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 618 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 619 "ubootaddr=0x01000000\0" \ 620 "ubootfile=u-boot.bin\0" \ 621 "ubootd=u-boot4dongle.bin\0" \ 622 "upgrade=run flashworking\0" \ 623 "usb_phy_type=ulpi\0 " \ 624 "workingaddr=0x02F00000\0" \ 625 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 626 627 #else 628 629 #if defined(CONFIG_UCP1020T1) 630 631 #define CONFIG_EXTRA_ENV_SETTINGS \ 632 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ 633 "bootfile=uImage\0" \ 634 "consoledev=ttyS0\0" \ 635 "cramfsfile=image.cramfs\0" \ 636 "dtbaddr=0x00c00000\0" \ 637 "dtbfile=image.dtb\0" \ 638 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 639 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 640 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 641 "fileaddr=0x01000000\0" \ 642 "filesize=0x00080000\0" \ 643 "flashmbr=sf probe 0; " \ 644 "tftp $loadaddr $mbr; " \ 645 "sf erase $mbr_offset +$filesize; " \ 646 "sf write $loadaddr $mbr_offset $filesize\0" \ 647 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 648 "protect off $nor_recoveryaddr +$filesize; " \ 649 "erase $nor_recoveryaddr +$filesize; " \ 650 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 651 "protect on $nor_recoveryaddr +$filesize\0 " \ 652 "flashuboot=tftp $ubootaddr $ubootfile; " \ 653 "protect off $nor_ubootaddr +$filesize; " \ 654 "erase $nor_ubootaddr +$filesize; " \ 655 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 656 "protect on $nor_ubootaddr +$filesize\0 " \ 657 "flashworking=tftp $workingaddr $cramfsfile; " \ 658 "protect off $nor_workingaddr +$filesize; " \ 659 "erase $nor_workingaddr +$filesize; " \ 660 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 661 "protect on $nor_workingaddr +$filesize\0 " \ 662 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 663 "kerneladdr=0x01100000\0" \ 664 "kernelfile=uImage\0" \ 665 "loadaddr=0x01000000\0" \ 666 "mbr=uCP1020.mbr\0" \ 667 "mbr_offset=0x00000000\0" \ 668 "netdev=eth0\0" \ 669 "nor_recoveryaddr=0xEC0A0000\0" \ 670 "nor_ubootaddr=0xEFF80000\0" \ 671 "nor_workingaddr=0xECFA0000\0" \ 672 "norbootrecovery=setenv bootargs $recoverybootargs" \ 673 " console=$consoledev,$baudrate $othbootargs; " \ 674 "run norloadrecovery; " \ 675 "bootm $kerneladdr - $dtbaddr\0" \ 676 "norbootworking=setenv bootargs $workingbootargs" \ 677 " console=$consoledev,$baudrate $othbootargs; " \ 678 "run norloadworking; " \ 679 "bootm $kerneladdr - $dtbaddr\0" \ 680 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 681 "setenv cramfsaddr $nor_recoveryaddr; " \ 682 "cramfsload $dtbaddr $dtbfile; " \ 683 "cramfsload $kerneladdr $kernelfile\0" \ 684 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 685 "setenv cramfsaddr $nor_workingaddr; " \ 686 "cramfsload $dtbaddr $dtbfile; " \ 687 "cramfsload $kerneladdr $kernelfile\0" \ 688 "othbootargs=quiet\0" \ 689 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 690 " console=$consoledev,$baudrate $othbootargs; " \ 691 "tftp $rootfsaddr $rootfsfile; " \ 692 "tftp $loadaddr $kernelfile; " \ 693 "tftp $dtbaddr $dtbfile; " \ 694 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 695 "ramdisk_size=120000\0" \ 696 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 697 "recoveryaddr=0x02F00000\0" \ 698 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 699 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 700 "mw.l 0xffe0f008 0x00400000\0" \ 701 "rootfsaddr=0x02F00000\0" \ 702 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 703 "rootpath=/opt/nfsroot\0" \ 704 "silent=1\0" \ 705 "tftpflash=tftpboot $loadaddr $uboot; " \ 706 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 707 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 708 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 709 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 710 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 711 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 712 "ubootaddr=0x01000000\0" \ 713 "ubootfile=u-boot.bin\0" \ 714 "upgrade=run flashworking\0" \ 715 "workingaddr=0x02F00000\0" \ 716 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 717 718 #else /* For Arcturus Modules */ 719 720 #define CONFIG_EXTRA_ENV_SETTINGS \ 721 "bootcmd=run norkernel\0" \ 722 "bootfile=uImage\0" \ 723 "consoledev=ttyS0\0" \ 724 "dtbaddr=0x00c00000\0" \ 725 "dtbfile=image.dtb\0" \ 726 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 727 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 728 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 729 "fileaddr=0x01000000\0" \ 730 "filesize=0x00080000\0" \ 731 "flashmbr=sf probe 0; " \ 732 "tftp $loadaddr $mbr; " \ 733 "sf erase $mbr_offset +$filesize; " \ 734 "sf write $loadaddr $mbr_offset $filesize\0" \ 735 "flashuboot=tftp $loadaddr $ubootfile; " \ 736 "protect off $nor_ubootaddr0 +$filesize; " \ 737 "erase $nor_ubootaddr0 +$filesize; " \ 738 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \ 739 "protect on $nor_ubootaddr0 +$filesize; " \ 740 "protect off $nor_ubootaddr1 +$filesize; " \ 741 "erase $nor_ubootaddr1 +$filesize; " \ 742 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \ 743 "protect on $nor_ubootaddr1 +$filesize\0 " \ 744 "format0=protect off $part0base +$part0size; " \ 745 "erase $part0base +$part0size\0" \ 746 "format1=protect off $part1base +$part1size; " \ 747 "erase $part1base +$part1size\0" \ 748 "format2=protect off $part2base +$part2size; " \ 749 "erase $part2base +$part2size\0" \ 750 "format3=protect off $part3base +$part3size; " \ 751 "erase $part3base +$part3size\0" \ 752 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 753 "kerneladdr=0x01100000\0" \ 754 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \ 755 "kernelfile=uImage\0" \ 756 "loadaddr=0x01000000\0" \ 757 "mbr=uCP1020.mbr\0" \ 758 "mbr_offset=0x00000000\0" \ 759 "netdev=eth0\0" \ 760 "nor_ubootaddr0=0xEC000000\0" \ 761 "nor_ubootaddr1=0xEFF80000\0" \ 762 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \ 763 "run norkernelload; " \ 764 "bootm $kerneladdr - $dtbaddr\0" \ 765 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \ 766 "setenv cramfsaddr $part0base; " \ 767 "cramfsload $dtbaddr $dtbfile; " \ 768 "cramfsload $kerneladdr $kernelfile\0" \ 769 "part0base=0xEC100000\0" \ 770 "part0size=0x00700000\0" \ 771 "part1base=0xEC800000\0" \ 772 "part1size=0x02000000\0" \ 773 "part2base=0xEE800000\0" \ 774 "part2size=0x00800000\0" \ 775 "part3base=0xEF000000\0" \ 776 "part3size=0x00F80000\0" \ 777 "partENVbase=0xEC080000\0" \ 778 "partENVsize=0x00080000\0" \ 779 "program0=tftp part0-000000.bin; " \ 780 "protect off $part0base +$filesize; " \ 781 "erase $part0base +$filesize; " \ 782 "cp.b $loadaddr $part0base $filesize; " \ 783 "echo Verifying...; " \ 784 "cmp.b $loadaddr $part0base $filesize\0" \ 785 "program1=tftp part1-000000.bin; " \ 786 "protect off $part1base +$filesize; " \ 787 "erase $part1base +$filesize; " \ 788 "cp.b $loadaddr $part1base $filesize; " \ 789 "echo Verifying...; " \ 790 "cmp.b $loadaddr $part1base $filesize\0" \ 791 "program2=tftp part2-000000.bin; " \ 792 "protect off $part2base +$filesize; " \ 793 "erase $part2base +$filesize; " \ 794 "cp.b $loadaddr $part2base $filesize; " \ 795 "echo Verifying...; " \ 796 "cmp.b $loadaddr $part2base $filesize\0" \ 797 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 798 " console=$consoledev,$baudrate $othbootargs; " \ 799 "tftp $rootfsaddr $rootfsfile; " \ 800 "tftp $loadaddr $kernelfile; " \ 801 "tftp $dtbaddr $dtbfile; " \ 802 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 803 "ramdisk_size=120000\0" \ 804 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 805 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 806 "mw.l 0xffe0f008 0x00400000\0" \ 807 "rootfsaddr=0x02F00000\0" \ 808 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 809 "rootpath=/opt/nfsroot\0" \ 810 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 811 "sf probe 0; sf erase 0 +$filesize; " \ 812 "sf write $loadaddr 0 $filesize\0" \ 813 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 814 "protect off 0xeC000000 +$filesize; " \ 815 "erase 0xEC000000 +$filesize; " \ 816 "cp.b $loadaddr 0xEC000000 $filesize; " \ 817 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 818 "protect on 0xeC000000 +$filesize\0" \ 819 "tftpflash=tftpboot $loadaddr $uboot; " \ 820 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 821 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 822 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 823 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 824 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 825 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 826 "ubootfile=u-boot.bin\0" \ 827 "upgrade=run flashuboot\0" \ 828 "usb_phy_type=ulpi\0 " \ 829 "boot_nfs= " \ 830 "setenv bootargs root=/dev/nfs rw " \ 831 "nfsroot=$serverip:$rootpath " \ 832 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 833 "console=$consoledev,$baudrate $othbootargs;" \ 834 "tftp $loadaddr $bootfile;" \ 835 "tftp $fdtaddr $fdtfile;" \ 836 "bootm $loadaddr - $fdtaddr\0" \ 837 "boot_hd = " \ 838 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 839 "console=$consoledev,$baudrate $othbootargs;" \ 840 "usb start;" \ 841 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 842 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 843 "bootm $loadaddr - $fdtaddr\0" \ 844 "boot_usb_fat = " \ 845 "setenv bootargs root=/dev/ram rw " \ 846 "console=$consoledev,$baudrate $othbootargs " \ 847 "ramdisk_size=$ramdisk_size;" \ 848 "usb start;" \ 849 "fatload usb 0:2 $loadaddr $bootfile;" \ 850 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 851 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 852 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 853 "boot_usb_ext2 = " \ 854 "setenv bootargs root=/dev/ram rw " \ 855 "console=$consoledev,$baudrate $othbootargs " \ 856 "ramdisk_size=$ramdisk_size;" \ 857 "usb start;" \ 858 "ext2load usb 0:4 $loadaddr $bootfile;" \ 859 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 860 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 861 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 862 "boot_nor = " \ 863 "setenv bootargs root=/dev/$jffs2nor rw " \ 864 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 865 "bootm $norbootaddr - $norfdtaddr\0 " \ 866 "boot_ram = " \ 867 "setenv bootargs root=/dev/ram rw " \ 868 "console=$consoledev,$baudrate $othbootargs " \ 869 "ramdisk_size=$ramdisk_size;" \ 870 "tftp $ramdiskaddr $ramdiskfile;" \ 871 "tftp $loadaddr $bootfile;" \ 872 "tftp $fdtaddr $fdtfile;" \ 873 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" 874 875 #endif 876 #endif 877 878 #endif /* __CONFIG_H */ 879