1 /* 2 * Copyright 2013-2015 Arcturus Networks, Inc. 3 * http://www.arcturusnetworks.com/products/ucp1020/ 4 * based on include/configs/p1_p2_rdb_pc.h 5 * original copyright follows: 6 * Copyright 2009-2011 Freescale Semiconductor, Inc. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * QorIQ uCP1020-xx boards configuration file 13 */ 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 #define CONFIG_FSL_ELBC 18 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 19 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 20 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 21 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 22 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 23 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 24 25 #if defined(CONFIG_TARTGET_UCP1020T1) 26 27 #define CONFIG_UCP1020_REV_1_3 28 29 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" 30 31 #define CONFIG_TSEC_ENET 32 #define CONFIG_TSEC1 33 #define CONFIG_TSEC3 34 #define CONFIG_HAS_ETH0 35 #define CONFIG_HAS_ETH1 36 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF 37 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE 38 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD 39 #define CONFIG_IPADDR 10.80.41.229 40 #define CONFIG_SERVERIP 10.80.41.227 41 #define CONFIG_NETMASK 255.255.252.0 42 #define CONFIG_ETHPRIME "eTSEC3" 43 44 #ifndef CONFIG_SPI_FLASH 45 #endif 46 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 47 48 #define CONFIG_SYS_L2_SIZE (256 << 10) 49 50 #define CONFIG_LAST_STAGE_INIT 51 52 #endif 53 54 #if defined(CONFIG_TARGET_UCP1020) 55 56 #define CONFIG_UCP1020 57 #define CONFIG_UCP1020_REV_1_3 58 59 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" 60 61 #define CONFIG_TSEC_ENET 62 #define CONFIG_TSEC1 63 #define CONFIG_TSEC2 64 #define CONFIG_TSEC3 65 #define CONFIG_HAS_ETH0 66 #define CONFIG_HAS_ETH1 67 #define CONFIG_HAS_ETH2 68 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF 69 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE 70 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD 71 #define CONFIG_IPADDR 192.168.1.81 72 #define CONFIG_IPADDR1 192.168.1.82 73 #define CONFIG_IPADDR2 192.168.1.83 74 #define CONFIG_SERVERIP 192.168.1.80 75 #define CONFIG_GATEWAYIP 102.168.1.1 76 #define CONFIG_NETMASK 255.255.255.0 77 #define CONFIG_ETHPRIME "eTSEC1" 78 79 #ifndef CONFIG_SPI_FLASH 80 #endif 81 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 82 83 #define CONFIG_SYS_L2_SIZE (256 << 10) 84 85 #define CONFIG_LAST_STAGE_INIT 86 87 #endif 88 89 #ifdef CONFIG_SDCARD 90 #define CONFIG_RAMBOOT_SDCARD 91 #define CONFIG_SYS_RAMBOOT 92 #define CONFIG_SYS_EXTRA_ENV_RELOC 93 #define CONFIG_SYS_TEXT_BASE 0x11000000 94 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 95 #endif 96 97 #ifdef CONFIG_SPIFLASH 98 #define CONFIG_RAMBOOT_SPIFLASH 99 #define CONFIG_SYS_RAMBOOT 100 #define CONFIG_SYS_EXTRA_ENV_RELOC 101 #define CONFIG_SYS_TEXT_BASE 0x11000000 102 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 103 #endif 104 105 #ifndef CONFIG_SYS_TEXT_BASE 106 #define CONFIG_SYS_TEXT_BASE 0xeff80000 107 #endif 108 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000 109 110 #ifndef CONFIG_RESET_VECTOR_ADDRESS 111 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 112 #endif 113 114 #ifndef CONFIG_SYS_MONITOR_BASE 115 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 116 #endif 117 118 #define CONFIG_MP 119 120 #define CONFIG_ENV_OVERWRITE 121 122 #define CONFIG_CMD_SATA 123 #define CONFIG_SATA_SIL 124 #define CONFIG_SYS_SATA_MAX_DEVICE 2 125 #define CONFIG_LIBATA 126 #define CONFIG_LBA48 127 128 #define CONFIG_SYS_CLK_FREQ 66666666 129 #define CONFIG_DDR_CLK_FREQ 66666666 130 131 #define CONFIG_HWCONFIG 132 133 #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ 134 #define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */ 135 #define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */ 136 /* 137 * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details). 138 * there will be one entry in this array for each two (dummy) sensors in 139 * CONFIG_DTT_SENSORS. 140 * 141 * For uCP1020 module: 142 * - only one ADM1021/NCT72 143 * - i2c addr 0x41 144 * - conversion rate 0x02 = 0.25 conversions/second 145 * - ALERT output disabled 146 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg 147 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg 148 */ 149 #define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, \ 150 0x02, 0, 1, 0, 85, 1, 0, 85} } 151 152 #define CONFIG_CMD_DTT 153 154 /* 155 * These can be toggled for performance analysis, otherwise use default. 156 */ 157 #define CONFIG_L2_CACHE 158 #define CONFIG_BTB 159 160 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 161 162 #define CONFIG_ENABLE_36BIT_PHYS 163 164 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 165 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 166 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 167 168 #define CONFIG_SYS_CCSRBAR 0xffe00000 169 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 170 171 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 172 SPL code*/ 173 #ifdef CONFIG_SPL_BUILD 174 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 175 #endif 176 177 /* DDR Setup */ 178 #define CONFIG_DDR_ECC_ENABLE 179 #ifndef CONFIG_DDR_ECC_ENABLE 180 #define CONFIG_SYS_DDR_RAW_TIMING 181 #define CONFIG_DDR_SPD 182 #endif 183 #define CONFIG_SYS_SPD_BUS_NUM 1 184 #undef CONFIG_FSL_DDR_INTERACTIVE 185 186 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 187 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 188 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 189 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 190 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 191 192 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 193 194 /* Default settings for DDR3 */ 195 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 196 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 197 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 198 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 199 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 200 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 201 202 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 203 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 204 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 205 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 206 207 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 208 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 209 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 210 #define CONFIG_SYS_DDR_RCW_1 0x00000000 211 #define CONFIG_SYS_DDR_RCW_2 0x00000000 212 #ifdef CONFIG_DDR_ECC_ENABLE 213 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */ 214 #else 215 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 216 #endif 217 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 218 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 219 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 220 221 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 222 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 223 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 224 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 225 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 226 #define CONFIG_SYS_DDR_MODE_1 0x40461520 227 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 228 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 229 230 #undef CONFIG_CLOCKS_IN_MHZ 231 232 /* 233 * Memory map 234 * 235 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 236 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2) 237 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 238 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable 239 * (early boot only) 240 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 241 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 242 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 243 */ 244 245 /* 246 * Local Bus Definitions 247 */ 248 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 249 #define CONFIG_SYS_FLASH_BASE 0xec000000 250 251 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 252 253 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 254 | BR_PS_16 | BR_V) 255 256 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 257 258 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 259 #define CONFIG_SYS_FLASH_QUIET_TEST 260 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 261 262 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 263 264 #undef CONFIG_SYS_FLASH_CHECKSUM 265 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 266 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 267 268 #define CONFIG_FLASH_CFI_DRIVER 269 #define CONFIG_SYS_FLASH_CFI 270 #define CONFIG_SYS_FLASH_EMPTY_INFO 271 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 272 273 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 274 275 #define CONFIG_SYS_INIT_RAM_LOCK 276 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 277 /* Initial L1 address */ 278 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 279 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 280 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 281 /* Size of used area in RAM */ 282 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 283 284 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 285 GENERATED_GBL_DATA_SIZE) 286 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 287 288 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ 289 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 290 291 #define CONFIG_SYS_PMC_BASE 0xff980000 292 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 293 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 294 BR_PS_8 | BR_V) 295 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 296 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 297 OR_GPCM_EAD) 298 299 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 300 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 301 #ifdef CONFIG_NAND_FSL_ELBC 302 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 303 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 304 #endif 305 306 /* Serial Port - controlled on board with jumper J8 307 * open - index 2 308 * shorted - index 1 309 */ 310 #define CONFIG_CONS_INDEX 1 311 #undef CONFIG_SERIAL_SOFTWARE_FIFO 312 #define CONFIG_SYS_NS16550_SERIAL 313 #define CONFIG_SYS_NS16550_REG_SIZE 1 314 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 315 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 316 #define CONFIG_NS16550_MIN_FUNCTIONS 317 #endif 318 319 #define CONFIG_SYS_BAUDRATE_TABLE \ 320 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 321 322 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 323 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 324 325 /* I2C */ 326 #define CONFIG_SYS_I2C 327 #define CONFIG_SYS_I2C_FSL 328 #define CONFIG_SYS_FSL_I2C_SPEED 400000 329 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 330 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 331 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 332 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 333 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 334 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 335 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 336 337 #define CONFIG_RTC_DS1337 338 #define CONFIG_SYS_RTC_DS1337_NOOSC 339 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 340 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 341 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C 342 #define CONFIG_SYS_I2C_IDT6V49205B 0x69 343 344 /* 345 * eSPI - Enhanced SPI 346 */ 347 #define CONFIG_HARD_SPI 348 349 #define CONFIG_SF_DEFAULT_SPEED 10000000 350 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 351 352 #if defined(CONFIG_PCI) 353 /* 354 * General PCI 355 * Memory space is mapped 1-1, but I/O space must start from 0. 356 */ 357 358 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 359 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9" 360 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 361 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 362 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 363 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 364 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 365 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 366 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 367 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 368 369 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 370 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10" 371 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 372 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 373 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 374 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 375 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 376 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 377 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 378 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 379 380 #define CONFIG_CMD_PCI 381 382 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 383 #define CONFIG_DOS_PARTITION 384 #endif /* CONFIG_PCI */ 385 386 /* 387 * Environment 388 */ 389 #ifdef CONFIG_ENV_FIT_UCBOOT 390 391 #define CONFIG_ENV_IS_IN_FLASH 392 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000) 393 #define CONFIG_ENV_SIZE 0x20000 394 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 395 396 #else 397 398 #define CONFIG_ENV_SPI_BUS 0 399 #define CONFIG_ENV_SPI_CS 0 400 #define CONFIG_ENV_SPI_MAX_HZ 10000000 401 #define CONFIG_ENV_SPI_MODE 0 402 403 #ifdef CONFIG_RAMBOOT_SPIFLASH 404 405 #define CONFIG_ENV_IS_IN_SPI_FLASH 406 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */ 407 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */ 408 #define CONFIG_ENV_SECT_SIZE 0x1000 409 410 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 411 /* Address and size of Redundant Environment Sector */ 412 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 413 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 414 #endif 415 416 #elif defined(CONFIG_RAMBOOT_SDCARD) 417 #define CONFIG_ENV_IS_IN_MMC 418 #define CONFIG_FSL_FIXED_MMC_LOCATION 419 #define CONFIG_ENV_SIZE 0x2000 420 #define CONFIG_SYS_MMC_ENV_DEV 0 421 422 #elif defined(CONFIG_SYS_RAMBOOT) 423 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 424 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 425 #define CONFIG_ENV_SIZE 0x2000 426 427 #else 428 #define CONFIG_ENV_IS_IN_FLASH 429 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE) 430 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 431 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 432 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000) 433 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 434 /* Address and size of Redundant Environment Sector */ 435 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 436 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 437 #endif 438 439 #endif 440 441 #endif /* CONFIG_ENV_FIT_UCBOOT */ 442 443 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 444 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 445 446 /* 447 * Command line configuration. 448 */ 449 #define CONFIG_CMD_IRQ 450 #define CONFIG_CMD_DATE 451 #define CONFIG_CMD_IRQ 452 #define CONFIG_CMD_REGINFO 453 #define CONFIG_CMD_ERRATA 454 #define CONFIG_CMD_CRAMFS 455 456 /* 457 * USB 458 */ 459 #define CONFIG_HAS_FSL_DR_USB 460 461 #if defined(CONFIG_HAS_FSL_DR_USB) 462 #define CONFIG_USB_EHCI 463 464 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 465 466 #ifdef CONFIG_USB_EHCI 467 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 468 #define CONFIG_USB_EHCI_FSL 469 #endif 470 #endif 471 472 #undef CONFIG_WATCHDOG /* watchdog disabled */ 473 474 #ifdef CONFIG_MMC 475 #define CONFIG_FSL_ESDHC 476 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 477 #define CONFIG_MMC_SPI 478 #define CONFIG_CMD_MMC_SPI 479 #define CONFIG_GENERIC_MMC 480 #endif 481 482 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA) 483 #define CONFIG_DOS_PARTITION 484 #endif 485 486 /* Misc Extra Settings */ 487 #undef CONFIG_WATCHDOG /* watchdog disabled */ 488 489 /* 490 * Miscellaneous configurable options 491 */ 492 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 493 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 494 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 495 #if defined(CONFIG_CMD_KGDB) 496 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 497 #else 498 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 499 #endif 500 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 501 /* Print Buffer Size */ 502 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 503 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 504 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ 505 506 /* 507 * For booting Linux, the board info and command line data 508 * have to be in the first 64 MB of memory, since this is 509 * the maximum mapped by the Linux kernel during initialization. 510 */ 511 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 512 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 513 514 #if defined(CONFIG_CMD_KGDB) 515 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 516 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 517 #endif 518 519 /* 520 * Environment Configuration 521 */ 522 523 #if defined(CONFIG_TSEC_ENET) 524 525 #if defined(CONFIG_UCP1020_REV_1_2) 526 #define CONFIG_PHY_MICREL_KSZ9021 527 #elif defined(CONFIG_UCP1020_REV_1_3) 528 #define CONFIG_PHY_MICREL_KSZ9031 529 #else 530 #error "UCP1020 module revision is not defined !!!" 531 #endif 532 533 #define CONFIG_BOOTP_SERVERIP 534 535 #define CONFIG_MII /* MII PHY management */ 536 #define CONFIG_TSEC1_NAME "eTSEC1" 537 #define CONFIG_TSEC2_NAME "eTSEC2" 538 #define CONFIG_TSEC3_NAME "eTSEC3" 539 540 #define TSEC1_PHY_ADDR 4 541 #define TSEC2_PHY_ADDR 0 542 #define TSEC2_PHY_ADDR_SGMII 0x00 543 #define TSEC3_PHY_ADDR 6 544 545 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 546 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 547 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 548 549 #define TSEC1_PHYIDX 0 550 #define TSEC2_PHYIDX 0 551 #define TSEC3_PHYIDX 0 552 553 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 554 555 #endif 556 557 #define CONFIG_HOSTNAME UCP1020 558 #define CONFIG_ROOTPATH "/opt/nfsroot" 559 #define CONFIG_BOOTFILE "uImage" 560 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 561 562 /* default location for tftp and bootm */ 563 #define CONFIG_LOADADDR 1000000 564 565 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 566 567 #define CONFIG_BAUDRATE 115200 568 569 #if defined(CONFIG_DONGLE) 570 571 #define CONFIG_EXTRA_ENV_SETTINGS \ 572 "bootcmd=run prog_spi_mbrbootcramfs\0" \ 573 "bootfile=uImage\0" \ 574 "consoledev=ttyS0\0" \ 575 "cramfsfile=image.cramfs\0" \ 576 "dtbaddr=0x00c00000\0" \ 577 "dtbfile=image.dtb\0" \ 578 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 579 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 580 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 581 "fileaddr=0x01000000\0" \ 582 "filesize=0x00080000\0" \ 583 "flashmbr=sf probe 0; " \ 584 "tftp $loadaddr $mbr; " \ 585 "sf erase $mbr_offset +$filesize; " \ 586 "sf write $loadaddr $mbr_offset $filesize\0" \ 587 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 588 "protect off $nor_recoveryaddr +$filesize; " \ 589 "erase $nor_recoveryaddr +$filesize; " \ 590 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 591 "protect on $nor_recoveryaddr +$filesize\0 " \ 592 "flashuboot=tftp $ubootaddr $ubootfile; " \ 593 "protect off $nor_ubootaddr +$filesize; " \ 594 "erase $nor_ubootaddr +$filesize; " \ 595 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 596 "protect on $nor_ubootaddr +$filesize\0 " \ 597 "flashworking=tftp $workingaddr $cramfsfile; " \ 598 "protect off $nor_workingaddr +$filesize; " \ 599 "erase $nor_workingaddr +$filesize; " \ 600 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 601 "protect on $nor_workingaddr +$filesize\0 " \ 602 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 603 "kerneladdr=0x01100000\0" \ 604 "kernelfile=uImage\0" \ 605 "loadaddr=0x01000000\0" \ 606 "mbr=uCP1020d.mbr\0" \ 607 "mbr_offset=0x00000000\0" \ 608 "mmbr=uCP1020Quiet.mbr\0" \ 609 "mmcpart=0:2\0" \ 610 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 611 "mmc erase 1 1; " \ 612 "mmc write $loadaddr 1 1\0" \ 613 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \ 614 "mmc erase 0x40 0x400; " \ 615 "mmc write $loadaddr 0x40 0x400\0" \ 616 "netdev=eth0\0" \ 617 "nor_recoveryaddr=0xEC0A0000\0" \ 618 "nor_ubootaddr=0xEFF80000\0" \ 619 "nor_workingaddr=0xECFA0000\0" \ 620 "norbootrecovery=setenv bootargs $recoverybootargs" \ 621 " console=$consoledev,$baudrate $othbootargs; " \ 622 "run norloadrecovery; " \ 623 "bootm $kerneladdr - $dtbaddr\0" \ 624 "norbootworking=setenv bootargs $workingbootargs" \ 625 " console=$consoledev,$baudrate $othbootargs; " \ 626 "run norloadworking; " \ 627 "bootm $kerneladdr - $dtbaddr\0" \ 628 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 629 "setenv cramfsaddr $nor_recoveryaddr; " \ 630 "cramfsload $dtbaddr $dtbfile; " \ 631 "cramfsload $kerneladdr $kernelfile\0" \ 632 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 633 "setenv cramfsaddr $nor_workingaddr; " \ 634 "cramfsload $dtbaddr $dtbfile; " \ 635 "cramfsload $kerneladdr $kernelfile\0" \ 636 "prog_spi_mbr=run spi__mbr\0" \ 637 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \ 638 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \ 639 "run spi__cramfs\0" \ 640 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 641 " console=$consoledev,$baudrate $othbootargs; " \ 642 "tftp $rootfsaddr $rootfsfile; " \ 643 "tftp $loadaddr $kernelfile; " \ 644 "tftp $dtbaddr $dtbfile; " \ 645 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 646 "ramdisk_size=120000\0" \ 647 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 648 "recoveryaddr=0x02F00000\0" \ 649 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 650 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 651 "mw.l 0xffe0f008 0x00400000\0" \ 652 "rootfsaddr=0x02F00000\0" \ 653 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 654 "rootpath=/opt/nfsroot\0" \ 655 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 656 "protect off 0xeC000000 +$filesize; " \ 657 "erase 0xEC000000 +$filesize; " \ 658 "cp.b $loadaddr 0xEC000000 $filesize; " \ 659 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 660 "protect on 0xeC000000 +$filesize\0" \ 661 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 662 "protect off 0xeFF80000 +$filesize; " \ 663 "erase 0xEFF80000 +$filesize; " \ 664 "cp.b $loadaddr 0xEFF80000 $filesize; " \ 665 "cmp.b $loadaddr 0xEFF80000 $filesize; " \ 666 "protect on 0xeFF80000 +$filesize\0" \ 667 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \ 668 "sf probe 0; sf erase 0x8000 +$filesize; " \ 669 "sf write $loadaddr 0x8000 $filesize\0" \ 670 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \ 671 "protect off 0xec0a0000 +$filesize; " \ 672 "erase 0xeC0A0000 +$filesize; " \ 673 "cp.b $loadaddr 0xeC0A0000 $filesize; " \ 674 "protect on 0xec0a0000 +$filesize\0" \ 675 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 676 "sf probe 1; sf erase 0 +$filesize; " \ 677 "sf write $loadaddr 0 $filesize\0" \ 678 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 679 "sf probe 0; sf erase 0 +$filesize; " \ 680 "sf write $loadaddr 0 $filesize\0" \ 681 "tftpflash=tftpboot $loadaddr $uboot; " \ 682 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 683 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 684 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 685 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 686 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 687 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 688 "ubootaddr=0x01000000\0" \ 689 "ubootfile=u-boot.bin\0" \ 690 "ubootd=u-boot4dongle.bin\0" \ 691 "upgrade=run flashworking\0" \ 692 "usb_phy_type=ulpi\0 " \ 693 "workingaddr=0x02F00000\0" \ 694 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 695 696 #else 697 698 #if defined(CONFIG_UCP1020T1) 699 700 #define CONFIG_EXTRA_ENV_SETTINGS \ 701 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ 702 "bootfile=uImage\0" \ 703 "consoledev=ttyS0\0" \ 704 "cramfsfile=image.cramfs\0" \ 705 "dtbaddr=0x00c00000\0" \ 706 "dtbfile=image.dtb\0" \ 707 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 708 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 709 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 710 "fileaddr=0x01000000\0" \ 711 "filesize=0x00080000\0" \ 712 "flashmbr=sf probe 0; " \ 713 "tftp $loadaddr $mbr; " \ 714 "sf erase $mbr_offset +$filesize; " \ 715 "sf write $loadaddr $mbr_offset $filesize\0" \ 716 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 717 "protect off $nor_recoveryaddr +$filesize; " \ 718 "erase $nor_recoveryaddr +$filesize; " \ 719 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 720 "protect on $nor_recoveryaddr +$filesize\0 " \ 721 "flashuboot=tftp $ubootaddr $ubootfile; " \ 722 "protect off $nor_ubootaddr +$filesize; " \ 723 "erase $nor_ubootaddr +$filesize; " \ 724 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 725 "protect on $nor_ubootaddr +$filesize\0 " \ 726 "flashworking=tftp $workingaddr $cramfsfile; " \ 727 "protect off $nor_workingaddr +$filesize; " \ 728 "erase $nor_workingaddr +$filesize; " \ 729 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 730 "protect on $nor_workingaddr +$filesize\0 " \ 731 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 732 "kerneladdr=0x01100000\0" \ 733 "kernelfile=uImage\0" \ 734 "loadaddr=0x01000000\0" \ 735 "mbr=uCP1020.mbr\0" \ 736 "mbr_offset=0x00000000\0" \ 737 "netdev=eth0\0" \ 738 "nor_recoveryaddr=0xEC0A0000\0" \ 739 "nor_ubootaddr=0xEFF80000\0" \ 740 "nor_workingaddr=0xECFA0000\0" \ 741 "norbootrecovery=setenv bootargs $recoverybootargs" \ 742 " console=$consoledev,$baudrate $othbootargs; " \ 743 "run norloadrecovery; " \ 744 "bootm $kerneladdr - $dtbaddr\0" \ 745 "norbootworking=setenv bootargs $workingbootargs" \ 746 " console=$consoledev,$baudrate $othbootargs; " \ 747 "run norloadworking; " \ 748 "bootm $kerneladdr - $dtbaddr\0" \ 749 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 750 "setenv cramfsaddr $nor_recoveryaddr; " \ 751 "cramfsload $dtbaddr $dtbfile; " \ 752 "cramfsload $kerneladdr $kernelfile\0" \ 753 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 754 "setenv cramfsaddr $nor_workingaddr; " \ 755 "cramfsload $dtbaddr $dtbfile; " \ 756 "cramfsload $kerneladdr $kernelfile\0" \ 757 "othbootargs=quiet\0" \ 758 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 759 " console=$consoledev,$baudrate $othbootargs; " \ 760 "tftp $rootfsaddr $rootfsfile; " \ 761 "tftp $loadaddr $kernelfile; " \ 762 "tftp $dtbaddr $dtbfile; " \ 763 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 764 "ramdisk_size=120000\0" \ 765 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 766 "recoveryaddr=0x02F00000\0" \ 767 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 768 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 769 "mw.l 0xffe0f008 0x00400000\0" \ 770 "rootfsaddr=0x02F00000\0" \ 771 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 772 "rootpath=/opt/nfsroot\0" \ 773 "silent=1\0" \ 774 "tftpflash=tftpboot $loadaddr $uboot; " \ 775 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 776 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 777 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 778 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 779 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 780 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 781 "ubootaddr=0x01000000\0" \ 782 "ubootfile=u-boot.bin\0" \ 783 "upgrade=run flashworking\0" \ 784 "workingaddr=0x02F00000\0" \ 785 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 786 787 #else /* For Arcturus Modules */ 788 789 #define CONFIG_EXTRA_ENV_SETTINGS \ 790 "bootcmd=run norkernel\0" \ 791 "bootfile=uImage\0" \ 792 "consoledev=ttyS0\0" \ 793 "dtbaddr=0x00c00000\0" \ 794 "dtbfile=image.dtb\0" \ 795 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 796 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 797 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 798 "fileaddr=0x01000000\0" \ 799 "filesize=0x00080000\0" \ 800 "flashmbr=sf probe 0; " \ 801 "tftp $loadaddr $mbr; " \ 802 "sf erase $mbr_offset +$filesize; " \ 803 "sf write $loadaddr $mbr_offset $filesize\0" \ 804 "flashuboot=tftp $loadaddr $ubootfile; " \ 805 "protect off $nor_ubootaddr0 +$filesize; " \ 806 "erase $nor_ubootaddr0 +$filesize; " \ 807 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \ 808 "protect on $nor_ubootaddr0 +$filesize; " \ 809 "protect off $nor_ubootaddr1 +$filesize; " \ 810 "erase $nor_ubootaddr1 +$filesize; " \ 811 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \ 812 "protect on $nor_ubootaddr1 +$filesize\0 " \ 813 "format0=protect off $part0base +$part0size; " \ 814 "erase $part0base +$part0size\0" \ 815 "format1=protect off $part1base +$part1size; " \ 816 "erase $part1base +$part1size\0" \ 817 "format2=protect off $part2base +$part2size; " \ 818 "erase $part2base +$part2size\0" \ 819 "format3=protect off $part3base +$part3size; " \ 820 "erase $part3base +$part3size\0" \ 821 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 822 "kerneladdr=0x01100000\0" \ 823 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \ 824 "kernelfile=uImage\0" \ 825 "loadaddr=0x01000000\0" \ 826 "mbr=uCP1020.mbr\0" \ 827 "mbr_offset=0x00000000\0" \ 828 "netdev=eth0\0" \ 829 "nor_ubootaddr0=0xEC000000\0" \ 830 "nor_ubootaddr1=0xEFF80000\0" \ 831 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \ 832 "run norkernelload; " \ 833 "bootm $kerneladdr - $dtbaddr\0" \ 834 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \ 835 "setenv cramfsaddr $part0base; " \ 836 "cramfsload $dtbaddr $dtbfile; " \ 837 "cramfsload $kerneladdr $kernelfile\0" \ 838 "part0base=0xEC100000\0" \ 839 "part0size=0x00700000\0" \ 840 "part1base=0xEC800000\0" \ 841 "part1size=0x02000000\0" \ 842 "part2base=0xEE800000\0" \ 843 "part2size=0x00800000\0" \ 844 "part3base=0xEF000000\0" \ 845 "part3size=0x00F80000\0" \ 846 "partENVbase=0xEC080000\0" \ 847 "partENVsize=0x00080000\0" \ 848 "program0=tftp part0-000000.bin; " \ 849 "protect off $part0base +$filesize; " \ 850 "erase $part0base +$filesize; " \ 851 "cp.b $loadaddr $part0base $filesize; " \ 852 "echo Verifying...; " \ 853 "cmp.b $loadaddr $part0base $filesize\0" \ 854 "program1=tftp part1-000000.bin; " \ 855 "protect off $part1base +$filesize; " \ 856 "erase $part1base +$filesize; " \ 857 "cp.b $loadaddr $part1base $filesize; " \ 858 "echo Verifying...; " \ 859 "cmp.b $loadaddr $part1base $filesize\0" \ 860 "program2=tftp part2-000000.bin; " \ 861 "protect off $part2base +$filesize; " \ 862 "erase $part2base +$filesize; " \ 863 "cp.b $loadaddr $part2base $filesize; " \ 864 "echo Verifying...; " \ 865 "cmp.b $loadaddr $part2base $filesize\0" \ 866 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 867 " console=$consoledev,$baudrate $othbootargs; " \ 868 "tftp $rootfsaddr $rootfsfile; " \ 869 "tftp $loadaddr $kernelfile; " \ 870 "tftp $dtbaddr $dtbfile; " \ 871 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 872 "ramdisk_size=120000\0" \ 873 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 874 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 875 "mw.l 0xffe0f008 0x00400000\0" \ 876 "rootfsaddr=0x02F00000\0" \ 877 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 878 "rootpath=/opt/nfsroot\0" \ 879 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 880 "sf probe 0; sf erase 0 +$filesize; " \ 881 "sf write $loadaddr 0 $filesize\0" \ 882 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 883 "protect off 0xeC000000 +$filesize; " \ 884 "erase 0xEC000000 +$filesize; " \ 885 "cp.b $loadaddr 0xEC000000 $filesize; " \ 886 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 887 "protect on 0xeC000000 +$filesize\0" \ 888 "tftpflash=tftpboot $loadaddr $uboot; " \ 889 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 890 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 891 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 892 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 893 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 894 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 895 "ubootfile=u-boot.bin\0" \ 896 "upgrade=run flashuboot\0" \ 897 "usb_phy_type=ulpi\0 " \ 898 "boot_nfs= " \ 899 "setenv bootargs root=/dev/nfs rw " \ 900 "nfsroot=$serverip:$rootpath " \ 901 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 902 "console=$consoledev,$baudrate $othbootargs;" \ 903 "tftp $loadaddr $bootfile;" \ 904 "tftp $fdtaddr $fdtfile;" \ 905 "bootm $loadaddr - $fdtaddr\0" \ 906 "boot_hd = " \ 907 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 908 "console=$consoledev,$baudrate $othbootargs;" \ 909 "usb start;" \ 910 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 911 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 912 "bootm $loadaddr - $fdtaddr\0" \ 913 "boot_usb_fat = " \ 914 "setenv bootargs root=/dev/ram rw " \ 915 "console=$consoledev,$baudrate $othbootargs " \ 916 "ramdisk_size=$ramdisk_size;" \ 917 "usb start;" \ 918 "fatload usb 0:2 $loadaddr $bootfile;" \ 919 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 920 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 921 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 922 "boot_usb_ext2 = " \ 923 "setenv bootargs root=/dev/ram rw " \ 924 "console=$consoledev,$baudrate $othbootargs " \ 925 "ramdisk_size=$ramdisk_size;" \ 926 "usb start;" \ 927 "ext2load usb 0:4 $loadaddr $bootfile;" \ 928 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 929 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 930 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 931 "boot_nor = " \ 932 "setenv bootargs root=/dev/$jffs2nor rw " \ 933 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 934 "bootm $norbootaddr - $norfdtaddr\0 " \ 935 "boot_ram = " \ 936 "setenv bootargs root=/dev/ram rw " \ 937 "console=$consoledev,$baudrate $othbootargs " \ 938 "ramdisk_size=$ramdisk_size;" \ 939 "tftp $ramdiskaddr $ramdiskfile;" \ 940 "tftp $loadaddr $bootfile;" \ 941 "tftp $fdtaddr $fdtfile;" \ 942 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" 943 944 #endif 945 #endif 946 947 #endif /* __CONFIG_H */ 948