1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013-2015 Arcturus Networks, Inc. 4 * http://www.arcturusnetworks.com/products/ucp1020/ 5 * based on include/configs/p1_p2_rdb_pc.h 6 * original copyright follows: 7 * Copyright 2009-2011 Freescale Semiconductor, Inc. 8 */ 9 10 /* 11 * QorIQ uCP1020-xx boards configuration file 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 17 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 18 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 19 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 20 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 21 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 22 23 #if defined(CONFIG_TARTGET_UCP1020T1) 24 25 #define CONFIG_UCP1020_REV_1_3 26 27 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" 28 29 #define CONFIG_TSEC1 30 #define CONFIG_TSEC3 31 #define CONFIG_HAS_ETH0 32 #define CONFIG_HAS_ETH1 33 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF 34 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE 35 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD 36 #define CONFIG_IPADDR 10.80.41.229 37 #define CONFIG_SERVERIP 10.80.41.227 38 #define CONFIG_NETMASK 255.255.252.0 39 #define CONFIG_ETHPRIME "eTSEC3" 40 41 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 42 43 #define CONFIG_SYS_L2_SIZE (256 << 10) 44 45 #endif 46 47 #if defined(CONFIG_TARGET_UCP1020) 48 49 #define CONFIG_UCP1020 50 #define CONFIG_UCP1020_REV_1_3 51 52 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" 53 54 #define CONFIG_TSEC1 55 #define CONFIG_TSEC2 56 #define CONFIG_TSEC3 57 #define CONFIG_HAS_ETH0 58 #define CONFIG_HAS_ETH1 59 #define CONFIG_HAS_ETH2 60 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF 61 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE 62 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD 63 #define CONFIG_IPADDR 192.168.1.81 64 #define CONFIG_IPADDR1 192.168.1.82 65 #define CONFIG_IPADDR2 192.168.1.83 66 #define CONFIG_SERVERIP 192.168.1.80 67 #define CONFIG_GATEWAYIP 102.168.1.1 68 #define CONFIG_NETMASK 255.255.255.0 69 #define CONFIG_ETHPRIME "eTSEC1" 70 71 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 72 73 #define CONFIG_SYS_L2_SIZE (256 << 10) 74 75 #endif 76 77 #ifdef CONFIG_SDCARD 78 #define CONFIG_RAMBOOT_SDCARD 79 #define CONFIG_SYS_RAMBOOT 80 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 81 #endif 82 83 #ifdef CONFIG_SPIFLASH 84 #define CONFIG_RAMBOOT_SPIFLASH 85 #define CONFIG_SYS_RAMBOOT 86 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 87 #endif 88 89 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000 90 91 #ifndef CONFIG_RESET_VECTOR_ADDRESS 92 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 93 #endif 94 95 #ifndef CONFIG_SYS_MONITOR_BASE 96 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 97 #endif 98 99 #define CONFIG_ENV_OVERWRITE 100 101 #define CONFIG_SYS_SATA_MAX_DEVICE 2 102 #define CONFIG_LBA48 103 104 #define CONFIG_SYS_CLK_FREQ 66666666 105 #define CONFIG_DDR_CLK_FREQ 66666666 106 107 #define CONFIG_HWCONFIG 108 109 /* 110 * These can be toggled for performance analysis, otherwise use default. 111 */ 112 #define CONFIG_L2_CACHE 113 #define CONFIG_BTB 114 115 #define CONFIG_ENABLE_36BIT_PHYS 116 117 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 118 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 119 120 #define CONFIG_SYS_CCSRBAR 0xffe00000 121 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 122 123 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 124 SPL code*/ 125 #ifdef CONFIG_SPL_BUILD 126 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 127 #endif 128 129 /* DDR Setup */ 130 #define CONFIG_DDR_ECC_ENABLE 131 #ifndef CONFIG_DDR_ECC_ENABLE 132 #define CONFIG_SYS_DDR_RAW_TIMING 133 #define CONFIG_DDR_SPD 134 #endif 135 #define CONFIG_SYS_SPD_BUS_NUM 1 136 137 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 138 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 139 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 140 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 141 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 142 143 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 144 145 /* Default settings for DDR3 */ 146 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 147 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 148 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 149 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 150 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 151 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 152 153 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 154 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 155 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 156 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 157 158 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 159 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 160 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 161 #define CONFIG_SYS_DDR_RCW_1 0x00000000 162 #define CONFIG_SYS_DDR_RCW_2 0x00000000 163 #ifdef CONFIG_DDR_ECC_ENABLE 164 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */ 165 #else 166 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 167 #endif 168 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 169 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 170 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 171 172 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 173 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 174 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 175 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 176 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 177 #define CONFIG_SYS_DDR_MODE_1 0x40461520 178 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 179 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 180 181 #undef CONFIG_CLOCKS_IN_MHZ 182 183 /* 184 * Memory map 185 * 186 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 187 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2) 188 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 189 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable 190 * (early boot only) 191 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 192 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 193 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 194 */ 195 196 /* 197 * Local Bus Definitions 198 */ 199 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 200 #define CONFIG_SYS_FLASH_BASE 0xec000000 201 202 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 203 204 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 205 | BR_PS_16 | BR_V) 206 207 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 208 209 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 210 #define CONFIG_SYS_FLASH_QUIET_TEST 211 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 212 213 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 214 215 #undef CONFIG_SYS_FLASH_CHECKSUM 216 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 217 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 218 219 #define CONFIG_SYS_FLASH_EMPTY_INFO 220 221 #define CONFIG_SYS_INIT_RAM_LOCK 222 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 223 /* Initial L1 address */ 224 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 225 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 226 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 227 /* Size of used area in RAM */ 228 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 229 230 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 231 GENERATED_GBL_DATA_SIZE) 232 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 233 234 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ 235 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 236 237 #define CONFIG_SYS_PMC_BASE 0xff980000 238 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 239 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 240 BR_PS_8 | BR_V) 241 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 242 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 243 OR_GPCM_EAD) 244 245 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 246 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 247 #ifdef CONFIG_NAND_FSL_ELBC 248 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 249 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 250 #endif 251 252 /* Serial Port - controlled on board with jumper J8 253 * open - index 2 254 * shorted - index 1 255 */ 256 #undef CONFIG_SERIAL_SOFTWARE_FIFO 257 #define CONFIG_SYS_NS16550_SERIAL 258 #define CONFIG_SYS_NS16550_REG_SIZE 1 259 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 260 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 261 #define CONFIG_NS16550_MIN_FUNCTIONS 262 #endif 263 264 #define CONFIG_SYS_BAUDRATE_TABLE \ 265 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 266 267 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 268 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 269 270 /* I2C */ 271 #define CONFIG_SYS_I2C 272 #define CONFIG_SYS_I2C_FSL 273 #define CONFIG_SYS_FSL_I2C_SPEED 400000 274 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 275 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 276 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 277 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 278 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 279 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 280 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 281 282 #define CONFIG_RTC_DS1337 283 #define CONFIG_RTC_DS1337_NOOSC 284 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 285 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 286 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C 287 #define CONFIG_SYS_I2C_IDT6V49205B 0x69 288 289 #if defined(CONFIG_PCI) 290 /* 291 * General PCI 292 * Memory space is mapped 1-1, but I/O space must start from 0. 293 */ 294 295 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 296 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9" 297 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 298 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 299 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 300 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 301 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 302 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 303 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 304 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 305 306 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 307 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10" 308 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 309 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 310 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 311 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 312 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 313 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 314 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 315 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 316 317 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 318 #endif /* CONFIG_PCI */ 319 320 /* 321 * Environment 322 */ 323 #ifdef CONFIG_ENV_FIT_UCBOOT 324 325 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000) 326 #define CONFIG_ENV_SIZE 0x20000 327 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 328 329 #else 330 331 #define CONFIG_ENV_SPI_BUS 0 332 #define CONFIG_ENV_SPI_CS 0 333 #define CONFIG_ENV_SPI_MAX_HZ 10000000 334 #define CONFIG_ENV_SPI_MODE 0 335 336 #ifdef CONFIG_RAMBOOT_SPIFLASH 337 338 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */ 339 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */ 340 #define CONFIG_ENV_SECT_SIZE 0x1000 341 342 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 343 /* Address and size of Redundant Environment Sector */ 344 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 345 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 346 #endif 347 348 #elif defined(CONFIG_RAMBOOT_SDCARD) 349 #define CONFIG_FSL_FIXED_MMC_LOCATION 350 #define CONFIG_ENV_SIZE 0x2000 351 #define CONFIG_SYS_MMC_ENV_DEV 0 352 353 #elif defined(CONFIG_SYS_RAMBOOT) 354 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 355 #define CONFIG_ENV_SIZE 0x2000 356 357 #else 358 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE) 359 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 360 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 361 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000) 362 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 363 /* Address and size of Redundant Environment Sector */ 364 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 365 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 366 #endif 367 368 #endif 369 370 #endif /* CONFIG_ENV_FIT_UCBOOT */ 371 372 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 373 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 374 375 /* 376 * USB 377 */ 378 #define CONFIG_HAS_FSL_DR_USB 379 380 #if defined(CONFIG_HAS_FSL_DR_USB) 381 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 382 383 #ifdef CONFIG_USB_EHCI_HCD 384 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 385 #define CONFIG_USB_EHCI_FSL 386 #endif 387 #endif 388 389 #undef CONFIG_WATCHDOG /* watchdog disabled */ 390 391 #ifdef CONFIG_MMC 392 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 393 #define CONFIG_MMC_SPI 394 #endif 395 396 /* Misc Extra Settings */ 397 #undef CONFIG_WATCHDOG /* watchdog disabled */ 398 399 /* 400 * Miscellaneous configurable options 401 */ 402 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 403 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ 404 405 /* 406 * For booting Linux, the board info and command line data 407 * have to be in the first 64 MB of memory, since this is 408 * the maximum mapped by the Linux kernel during initialization. 409 */ 410 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 411 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 412 413 #if defined(CONFIG_CMD_KGDB) 414 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 415 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 416 #endif 417 418 /* 419 * Environment Configuration 420 */ 421 422 #if defined(CONFIG_TSEC_ENET) 423 424 #if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3) 425 #else 426 #error "UCP1020 module revision is not defined !!!" 427 #endif 428 429 #define CONFIG_BOOTP_SERVERIP 430 431 #define CONFIG_TSEC1_NAME "eTSEC1" 432 #define CONFIG_TSEC2_NAME "eTSEC2" 433 #define CONFIG_TSEC3_NAME "eTSEC3" 434 435 #define TSEC1_PHY_ADDR 4 436 #define TSEC2_PHY_ADDR 0 437 #define TSEC2_PHY_ADDR_SGMII 0x00 438 #define TSEC3_PHY_ADDR 6 439 440 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 441 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 442 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 443 444 #define TSEC1_PHYIDX 0 445 #define TSEC2_PHYIDX 0 446 #define TSEC3_PHYIDX 0 447 448 #endif 449 450 #define CONFIG_HOSTNAME "UCP1020" 451 #define CONFIG_ROOTPATH "/opt/nfsroot" 452 #define CONFIG_BOOTFILE "uImage" 453 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 454 455 /* default location for tftp and bootm */ 456 #define CONFIG_LOADADDR 1000000 457 458 #if defined(CONFIG_DONGLE) 459 460 #define CONFIG_EXTRA_ENV_SETTINGS \ 461 "bootcmd=run prog_spi_mbrbootcramfs\0" \ 462 "bootfile=uImage\0" \ 463 "consoledev=ttyS0\0" \ 464 "cramfsfile=image.cramfs\0" \ 465 "dtbaddr=0x00c00000\0" \ 466 "dtbfile=image.dtb\0" \ 467 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 468 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 469 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 470 "fileaddr=0x01000000\0" \ 471 "filesize=0x00080000\0" \ 472 "flashmbr=sf probe 0; " \ 473 "tftp $loadaddr $mbr; " \ 474 "sf erase $mbr_offset +$filesize; " \ 475 "sf write $loadaddr $mbr_offset $filesize\0" \ 476 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 477 "protect off $nor_recoveryaddr +$filesize; " \ 478 "erase $nor_recoveryaddr +$filesize; " \ 479 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 480 "protect on $nor_recoveryaddr +$filesize\0 " \ 481 "flashuboot=tftp $ubootaddr $ubootfile; " \ 482 "protect off $nor_ubootaddr +$filesize; " \ 483 "erase $nor_ubootaddr +$filesize; " \ 484 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 485 "protect on $nor_ubootaddr +$filesize\0 " \ 486 "flashworking=tftp $workingaddr $cramfsfile; " \ 487 "protect off $nor_workingaddr +$filesize; " \ 488 "erase $nor_workingaddr +$filesize; " \ 489 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 490 "protect on $nor_workingaddr +$filesize\0 " \ 491 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 492 "kerneladdr=0x01100000\0" \ 493 "kernelfile=uImage\0" \ 494 "loadaddr=0x01000000\0" \ 495 "mbr=uCP1020d.mbr\0" \ 496 "mbr_offset=0x00000000\0" \ 497 "mmbr=uCP1020Quiet.mbr\0" \ 498 "mmcpart=0:2\0" \ 499 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 500 "mmc erase 1 1; " \ 501 "mmc write $loadaddr 1 1\0" \ 502 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \ 503 "mmc erase 0x40 0x400; " \ 504 "mmc write $loadaddr 0x40 0x400\0" \ 505 "netdev=eth0\0" \ 506 "nor_recoveryaddr=0xEC0A0000\0" \ 507 "nor_ubootaddr=0xEFF80000\0" \ 508 "nor_workingaddr=0xECFA0000\0" \ 509 "norbootrecovery=setenv bootargs $recoverybootargs" \ 510 " console=$consoledev,$baudrate $othbootargs; " \ 511 "run norloadrecovery; " \ 512 "bootm $kerneladdr - $dtbaddr\0" \ 513 "norbootworking=setenv bootargs $workingbootargs" \ 514 " console=$consoledev,$baudrate $othbootargs; " \ 515 "run norloadworking; " \ 516 "bootm $kerneladdr - $dtbaddr\0" \ 517 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 518 "setenv cramfsaddr $nor_recoveryaddr; " \ 519 "cramfsload $dtbaddr $dtbfile; " \ 520 "cramfsload $kerneladdr $kernelfile\0" \ 521 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 522 "setenv cramfsaddr $nor_workingaddr; " \ 523 "cramfsload $dtbaddr $dtbfile; " \ 524 "cramfsload $kerneladdr $kernelfile\0" \ 525 "prog_spi_mbr=run spi__mbr\0" \ 526 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \ 527 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \ 528 "run spi__cramfs\0" \ 529 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 530 " console=$consoledev,$baudrate $othbootargs; " \ 531 "tftp $rootfsaddr $rootfsfile; " \ 532 "tftp $loadaddr $kernelfile; " \ 533 "tftp $dtbaddr $dtbfile; " \ 534 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 535 "ramdisk_size=120000\0" \ 536 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 537 "recoveryaddr=0x02F00000\0" \ 538 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 539 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 540 "mw.l 0xffe0f008 0x00400000\0" \ 541 "rootfsaddr=0x02F00000\0" \ 542 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 543 "rootpath=/opt/nfsroot\0" \ 544 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 545 "protect off 0xeC000000 +$filesize; " \ 546 "erase 0xEC000000 +$filesize; " \ 547 "cp.b $loadaddr 0xEC000000 $filesize; " \ 548 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 549 "protect on 0xeC000000 +$filesize\0" \ 550 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 551 "protect off 0xeFF80000 +$filesize; " \ 552 "erase 0xEFF80000 +$filesize; " \ 553 "cp.b $loadaddr 0xEFF80000 $filesize; " \ 554 "cmp.b $loadaddr 0xEFF80000 $filesize; " \ 555 "protect on 0xeFF80000 +$filesize\0" \ 556 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \ 557 "sf probe 0; sf erase 0x8000 +$filesize; " \ 558 "sf write $loadaddr 0x8000 $filesize\0" \ 559 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \ 560 "protect off 0xec0a0000 +$filesize; " \ 561 "erase 0xeC0A0000 +$filesize; " \ 562 "cp.b $loadaddr 0xeC0A0000 $filesize; " \ 563 "protect on 0xec0a0000 +$filesize\0" \ 564 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 565 "sf probe 1; sf erase 0 +$filesize; " \ 566 "sf write $loadaddr 0 $filesize\0" \ 567 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 568 "sf probe 0; sf erase 0 +$filesize; " \ 569 "sf write $loadaddr 0 $filesize\0" \ 570 "tftpflash=tftpboot $loadaddr $uboot; " \ 571 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 572 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 573 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 574 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 575 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 576 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 577 "ubootaddr=0x01000000\0" \ 578 "ubootfile=u-boot.bin\0" \ 579 "ubootd=u-boot4dongle.bin\0" \ 580 "upgrade=run flashworking\0" \ 581 "usb_phy_type=ulpi\0 " \ 582 "workingaddr=0x02F00000\0" \ 583 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 584 585 #else 586 587 #if defined(CONFIG_UCP1020T1) 588 589 #define CONFIG_EXTRA_ENV_SETTINGS \ 590 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ 591 "bootfile=uImage\0" \ 592 "consoledev=ttyS0\0" \ 593 "cramfsfile=image.cramfs\0" \ 594 "dtbaddr=0x00c00000\0" \ 595 "dtbfile=image.dtb\0" \ 596 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 597 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 598 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 599 "fileaddr=0x01000000\0" \ 600 "filesize=0x00080000\0" \ 601 "flashmbr=sf probe 0; " \ 602 "tftp $loadaddr $mbr; " \ 603 "sf erase $mbr_offset +$filesize; " \ 604 "sf write $loadaddr $mbr_offset $filesize\0" \ 605 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 606 "protect off $nor_recoveryaddr +$filesize; " \ 607 "erase $nor_recoveryaddr +$filesize; " \ 608 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 609 "protect on $nor_recoveryaddr +$filesize\0 " \ 610 "flashuboot=tftp $ubootaddr $ubootfile; " \ 611 "protect off $nor_ubootaddr +$filesize; " \ 612 "erase $nor_ubootaddr +$filesize; " \ 613 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 614 "protect on $nor_ubootaddr +$filesize\0 " \ 615 "flashworking=tftp $workingaddr $cramfsfile; " \ 616 "protect off $nor_workingaddr +$filesize; " \ 617 "erase $nor_workingaddr +$filesize; " \ 618 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 619 "protect on $nor_workingaddr +$filesize\0 " \ 620 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 621 "kerneladdr=0x01100000\0" \ 622 "kernelfile=uImage\0" \ 623 "loadaddr=0x01000000\0" \ 624 "mbr=uCP1020.mbr\0" \ 625 "mbr_offset=0x00000000\0" \ 626 "netdev=eth0\0" \ 627 "nor_recoveryaddr=0xEC0A0000\0" \ 628 "nor_ubootaddr=0xEFF80000\0" \ 629 "nor_workingaddr=0xECFA0000\0" \ 630 "norbootrecovery=setenv bootargs $recoverybootargs" \ 631 " console=$consoledev,$baudrate $othbootargs; " \ 632 "run norloadrecovery; " \ 633 "bootm $kerneladdr - $dtbaddr\0" \ 634 "norbootworking=setenv bootargs $workingbootargs" \ 635 " console=$consoledev,$baudrate $othbootargs; " \ 636 "run norloadworking; " \ 637 "bootm $kerneladdr - $dtbaddr\0" \ 638 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 639 "setenv cramfsaddr $nor_recoveryaddr; " \ 640 "cramfsload $dtbaddr $dtbfile; " \ 641 "cramfsload $kerneladdr $kernelfile\0" \ 642 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 643 "setenv cramfsaddr $nor_workingaddr; " \ 644 "cramfsload $dtbaddr $dtbfile; " \ 645 "cramfsload $kerneladdr $kernelfile\0" \ 646 "othbootargs=quiet\0" \ 647 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 648 " console=$consoledev,$baudrate $othbootargs; " \ 649 "tftp $rootfsaddr $rootfsfile; " \ 650 "tftp $loadaddr $kernelfile; " \ 651 "tftp $dtbaddr $dtbfile; " \ 652 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 653 "ramdisk_size=120000\0" \ 654 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 655 "recoveryaddr=0x02F00000\0" \ 656 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 657 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 658 "mw.l 0xffe0f008 0x00400000\0" \ 659 "rootfsaddr=0x02F00000\0" \ 660 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 661 "rootpath=/opt/nfsroot\0" \ 662 "silent=1\0" \ 663 "tftpflash=tftpboot $loadaddr $uboot; " \ 664 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 665 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 666 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 667 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 668 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 669 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 670 "ubootaddr=0x01000000\0" \ 671 "ubootfile=u-boot.bin\0" \ 672 "upgrade=run flashworking\0" \ 673 "workingaddr=0x02F00000\0" \ 674 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 675 676 #else /* For Arcturus Modules */ 677 678 #define CONFIG_EXTRA_ENV_SETTINGS \ 679 "bootcmd=run norkernel\0" \ 680 "bootfile=uImage\0" \ 681 "consoledev=ttyS0\0" \ 682 "dtbaddr=0x00c00000\0" \ 683 "dtbfile=image.dtb\0" \ 684 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 685 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 686 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 687 "fileaddr=0x01000000\0" \ 688 "filesize=0x00080000\0" \ 689 "flashmbr=sf probe 0; " \ 690 "tftp $loadaddr $mbr; " \ 691 "sf erase $mbr_offset +$filesize; " \ 692 "sf write $loadaddr $mbr_offset $filesize\0" \ 693 "flashuboot=tftp $loadaddr $ubootfile; " \ 694 "protect off $nor_ubootaddr0 +$filesize; " \ 695 "erase $nor_ubootaddr0 +$filesize; " \ 696 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \ 697 "protect on $nor_ubootaddr0 +$filesize; " \ 698 "protect off $nor_ubootaddr1 +$filesize; " \ 699 "erase $nor_ubootaddr1 +$filesize; " \ 700 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \ 701 "protect on $nor_ubootaddr1 +$filesize\0 " \ 702 "format0=protect off $part0base +$part0size; " \ 703 "erase $part0base +$part0size\0" \ 704 "format1=protect off $part1base +$part1size; " \ 705 "erase $part1base +$part1size\0" \ 706 "format2=protect off $part2base +$part2size; " \ 707 "erase $part2base +$part2size\0" \ 708 "format3=protect off $part3base +$part3size; " \ 709 "erase $part3base +$part3size\0" \ 710 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 711 "kerneladdr=0x01100000\0" \ 712 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \ 713 "kernelfile=uImage\0" \ 714 "loadaddr=0x01000000\0" \ 715 "mbr=uCP1020.mbr\0" \ 716 "mbr_offset=0x00000000\0" \ 717 "netdev=eth0\0" \ 718 "nor_ubootaddr0=0xEC000000\0" \ 719 "nor_ubootaddr1=0xEFF80000\0" \ 720 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \ 721 "run norkernelload; " \ 722 "bootm $kerneladdr - $dtbaddr\0" \ 723 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \ 724 "setenv cramfsaddr $part0base; " \ 725 "cramfsload $dtbaddr $dtbfile; " \ 726 "cramfsload $kerneladdr $kernelfile\0" \ 727 "part0base=0xEC100000\0" \ 728 "part0size=0x00700000\0" \ 729 "part1base=0xEC800000\0" \ 730 "part1size=0x02000000\0" \ 731 "part2base=0xEE800000\0" \ 732 "part2size=0x00800000\0" \ 733 "part3base=0xEF000000\0" \ 734 "part3size=0x00F80000\0" \ 735 "partENVbase=0xEC080000\0" \ 736 "partENVsize=0x00080000\0" \ 737 "program0=tftp part0-000000.bin; " \ 738 "protect off $part0base +$filesize; " \ 739 "erase $part0base +$filesize; " \ 740 "cp.b $loadaddr $part0base $filesize; " \ 741 "echo Verifying...; " \ 742 "cmp.b $loadaddr $part0base $filesize\0" \ 743 "program1=tftp part1-000000.bin; " \ 744 "protect off $part1base +$filesize; " \ 745 "erase $part1base +$filesize; " \ 746 "cp.b $loadaddr $part1base $filesize; " \ 747 "echo Verifying...; " \ 748 "cmp.b $loadaddr $part1base $filesize\0" \ 749 "program2=tftp part2-000000.bin; " \ 750 "protect off $part2base +$filesize; " \ 751 "erase $part2base +$filesize; " \ 752 "cp.b $loadaddr $part2base $filesize; " \ 753 "echo Verifying...; " \ 754 "cmp.b $loadaddr $part2base $filesize\0" \ 755 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 756 " console=$consoledev,$baudrate $othbootargs; " \ 757 "tftp $rootfsaddr $rootfsfile; " \ 758 "tftp $loadaddr $kernelfile; " \ 759 "tftp $dtbaddr $dtbfile; " \ 760 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 761 "ramdisk_size=120000\0" \ 762 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 763 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 764 "mw.l 0xffe0f008 0x00400000\0" \ 765 "rootfsaddr=0x02F00000\0" \ 766 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 767 "rootpath=/opt/nfsroot\0" \ 768 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 769 "sf probe 0; sf erase 0 +$filesize; " \ 770 "sf write $loadaddr 0 $filesize\0" \ 771 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 772 "protect off 0xeC000000 +$filesize; " \ 773 "erase 0xEC000000 +$filesize; " \ 774 "cp.b $loadaddr 0xEC000000 $filesize; " \ 775 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 776 "protect on 0xeC000000 +$filesize\0" \ 777 "tftpflash=tftpboot $loadaddr $uboot; " \ 778 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 779 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 780 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 781 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 782 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 783 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 784 "ubootfile=u-boot.bin\0" \ 785 "upgrade=run flashuboot\0" \ 786 "usb_phy_type=ulpi\0 " \ 787 "boot_nfs= " \ 788 "setenv bootargs root=/dev/nfs rw " \ 789 "nfsroot=$serverip:$rootpath " \ 790 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 791 "console=$consoledev,$baudrate $othbootargs;" \ 792 "tftp $loadaddr $bootfile;" \ 793 "tftp $fdtaddr $fdtfile;" \ 794 "bootm $loadaddr - $fdtaddr\0" \ 795 "boot_hd = " \ 796 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 797 "console=$consoledev,$baudrate $othbootargs;" \ 798 "usb start;" \ 799 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 800 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 801 "bootm $loadaddr - $fdtaddr\0" \ 802 "boot_usb_fat = " \ 803 "setenv bootargs root=/dev/ram rw " \ 804 "console=$consoledev,$baudrate $othbootargs " \ 805 "ramdisk_size=$ramdisk_size;" \ 806 "usb start;" \ 807 "fatload usb 0:2 $loadaddr $bootfile;" \ 808 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 809 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 810 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 811 "boot_usb_ext2 = " \ 812 "setenv bootargs root=/dev/ram rw " \ 813 "console=$consoledev,$baudrate $othbootargs " \ 814 "ramdisk_size=$ramdisk_size;" \ 815 "usb start;" \ 816 "ext2load usb 0:4 $loadaddr $bootfile;" \ 817 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 818 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 819 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 820 "boot_nor = " \ 821 "setenv bootargs root=/dev/$jffs2nor rw " \ 822 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 823 "bootm $norbootaddr - $norfdtaddr\0 " \ 824 "boot_ram = " \ 825 "setenv bootargs root=/dev/ram rw " \ 826 "console=$consoledev,$baudrate $othbootargs " \ 827 "ramdisk_size=$ramdisk_size;" \ 828 "tftp $ramdiskaddr $ramdiskfile;" \ 829 "tftp $loadaddr $bootfile;" \ 830 "tftp $fdtaddr $fdtfile;" \ 831 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" 832 833 #endif 834 #endif 835 836 #endif /* __CONFIG_H */ 837