1 /* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * TQM8349 board configuration file 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 #define DEBUG 32 #undef DEBUG 33 34 /* 35 * High Level Configuration Options 36 */ 37 #define CONFIG_E300 1 /* E300 Family */ 38 #define CONFIG_MPC83XX 1 /* MPC83XX family */ 39 #define CONFIG_MPC834X 1 /* MPC834X specific */ 40 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 41 #define CONFIG_TQM834X 1 /* TQM834X board specific */ 42 43 /* IMMR Base Addres Register, use Freescale default: 0xff400000 */ 44 #define CFG_IMMR 0xff400000 45 46 /* System clock. Primary input clock when in PCI host mode */ 47 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ 48 49 /* 50 * Local Bus LCRR 51 * LCRR: DLL bypass, Clock divider is 8 52 * 53 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz 54 * 55 * External Local Bus rate is 56 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 57 */ 58 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) 59 60 /* board pre init: do not call, nothing to do */ 61 #undef CONFIG_BOARD_EARLY_INIT_F 62 63 /* detect the number of flash banks */ 64 #define CONFIG_BOARD_EARLY_INIT_R 65 66 /* 67 * DDR Setup 68 */ 69 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 70 #define CFG_SDRAM_BASE CFG_DDR_BASE 71 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 72 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ 73 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 74 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ 75 76 #undef CFG_DRAM_TEST /* memory test, takes time */ 77 #define CFG_MEMTEST_START 0x00000000 /* memtest region */ 78 #define CFG_MEMTEST_END 0x00100000 79 80 /* 81 * FLASH on the Local Bus 82 */ 83 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 84 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 85 #undef CFG_FLASH_CHECKSUM 86 #define CFG_FLASH_BASE 0x80000000 /* start of FLASH */ 87 #define CFG_FLASH_SIZE 8 /* FLASH size in MB */ 88 89 /* buffered writes in the AMD chip set is not supported yet */ 90 #undef CFG_FLASH_USE_BUFFER_WRITE 91 92 /* 93 * FLASH bank number detection 94 */ 95 96 /* 97 * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash 98 * banks has to be determined at runtime and stored in a gloabl variable 99 * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only 100 * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and 101 * should be made sufficiently large to accomodate the number of banks that 102 * might actually be detected. Since most (all?) Flash related functions use 103 * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is 104 * defined as tqm834x_num_flash_banks. 105 */ 106 #define CFG_MAX_FLASH_BANKS_DETECT 2 107 #ifndef __ASSEMBLY__ 108 extern int tqm834x_num_flash_banks; 109 #endif 110 #define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks) 111 112 #define CFG_MAX_FLASH_SECT 512 /* max sectors per device */ 113 114 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ 115 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA) | \ 116 BR_MS_GPCM | BR_PS_32 | BR_V) 117 118 /* FLASH timing (0x0000_0c54) */ 119 #define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \ 120 OR_GPCM_SCY_5 | OR_GPCM_TRLX) 121 122 #define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */ 123 124 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) 125 126 #define CFG_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */ 127 128 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ 129 130 /* disable remaining mappings */ 131 #define CFG_BR1_PRELIM 0x00000000 132 #define CFG_OR1_PRELIM 0x00000000 133 #define CFG_LBLAWBAR1_PRELIM 0x00000000 134 #define CFG_LBLAWAR1_PRELIM 0x00000000 135 136 #define CFG_BR2_PRELIM 0x00000000 137 #define CFG_OR2_PRELIM 0x00000000 138 #define CFG_LBLAWBAR2_PRELIM 0x00000000 139 #define CFG_LBLAWAR2_PRELIM 0x00000000 140 141 #define CFG_BR3_PRELIM 0x00000000 142 #define CFG_OR3_PRELIM 0x00000000 143 #define CFG_LBLAWBAR3_PRELIM 0x00000000 144 #define CFG_LBLAWAR3_PRELIM 0x00000000 145 146 #define CFG_BR4_PRELIM 0x00000000 147 #define CFG_OR4_PRELIM 0x00000000 148 #define CFG_LBLAWBAR4_PRELIM 0x00000000 149 #define CFG_LBLAWAR4_PRELIM 0x00000000 150 151 #define CFG_BR5_PRELIM 0x00000000 152 #define CFG_OR5_PRELIM 0x00000000 153 #define CFG_LBLAWBAR5_PRELIM 0x00000000 154 #define CFG_LBLAWAR5_PRELIM 0x00000000 155 156 #define CFG_BR6_PRELIM 0x00000000 157 #define CFG_OR6_PRELIM 0x00000000 158 #define CFG_LBLAWBAR6_PRELIM 0x00000000 159 #define CFG_LBLAWAR6_PRELIM 0x00000000 160 161 #define CFG_BR7_PRELIM 0x00000000 162 #define CFG_OR7_PRELIM 0x00000000 163 #define CFG_LBLAWBAR7_PRELIM 0x00000000 164 #define CFG_LBLAWAR7_PRELIM 0x00000000 165 166 /* 167 * Monitor config 168 */ 169 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 170 171 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 172 #define CFG_RAMBOOT 173 #else 174 #undef CFG_RAMBOOT 175 #endif 176 177 #define CONFIG_L1_INIT_RAM 178 #define CFG_INIT_RAM_LOCK 1 179 #define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ 180 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 181 182 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 183 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 184 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 185 186 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 187 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 188 189 /* 190 * Serial Port 191 */ 192 #define CONFIG_CONS_INDEX 1 193 #undef CONFIG_SERIAL_SOFTWARE_FIFO 194 #define CFG_NS16550 195 #define CFG_NS16550_SERIAL 196 #define CFG_NS16550_REG_SIZE 1 197 #define CFG_NS16550_CLK get_bus_freq(0) 198 199 #define CFG_BAUDRATE_TABLE \ 200 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 201 202 #define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) 203 #define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) 204 205 /* 206 * I2C 207 */ 208 #define CONFIG_HARD_I2C /* I2C with hardware support */ 209 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 210 #define CONFIG_FSL_I2C 211 #define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */ 212 #define CFG_I2C_SLAVE 0x7F /* slave address */ 213 #define CFG_I2C_OFFSET 0x3000 214 215 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ 216 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 217 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ 218 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */ 219 #define CFG_EEPROM_PAGE_WRITE_ENABLE 220 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ 221 #define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ 222 223 /* I2C RTC */ 224 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ 225 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 226 227 /* I2C SYSMON (LM75) */ 228 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ 229 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ 230 #define CFG_DTT_MAX_TEMP 70 231 #define CFG_DTT_LOW_TEMP -30 232 #define CFG_DTT_HYSTERESIS 3 233 234 /* 235 * TSEC 236 */ 237 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 238 #define CONFIG_MII 239 240 #define CFG_TSEC1_OFFSET 0x24000 241 #define CFG_TSEC1 (CFG_IMMR + CFG_TSEC1_OFFSET) 242 #define CFG_TSEC2_OFFSET 0x25000 243 #define CFG_TSEC2 (CFG_IMMR + CFG_TSEC2_OFFSET) 244 245 #if defined(CONFIG_TSEC_ENET) 246 247 #ifndef CONFIG_NET_MULTI 248 #define CONFIG_NET_MULTI 249 #endif 250 251 #define CONFIG_TSEC1 1 252 #define CONFIG_TSEC1_NAME "TSEC0" 253 #define CONFIG_TSEC2 1 254 #define CONFIG_TSEC2_NAME "TSEC1" 255 #define TSEC1_PHY_ADDR 2 256 #define TSEC2_PHY_ADDR 1 257 #define TSEC1_PHYIDX 0 258 #define TSEC2_PHYIDX 0 259 260 /* Options are: TSEC[0-1] */ 261 #define CONFIG_ETHPRIME "TSEC0" 262 263 #endif /* CONFIG_TSEC_ENET */ 264 265 /* 266 * General PCI 267 * Addresses are mapped 1-1. 268 */ 269 #define CONFIG_PCI 270 271 #if defined(CONFIG_PCI) 272 273 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 274 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 275 276 /* PCI1 host bridge */ 277 #define CFG_PCI1_MEM_BASE 0xc0000000 278 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 279 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 280 #define CFG_PCI1_IO_BASE 0xe2000000 281 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 282 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 283 284 #undef CONFIG_EEPRO100 285 #define CONFIG_EEPRO100 286 #undef CONFIG_TULIP 287 288 #if !defined(CONFIG_PCI_PNP) 289 #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE 290 #define PCI_ENET0_MEMADDR CFG_PCI1_MEM_BASE 291 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ 292 #endif 293 294 #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 295 296 #endif /* CONFIG_PCI */ 297 298 /* 299 * Environment 300 */ 301 #define CONFIG_ENV_OVERWRITE 302 303 #ifndef CFG_RAMBOOT 304 #define CFG_ENV_IS_IN_FLASH 1 305 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 306 #define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ 307 #define CFG_ENV_SIZE 0x2000 308 #else 309 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 310 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 311 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 312 #define CFG_ENV_SIZE 0x2000 313 #endif 314 315 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 316 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 317 318 /* 319 * Command line configuration. 320 */ 321 #include <config_cmd_default.h> 322 323 #define CONFIG_CMD_DATE 324 #define CONFIG_CMD_DTT 325 #define CONFIG_CMD_EEPROM 326 #define CONFIG_CMD_I2C 327 #define CONFIG_CMD_JFFS2 328 #define CONFIG_CMD_MII 329 #define CONFIG_CMD_PING 330 331 #if defined(CONFIG_PCI) 332 #define CONFIG_CMD_PCI 333 #endif 334 335 #if defined(CFG_RAMBOOT) 336 #undef CONFIG_CMD_ENV 337 #undef CONFIG_CMD_LOADS 338 #endif 339 340 /* 341 * Miscellaneous configurable options 342 */ 343 #define CFG_LONGHELP /* undef to save memory */ 344 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 345 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 346 347 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 348 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ 349 #ifdef CFG_HUSH_PARSER 350 #define CFG_PROMPT_HUSH_PS2 "> " 351 #endif 352 353 #if defined(CONFIG_CMD_KGDB) 354 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 355 #else 356 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 357 #endif 358 359 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 360 #define CFG_MAXARGS 16 /* max number of command args */ 361 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 362 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 363 364 #undef CONFIG_WATCHDOG /* watchdog disabled */ 365 366 /* 367 * For booting Linux, the board info and command line data 368 * have to be in the first 8 MB of memory, since this is 369 * the maximum mapped by the Linux kernel during initialization. 370 */ 371 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 372 373 /* 374 * Cache Configuration 375 */ 376 #define CFG_DCACHE_SIZE 32768 377 #define CFG_CACHELINE_SIZE 32 378 #if defined(CONFIG_CMD_KGDB) 379 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 380 #endif 381 382 #define CFG_HRCW_LOW (\ 383 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 384 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 385 HRCWL_CSB_TO_CLKIN_4X1 |\ 386 HRCWL_VCO_1X2 |\ 387 HRCWL_CORE_TO_CSB_2X1) 388 389 #if defined(PCI_64BIT) 390 #define CFG_HRCW_HIGH (\ 391 HRCWH_PCI_HOST |\ 392 HRCWH_64_BIT_PCI |\ 393 HRCWH_PCI1_ARBITER_ENABLE |\ 394 HRCWH_PCI2_ARBITER_DISABLE |\ 395 HRCWH_CORE_ENABLE |\ 396 HRCWH_FROM_0X00000100 |\ 397 HRCWH_BOOTSEQ_DISABLE |\ 398 HRCWH_SW_WATCHDOG_DISABLE |\ 399 HRCWH_ROM_LOC_LOCAL_16BIT |\ 400 HRCWH_TSEC1M_IN_GMII |\ 401 HRCWH_TSEC2M_IN_GMII ) 402 #else 403 #define CFG_HRCW_HIGH (\ 404 HRCWH_PCI_HOST |\ 405 HRCWH_32_BIT_PCI |\ 406 HRCWH_PCI1_ARBITER_ENABLE |\ 407 HRCWH_PCI2_ARBITER_DISABLE |\ 408 HRCWH_CORE_ENABLE |\ 409 HRCWH_FROM_0X00000100 |\ 410 HRCWH_BOOTSEQ_DISABLE |\ 411 HRCWH_SW_WATCHDOG_DISABLE |\ 412 HRCWH_ROM_LOC_LOCAL_16BIT |\ 413 HRCWH_TSEC1M_IN_GMII |\ 414 HRCWH_TSEC2M_IN_GMII ) 415 #endif 416 417 /* System IO Config */ 418 #define CFG_SICRH SICRH_TSOBI1 419 #define CFG_SICRL SICRL_LDP_A 420 421 /* i-cache and d-cache disabled */ 422 #define CFG_HID0_INIT 0x000000000 423 #define CFG_HID0_FINAL CFG_HID0_INIT 424 #define CFG_HID2 HID2_HBE 425 426 /* DDR 0 - 512M */ 427 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 428 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 429 #define CFG_IBAT1L (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 430 #define CFG_IBAT1U (CFG_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) 431 432 /* stack in DCACHE @ 512M (no backing mem) */ 433 #define CFG_IBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) 434 #define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 435 436 /* PCI */ 437 #ifdef CONFIG_PCI 438 #define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 439 #define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 440 #define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 441 #define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) 442 #define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 443 #define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP) 444 #else 445 #define CFG_IBAT3L (0) 446 #define CFG_IBAT3U (0) 447 #define CFG_IBAT4L (0) 448 #define CFG_IBAT4U (0) 449 #define CFG_IBAT5L (0) 450 #define CFG_IBAT5U (0) 451 #endif 452 453 /* IMMRBAR */ 454 #define CFG_IBAT6L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 455 #define CFG_IBAT6U (CFG_IMMR | BATU_BL_1M | BATU_VS | BATU_VP) 456 457 /* FLASH */ 458 #define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 459 #define CFG_IBAT7U (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 460 461 #define CFG_DBAT0L CFG_IBAT0L 462 #define CFG_DBAT0U CFG_IBAT0U 463 #define CFG_DBAT1L CFG_IBAT1L 464 #define CFG_DBAT1U CFG_IBAT1U 465 #define CFG_DBAT2L CFG_IBAT2L 466 #define CFG_DBAT2U CFG_IBAT2U 467 #define CFG_DBAT3L CFG_IBAT3L 468 #define CFG_DBAT3U CFG_IBAT3U 469 #define CFG_DBAT4L CFG_IBAT4L 470 #define CFG_DBAT4U CFG_IBAT4U 471 #define CFG_DBAT5L CFG_IBAT5L 472 #define CFG_DBAT5U CFG_IBAT5U 473 #define CFG_DBAT6L CFG_IBAT6L 474 #define CFG_DBAT6U CFG_IBAT6U 475 #define CFG_DBAT7L CFG_IBAT7L 476 #define CFG_DBAT7U CFG_IBAT7U 477 478 /* 479 * Internal Definitions 480 * 481 * Boot Flags 482 */ 483 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 484 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 485 486 #if defined(CONFIG_CMD_KGDB) 487 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 488 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 489 #endif 490 491 /* 492 * Environment Configuration 493 */ 494 495 #if defined(CONFIG_TSEC_ENET) 496 #define CONFIG_ETHADDR D2:DA:5E:44:BC:29 497 #define CONFIG_HAS_ETH1 498 #define CONFIG_ETH1ADDR 1E:F3:40:21:92:53 499 #endif 500 501 #define CONFIG_IPADDR 192.168.205.1 502 503 #define CONFIG_HOSTNAME tqm8349 504 #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx 505 #define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage 506 507 #define CONFIG_SERVERIP 192.168.1.1 508 #define CONFIG_GATEWAYIP 192.168.1.1 509 #define CONFIG_NETMASK 255.255.255.0 510 511 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 512 513 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 514 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 515 516 #define CONFIG_BAUDRATE 115200 517 518 #define CONFIG_PREBOOT "echo;" \ 519 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ 520 "echo" 521 522 #undef CONFIG_BOOTARGS 523 524 #define CONFIG_EXTRA_ENV_SETTINGS \ 525 "netdev=eth0\0" \ 526 "hostname=tqm83xx\0" \ 527 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 528 "nfsroot=${serverip}:${rootpath}\0" \ 529 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 530 "addip=setenv bootargs ${bootargs} " \ 531 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 532 ":${hostname}:${netdev}:off panic=1\0" \ 533 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 534 "flash_nfs=run nfsargs addip addtty;" \ 535 "bootm ${kernel_addr}\0" \ 536 "flash_self=run ramargs addip addtty;" \ 537 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 538 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 539 "bootm\0" \ 540 "rootpath=/opt/eldk/ppc_6xx\0" \ 541 "bootfile=/tftpboot/tqm83xx/uImage\0" \ 542 "kernel_addr=80060000\0" \ 543 "ramdisk_addr=80160000\0" \ 544 "load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0" \ 545 "update=protect off 80000000 8003ffff; " \ 546 "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \ 547 "upd=run load;run update\0" \ 548 "" 549 550 #define CONFIG_BOOTCOMMAND "run flash_self" 551 552 /* 553 * JFFS2 partitions 554 */ 555 /* mtdparts command line support */ 556 #define CONFIG_JFFS2_CMDLINE 557 #define MTDIDS_DEFAULT "nor0=TQM834x-0" 558 559 /* default mtd partition table */ 560 #define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\ 561 "1m(kernel),2m(initrd),"\ 562 "-(user);"\ 563 564 #endif /* __CONFIG_H */ 565