1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2005 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7 /* 8 * TQM8349 board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_E300 1 /* E300 Family */ 18 #define CONFIG_MPC834x 1 /* MPC834x specific */ 19 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 20 21 /* IMMR Base Address Register, use Freescale default: 0xff400000 */ 22 #define CONFIG_SYS_IMMR 0xff400000 23 24 /* System clock. Primary input clock when in PCI host mode */ 25 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ 26 27 /* 28 * Local Bus LCRR 29 * LCRR: DLL bypass, Clock divider is 8 30 * 31 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz 32 * 33 * External Local Bus rate is 34 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 35 */ 36 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 37 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 38 39 /* board pre init: do not call, nothing to do */ 40 41 /* detect the number of flash banks */ 42 43 /* 44 * DDR Setup 45 */ 46 /* DDR is system memory*/ 47 #define CONFIG_SYS_DDR_BASE 0x00000000 48 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 49 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 50 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ 51 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 52 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ 53 54 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 55 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 56 #define CONFIG_SYS_MEMTEST_END 0x00100000 57 58 /* 59 * FLASH on the Local Bus 60 */ 61 #undef CONFIG_SYS_FLASH_CHECKSUM 62 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ 63 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ 64 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ 65 66 /* 67 * FLASH bank number detection 68 */ 69 70 /* 71 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of 72 * Flash banks has to be determined at runtime and stored in a gloabl variable 73 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is 74 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array 75 * flash_info, and should be made sufficiently large to accomodate the number 76 * of banks that might actually be detected. Since most (all?) Flash related 77 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on 78 * the board, it is defined as tqm834x_num_flash_banks. 79 */ 80 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 81 82 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ 83 84 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ 85 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \ 86 | BR_MS_GPCM \ 87 | BR_PS_32 \ 88 | BR_V) 89 90 /* FLASH timing (0x0000_0c54) */ 91 #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \ 92 | OR_GPCM_ACS_DIV4 \ 93 | OR_GPCM_SCY_5 \ 94 | OR_GPCM_TRLX) 95 96 #define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */ 97 98 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ 99 | CONFIG_SYS_OR_TIMING_FLASH) 100 101 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB) 102 103 /* Window base at flash base */ 104 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 105 106 /* disable remaining mappings */ 107 #define CONFIG_SYS_BR1_PRELIM 0x00000000 108 #define CONFIG_SYS_OR1_PRELIM 0x00000000 109 #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000 110 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000 111 112 #define CONFIG_SYS_BR2_PRELIM 0x00000000 113 #define CONFIG_SYS_OR2_PRELIM 0x00000000 114 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000 115 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000 116 117 #define CONFIG_SYS_BR3_PRELIM 0x00000000 118 #define CONFIG_SYS_OR3_PRELIM 0x00000000 119 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000 120 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000 121 122 /* 123 * Monitor config 124 */ 125 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 126 127 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 128 # define CONFIG_SYS_RAMBOOT 129 #else 130 # undef CONFIG_SYS_RAMBOOT 131 #endif 132 133 #define CONFIG_SYS_INIT_RAM_LOCK 1 134 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ 135 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 136 137 #define CONFIG_SYS_GBL_DATA_OFFSET \ 138 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 139 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 140 141 /* Reserve 384 kB = 3 sect. for Mon */ 142 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 143 /* Reserve 512 kB for malloc */ 144 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 145 146 /* 147 * Serial Port 148 */ 149 #define CONFIG_SYS_NS16550_SERIAL 150 #define CONFIG_SYS_NS16550_REG_SIZE 1 151 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 152 153 #define CONFIG_SYS_BAUDRATE_TABLE \ 154 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 155 156 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 157 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 158 159 /* 160 * I2C 161 */ 162 #define CONFIG_SYS_I2C 163 #define CONFIG_SYS_I2C_FSL 164 #define CONFIG_SYS_FSL_I2C_SPEED 400000 165 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 166 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 167 168 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ 169 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 170 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ 171 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ 172 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ 173 174 /* I2C RTC */ 175 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ 176 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 177 178 /* 179 * TSEC 180 */ 181 182 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 183 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 184 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 185 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 186 187 #if defined(CONFIG_TSEC_ENET) 188 189 #define CONFIG_TSEC1 1 190 #define CONFIG_TSEC1_NAME "TSEC0" 191 #define CONFIG_TSEC2 1 192 #define CONFIG_TSEC2_NAME "TSEC1" 193 #define TSEC1_PHY_ADDR 2 194 #define TSEC2_PHY_ADDR 1 195 #define TSEC1_PHYIDX 0 196 #define TSEC2_PHYIDX 0 197 #define TSEC1_FLAGS TSEC_GIGABIT 198 #define TSEC2_FLAGS TSEC_GIGABIT 199 200 /* Options are: TSEC[0-1] */ 201 #define CONFIG_ETHPRIME "TSEC0" 202 203 #endif /* CONFIG_TSEC_ENET */ 204 205 #if defined(CONFIG_PCI) 206 207 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 208 209 /* PCI1 host bridge */ 210 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 211 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 212 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 213 #define CONFIG_SYS_PCI1_MMIO_BASE \ 214 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 215 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 216 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 217 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 218 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 219 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ 220 221 #undef CONFIG_EEPRO100 222 #define CONFIG_EEPRO100 223 #undef CONFIG_TULIP 224 225 #if !defined(CONFIG_PCI_PNP) 226 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE 227 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE 228 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ 229 #endif 230 231 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 232 233 #endif /* CONFIG_PCI */ 234 235 /* 236 * Environment 237 */ 238 #define CONFIG_ENV_ADDR \ 239 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 240 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ 241 #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */ 242 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 243 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 244 245 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 246 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 247 248 /* 249 * BOOTP options 250 */ 251 #define CONFIG_BOOTP_BOOTFILESIZE 252 253 /* 254 * Miscellaneous configurable options 255 */ 256 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 257 258 #undef CONFIG_WATCHDOG /* watchdog disabled */ 259 260 /* 261 * For booting Linux, the board info and command line data 262 * have to be in the first 256 MB of memory, since this is 263 * the maximum mapped by the Linux kernel during initialization. 264 */ 265 /* Initial Memory map for Linux */ 266 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 267 268 #define CONFIG_SYS_HRCW_LOW (\ 269 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 270 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 271 HRCWL_CSB_TO_CLKIN_4X1 |\ 272 HRCWL_VCO_1X2 |\ 273 HRCWL_CORE_TO_CSB_2X1) 274 275 #if defined(PCI_64BIT) 276 #define CONFIG_SYS_HRCW_HIGH (\ 277 HRCWH_PCI_HOST |\ 278 HRCWH_64_BIT_PCI |\ 279 HRCWH_PCI1_ARBITER_ENABLE |\ 280 HRCWH_PCI2_ARBITER_DISABLE |\ 281 HRCWH_CORE_ENABLE |\ 282 HRCWH_FROM_0X00000100 |\ 283 HRCWH_BOOTSEQ_DISABLE |\ 284 HRCWH_SW_WATCHDOG_DISABLE |\ 285 HRCWH_ROM_LOC_LOCAL_16BIT |\ 286 HRCWH_TSEC1M_IN_GMII |\ 287 HRCWH_TSEC2M_IN_GMII) 288 #else 289 #define CONFIG_SYS_HRCW_HIGH (\ 290 HRCWH_PCI_HOST |\ 291 HRCWH_32_BIT_PCI |\ 292 HRCWH_PCI1_ARBITER_ENABLE |\ 293 HRCWH_PCI2_ARBITER_DISABLE |\ 294 HRCWH_CORE_ENABLE |\ 295 HRCWH_FROM_0X00000100 |\ 296 HRCWH_BOOTSEQ_DISABLE |\ 297 HRCWH_SW_WATCHDOG_DISABLE |\ 298 HRCWH_ROM_LOC_LOCAL_16BIT |\ 299 HRCWH_TSEC1M_IN_GMII |\ 300 HRCWH_TSEC2M_IN_GMII) 301 #endif 302 303 /* System IO Config */ 304 #define CONFIG_SYS_SICRH 0 305 #define CONFIG_SYS_SICRL SICRL_LDP_A 306 307 /* i-cache and d-cache disabled */ 308 #define CONFIG_SYS_HID0_INIT 0x000000000 309 #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ 310 HID0_ENABLE_INSTRUCTION_CACHE) 311 #define CONFIG_SYS_HID2 HID2_HBE 312 313 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 314 315 /* DDR 0 - 512M */ 316 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 317 | BATL_PP_RW \ 318 | BATL_MEMCOHERENCE) 319 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 320 | BATU_BL_256M \ 321 | BATU_VS \ 322 | BATU_VP) 323 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 324 | BATL_PP_RW \ 325 | BATL_MEMCOHERENCE) 326 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 327 | BATU_BL_256M \ 328 | BATU_VS \ 329 | BATU_VP) 330 331 /* stack in DCACHE @ 512M (no backing mem) */ 332 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ 333 | BATL_PP_RW \ 334 | BATL_MEMCOHERENCE) 335 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ 336 | BATU_BL_128K \ 337 | BATU_VS \ 338 | BATU_VP) 339 340 /* PCI */ 341 #ifdef CONFIG_PCI 342 #define CONFIG_PCI_INDIRECT_BRIDGE 343 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \ 344 | BATL_PP_RW \ 345 | BATL_MEMCOHERENCE) 346 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \ 347 | BATU_BL_256M \ 348 | BATU_VS \ 349 | BATU_VP) 350 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \ 351 | BATL_PP_RW \ 352 | BATL_MEMCOHERENCE \ 353 | BATL_GUARDEDSTORAGE) 354 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \ 355 | BATU_BL_256M \ 356 | BATU_VS \ 357 | BATU_VP) 358 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \ 359 | BATL_PP_RW \ 360 | BATL_CACHEINHIBIT \ 361 | BATL_GUARDEDSTORAGE) 362 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \ 363 | BATU_BL_16M \ 364 | BATU_VS \ 365 | BATU_VP) 366 #else 367 #define CONFIG_SYS_IBAT3L (0) 368 #define CONFIG_SYS_IBAT3U (0) 369 #define CONFIG_SYS_IBAT4L (0) 370 #define CONFIG_SYS_IBAT4U (0) 371 #define CONFIG_SYS_IBAT5L (0) 372 #define CONFIG_SYS_IBAT5U (0) 373 #endif 374 375 /* IMMRBAR */ 376 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \ 377 | BATL_PP_RW \ 378 | BATL_CACHEINHIBIT \ 379 | BATL_GUARDEDSTORAGE) 380 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \ 381 | BATU_BL_1M \ 382 | BATU_VS \ 383 | BATU_VP) 384 385 /* FLASH */ 386 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \ 387 | BATL_PP_RW \ 388 | BATL_CACHEINHIBIT \ 389 | BATL_GUARDEDSTORAGE) 390 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \ 391 | BATU_BL_256M \ 392 | BATU_VS \ 393 | BATU_VP) 394 395 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 396 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 397 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 398 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 399 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 400 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 401 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 402 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 403 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 404 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 405 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 406 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 407 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 408 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 409 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 410 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 411 412 #if defined(CONFIG_CMD_KGDB) 413 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 414 #endif 415 416 /* 417 * Environment Configuration 418 */ 419 420 /* default location for tftp and bootm */ 421 #define CONFIG_LOADADDR 400000 422 423 #define CONFIG_PREBOOT "echo;" \ 424 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 425 "echo" 426 427 #define CONFIG_EXTRA_ENV_SETTINGS \ 428 "netdev=eth0\0" \ 429 "hostname=tqm834x\0" \ 430 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 431 "nfsroot=${serverip}:${rootpath}\0" \ 432 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 433 "addip=setenv bootargs ${bootargs} " \ 434 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 435 ":${hostname}:${netdev}:off panic=1\0" \ 436 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ 437 "flash_nfs_old=run nfsargs addip addcons;" \ 438 "bootm ${kernel_addr}\0" \ 439 "flash_nfs=run nfsargs addip addcons;" \ 440 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 441 "flash_self_old=run ramargs addip addcons;" \ 442 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 443 "flash_self=run ramargs addip addcons;" \ 444 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 445 "net_nfs_old=tftp 400000 ${bootfile};" \ 446 "run nfsargs addip addcons;bootm\0" \ 447 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 448 "tftp ${fdt_addr_r} ${fdt_file}; " \ 449 "run nfsargs addip addcons; " \ 450 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 451 "rootpath=/opt/eldk/ppc_6xx\0" \ 452 "bootfile=tqm834x/uImage\0" \ 453 "fdtfile=tqm834x/tqm834x.dtb\0" \ 454 "kernel_addr_r=400000\0" \ 455 "fdt_addr_r=600000\0" \ 456 "ramdisk_addr_r=800000\0" \ 457 "kernel_addr=800C0000\0" \ 458 "fdt_addr=800A0000\0" \ 459 "ramdisk_addr=80300000\0" \ 460 "u-boot=tqm834x/u-boot.bin\0" \ 461 "load=tftp 200000 ${u-boot}\0" \ 462 "update=protect off 80000000 +${filesize};" \ 463 "era 80000000 +${filesize};" \ 464 "cp.b 200000 80000000 ${filesize}\0" \ 465 "upd=run load update\0" \ 466 "" 467 468 #define CONFIG_BOOTCOMMAND "run flash_self" 469 470 /* 471 * JFFS2 partitions 472 */ 473 /* mtdparts command line support */ 474 475 /* default mtd partition table */ 476 #endif /* __CONFIG_H */ 477