1 /* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * TQM8349 board configuration file 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 #define CONFIG_E300 1 /* E300 Family */ 19 #define CONFIG_MPC834x 1 /* MPC834x specific */ 20 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 21 22 /* IMMR Base Address Register, use Freescale default: 0xff400000 */ 23 #define CONFIG_SYS_IMMR 0xff400000 24 25 /* System clock. Primary input clock when in PCI host mode */ 26 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ 27 28 /* 29 * Local Bus LCRR 30 * LCRR: DLL bypass, Clock divider is 8 31 * 32 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz 33 * 34 * External Local Bus rate is 35 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 36 */ 37 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 38 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 39 40 /* board pre init: do not call, nothing to do */ 41 42 /* detect the number of flash banks */ 43 #define CONFIG_BOARD_EARLY_INIT_R 44 45 /* 46 * DDR Setup 47 */ 48 /* DDR is system memory*/ 49 #define CONFIG_SYS_DDR_BASE 0x00000000 50 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 51 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 52 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ 53 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 54 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ 55 56 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 57 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 58 #define CONFIG_SYS_MEMTEST_END 0x00100000 59 60 /* 61 * FLASH on the Local Bus 62 */ 63 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 64 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 65 #undef CONFIG_SYS_FLASH_CHECKSUM 66 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ 67 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ 68 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ 69 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 70 71 /* 72 * FLASH bank number detection 73 */ 74 75 /* 76 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of 77 * Flash banks has to be determined at runtime and stored in a gloabl variable 78 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is 79 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array 80 * flash_info, and should be made sufficiently large to accomodate the number 81 * of banks that might actually be detected. Since most (all?) Flash related 82 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on 83 * the board, it is defined as tqm834x_num_flash_banks. 84 */ 85 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 86 87 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ 88 89 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ 90 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \ 91 | BR_MS_GPCM \ 92 | BR_PS_32 \ 93 | BR_V) 94 95 /* FLASH timing (0x0000_0c54) */ 96 #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \ 97 | OR_GPCM_ACS_DIV4 \ 98 | OR_GPCM_SCY_5 \ 99 | OR_GPCM_TRLX) 100 101 #define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */ 102 103 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ 104 | CONFIG_SYS_OR_TIMING_FLASH) 105 106 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB) 107 108 /* Window base at flash base */ 109 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 110 111 /* disable remaining mappings */ 112 #define CONFIG_SYS_BR1_PRELIM 0x00000000 113 #define CONFIG_SYS_OR1_PRELIM 0x00000000 114 #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000 115 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000 116 117 #define CONFIG_SYS_BR2_PRELIM 0x00000000 118 #define CONFIG_SYS_OR2_PRELIM 0x00000000 119 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000 120 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000 121 122 #define CONFIG_SYS_BR3_PRELIM 0x00000000 123 #define CONFIG_SYS_OR3_PRELIM 0x00000000 124 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000 125 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000 126 127 /* 128 * Monitor config 129 */ 130 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 131 132 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 133 # define CONFIG_SYS_RAMBOOT 134 #else 135 # undef CONFIG_SYS_RAMBOOT 136 #endif 137 138 #define CONFIG_SYS_INIT_RAM_LOCK 1 139 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ 140 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 141 142 #define CONFIG_SYS_GBL_DATA_OFFSET \ 143 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 144 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 145 146 /* Reserve 384 kB = 3 sect. for Mon */ 147 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 148 /* Reserve 512 kB for malloc */ 149 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 150 151 /* 152 * Serial Port 153 */ 154 #define CONFIG_CONS_INDEX 1 155 #define CONFIG_SYS_NS16550_SERIAL 156 #define CONFIG_SYS_NS16550_REG_SIZE 1 157 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 158 159 #define CONFIG_SYS_BAUDRATE_TABLE \ 160 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 161 162 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 163 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 164 165 /* 166 * I2C 167 */ 168 #define CONFIG_SYS_I2C 169 #define CONFIG_SYS_I2C_FSL 170 #define CONFIG_SYS_FSL_I2C_SPEED 400000 171 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 172 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 173 174 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ 175 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 176 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ 177 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ 178 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ 179 180 /* I2C RTC */ 181 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ 182 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 183 184 /* 185 * TSEC 186 */ 187 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 188 #define CONFIG_MII 189 190 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 191 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 192 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 193 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 194 195 #if defined(CONFIG_TSEC_ENET) 196 197 #define CONFIG_TSEC1 1 198 #define CONFIG_TSEC1_NAME "TSEC0" 199 #define CONFIG_TSEC2 1 200 #define CONFIG_TSEC2_NAME "TSEC1" 201 #define TSEC1_PHY_ADDR 2 202 #define TSEC2_PHY_ADDR 1 203 #define TSEC1_PHYIDX 0 204 #define TSEC2_PHYIDX 0 205 #define TSEC1_FLAGS TSEC_GIGABIT 206 #define TSEC2_FLAGS TSEC_GIGABIT 207 208 /* Options are: TSEC[0-1] */ 209 #define CONFIG_ETHPRIME "TSEC0" 210 211 #endif /* CONFIG_TSEC_ENET */ 212 213 #if defined(CONFIG_PCI) 214 215 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 216 217 /* PCI1 host bridge */ 218 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 219 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 220 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 221 #define CONFIG_SYS_PCI1_MMIO_BASE \ 222 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 223 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 224 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 225 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 226 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 227 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ 228 229 #undef CONFIG_EEPRO100 230 #define CONFIG_EEPRO100 231 #undef CONFIG_TULIP 232 233 #if !defined(CONFIG_PCI_PNP) 234 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE 235 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE 236 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ 237 #endif 238 239 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 240 241 #endif /* CONFIG_PCI */ 242 243 /* 244 * Environment 245 */ 246 #define CONFIG_ENV_ADDR \ 247 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 248 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ 249 #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */ 250 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 251 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 252 253 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 254 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 255 256 /* 257 * BOOTP options 258 */ 259 #define CONFIG_BOOTP_BOOTFILESIZE 260 261 /* 262 * Miscellaneous configurable options 263 */ 264 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 265 266 #undef CONFIG_WATCHDOG /* watchdog disabled */ 267 268 /* 269 * For booting Linux, the board info and command line data 270 * have to be in the first 256 MB of memory, since this is 271 * the maximum mapped by the Linux kernel during initialization. 272 */ 273 /* Initial Memory map for Linux */ 274 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 275 276 #define CONFIG_SYS_HRCW_LOW (\ 277 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 278 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 279 HRCWL_CSB_TO_CLKIN_4X1 |\ 280 HRCWL_VCO_1X2 |\ 281 HRCWL_CORE_TO_CSB_2X1) 282 283 #if defined(PCI_64BIT) 284 #define CONFIG_SYS_HRCW_HIGH (\ 285 HRCWH_PCI_HOST |\ 286 HRCWH_64_BIT_PCI |\ 287 HRCWH_PCI1_ARBITER_ENABLE |\ 288 HRCWH_PCI2_ARBITER_DISABLE |\ 289 HRCWH_CORE_ENABLE |\ 290 HRCWH_FROM_0X00000100 |\ 291 HRCWH_BOOTSEQ_DISABLE |\ 292 HRCWH_SW_WATCHDOG_DISABLE |\ 293 HRCWH_ROM_LOC_LOCAL_16BIT |\ 294 HRCWH_TSEC1M_IN_GMII |\ 295 HRCWH_TSEC2M_IN_GMII) 296 #else 297 #define CONFIG_SYS_HRCW_HIGH (\ 298 HRCWH_PCI_HOST |\ 299 HRCWH_32_BIT_PCI |\ 300 HRCWH_PCI1_ARBITER_ENABLE |\ 301 HRCWH_PCI2_ARBITER_DISABLE |\ 302 HRCWH_CORE_ENABLE |\ 303 HRCWH_FROM_0X00000100 |\ 304 HRCWH_BOOTSEQ_DISABLE |\ 305 HRCWH_SW_WATCHDOG_DISABLE |\ 306 HRCWH_ROM_LOC_LOCAL_16BIT |\ 307 HRCWH_TSEC1M_IN_GMII |\ 308 HRCWH_TSEC2M_IN_GMII) 309 #endif 310 311 /* System IO Config */ 312 #define CONFIG_SYS_SICRH 0 313 #define CONFIG_SYS_SICRL SICRL_LDP_A 314 315 /* i-cache and d-cache disabled */ 316 #define CONFIG_SYS_HID0_INIT 0x000000000 317 #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ 318 HID0_ENABLE_INSTRUCTION_CACHE) 319 #define CONFIG_SYS_HID2 HID2_HBE 320 321 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 322 323 /* DDR 0 - 512M */ 324 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 325 | BATL_PP_RW \ 326 | BATL_MEMCOHERENCE) 327 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 328 | BATU_BL_256M \ 329 | BATU_VS \ 330 | BATU_VP) 331 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 332 | BATL_PP_RW \ 333 | BATL_MEMCOHERENCE) 334 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 335 | BATU_BL_256M \ 336 | BATU_VS \ 337 | BATU_VP) 338 339 /* stack in DCACHE @ 512M (no backing mem) */ 340 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ 341 | BATL_PP_RW \ 342 | BATL_MEMCOHERENCE) 343 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ 344 | BATU_BL_128K \ 345 | BATU_VS \ 346 | BATU_VP) 347 348 /* PCI */ 349 #ifdef CONFIG_PCI 350 #define CONFIG_PCI_INDIRECT_BRIDGE 351 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \ 352 | BATL_PP_RW \ 353 | BATL_MEMCOHERENCE) 354 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \ 355 | BATU_BL_256M \ 356 | BATU_VS \ 357 | BATU_VP) 358 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \ 359 | BATL_PP_RW \ 360 | BATL_MEMCOHERENCE \ 361 | BATL_GUARDEDSTORAGE) 362 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \ 363 | BATU_BL_256M \ 364 | BATU_VS \ 365 | BATU_VP) 366 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \ 367 | BATL_PP_RW \ 368 | BATL_CACHEINHIBIT \ 369 | BATL_GUARDEDSTORAGE) 370 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \ 371 | BATU_BL_16M \ 372 | BATU_VS \ 373 | BATU_VP) 374 #else 375 #define CONFIG_SYS_IBAT3L (0) 376 #define CONFIG_SYS_IBAT3U (0) 377 #define CONFIG_SYS_IBAT4L (0) 378 #define CONFIG_SYS_IBAT4U (0) 379 #define CONFIG_SYS_IBAT5L (0) 380 #define CONFIG_SYS_IBAT5U (0) 381 #endif 382 383 /* IMMRBAR */ 384 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \ 385 | BATL_PP_RW \ 386 | BATL_CACHEINHIBIT \ 387 | BATL_GUARDEDSTORAGE) 388 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \ 389 | BATU_BL_1M \ 390 | BATU_VS \ 391 | BATU_VP) 392 393 /* FLASH */ 394 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \ 395 | BATL_PP_RW \ 396 | BATL_CACHEINHIBIT \ 397 | BATL_GUARDEDSTORAGE) 398 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \ 399 | BATU_BL_256M \ 400 | BATU_VS \ 401 | BATU_VP) 402 403 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 404 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 405 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 406 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 407 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 408 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 409 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 410 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 411 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 412 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 413 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 414 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 415 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 416 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 417 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 418 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 419 420 #if defined(CONFIG_CMD_KGDB) 421 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 422 #endif 423 424 /* 425 * Environment Configuration 426 */ 427 428 /* default location for tftp and bootm */ 429 #define CONFIG_LOADADDR 400000 430 431 #define CONFIG_PREBOOT "echo;" \ 432 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 433 "echo" 434 435 #define CONFIG_EXTRA_ENV_SETTINGS \ 436 "netdev=eth0\0" \ 437 "hostname=tqm834x\0" \ 438 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 439 "nfsroot=${serverip}:${rootpath}\0" \ 440 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 441 "addip=setenv bootargs ${bootargs} " \ 442 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 443 ":${hostname}:${netdev}:off panic=1\0" \ 444 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ 445 "flash_nfs_old=run nfsargs addip addcons;" \ 446 "bootm ${kernel_addr}\0" \ 447 "flash_nfs=run nfsargs addip addcons;" \ 448 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 449 "flash_self_old=run ramargs addip addcons;" \ 450 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 451 "flash_self=run ramargs addip addcons;" \ 452 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 453 "net_nfs_old=tftp 400000 ${bootfile};" \ 454 "run nfsargs addip addcons;bootm\0" \ 455 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 456 "tftp ${fdt_addr_r} ${fdt_file}; " \ 457 "run nfsargs addip addcons; " \ 458 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 459 "rootpath=/opt/eldk/ppc_6xx\0" \ 460 "bootfile=tqm834x/uImage\0" \ 461 "fdtfile=tqm834x/tqm834x.dtb\0" \ 462 "kernel_addr_r=400000\0" \ 463 "fdt_addr_r=600000\0" \ 464 "ramdisk_addr_r=800000\0" \ 465 "kernel_addr=800C0000\0" \ 466 "fdt_addr=800A0000\0" \ 467 "ramdisk_addr=80300000\0" \ 468 "u-boot=tqm834x/u-boot.bin\0" \ 469 "load=tftp 200000 ${u-boot}\0" \ 470 "update=protect off 80000000 +${filesize};" \ 471 "era 80000000 +${filesize};" \ 472 "cp.b 200000 80000000 ${filesize}\0" \ 473 "upd=run load update\0" \ 474 "" 475 476 #define CONFIG_BOOTCOMMAND "run flash_self" 477 478 /* 479 * JFFS2 partitions 480 */ 481 /* mtdparts command line support */ 482 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 483 #define CONFIG_FLASH_CFI_MTD 484 485 /* default mtd partition table */ 486 #endif /* __CONFIG_H */ 487