1 /* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * TQM8349 board configuration file 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 #define CONFIG_E300 1 /* E300 Family */ 19 #define CONFIG_MPC834x 1 /* MPC834x specific */ 20 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 21 22 /* IMMR Base Address Register, use Freescale default: 0xff400000 */ 23 #define CONFIG_SYS_IMMR 0xff400000 24 25 /* System clock. Primary input clock when in PCI host mode */ 26 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ 27 28 /* 29 * Local Bus LCRR 30 * LCRR: DLL bypass, Clock divider is 8 31 * 32 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz 33 * 34 * External Local Bus rate is 35 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 36 */ 37 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 38 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 39 40 /* board pre init: do not call, nothing to do */ 41 42 /* detect the number of flash banks */ 43 44 /* 45 * DDR Setup 46 */ 47 /* DDR is system memory*/ 48 #define CONFIG_SYS_DDR_BASE 0x00000000 49 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 50 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 51 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ 52 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 53 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ 54 55 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 56 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 57 #define CONFIG_SYS_MEMTEST_END 0x00100000 58 59 /* 60 * FLASH on the Local Bus 61 */ 62 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 63 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 64 #undef CONFIG_SYS_FLASH_CHECKSUM 65 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ 66 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ 67 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ 68 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 69 70 /* 71 * FLASH bank number detection 72 */ 73 74 /* 75 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of 76 * Flash banks has to be determined at runtime and stored in a gloabl variable 77 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is 78 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array 79 * flash_info, and should be made sufficiently large to accomodate the number 80 * of banks that might actually be detected. Since most (all?) Flash related 81 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on 82 * the board, it is defined as tqm834x_num_flash_banks. 83 */ 84 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 85 86 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ 87 88 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ 89 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \ 90 | BR_MS_GPCM \ 91 | BR_PS_32 \ 92 | BR_V) 93 94 /* FLASH timing (0x0000_0c54) */ 95 #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \ 96 | OR_GPCM_ACS_DIV4 \ 97 | OR_GPCM_SCY_5 \ 98 | OR_GPCM_TRLX) 99 100 #define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */ 101 102 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ 103 | CONFIG_SYS_OR_TIMING_FLASH) 104 105 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB) 106 107 /* Window base at flash base */ 108 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 109 110 /* disable remaining mappings */ 111 #define CONFIG_SYS_BR1_PRELIM 0x00000000 112 #define CONFIG_SYS_OR1_PRELIM 0x00000000 113 #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000 114 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000 115 116 #define CONFIG_SYS_BR2_PRELIM 0x00000000 117 #define CONFIG_SYS_OR2_PRELIM 0x00000000 118 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000 119 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000 120 121 #define CONFIG_SYS_BR3_PRELIM 0x00000000 122 #define CONFIG_SYS_OR3_PRELIM 0x00000000 123 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000 124 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000 125 126 /* 127 * Monitor config 128 */ 129 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 130 131 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 132 # define CONFIG_SYS_RAMBOOT 133 #else 134 # undef CONFIG_SYS_RAMBOOT 135 #endif 136 137 #define CONFIG_SYS_INIT_RAM_LOCK 1 138 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ 139 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 140 141 #define CONFIG_SYS_GBL_DATA_OFFSET \ 142 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 143 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 144 145 /* Reserve 384 kB = 3 sect. for Mon */ 146 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 147 /* Reserve 512 kB for malloc */ 148 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 149 150 /* 151 * Serial Port 152 */ 153 #define CONFIG_SYS_NS16550_SERIAL 154 #define CONFIG_SYS_NS16550_REG_SIZE 1 155 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 156 157 #define CONFIG_SYS_BAUDRATE_TABLE \ 158 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 159 160 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 161 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 162 163 /* 164 * I2C 165 */ 166 #define CONFIG_SYS_I2C 167 #define CONFIG_SYS_I2C_FSL 168 #define CONFIG_SYS_FSL_I2C_SPEED 400000 169 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 170 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 171 172 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ 173 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 174 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ 175 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ 176 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ 177 178 /* I2C RTC */ 179 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ 180 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 181 182 /* 183 * TSEC 184 */ 185 #define CONFIG_MII 186 187 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 188 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 189 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 190 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 191 192 #if defined(CONFIG_TSEC_ENET) 193 194 #define CONFIG_TSEC1 1 195 #define CONFIG_TSEC1_NAME "TSEC0" 196 #define CONFIG_TSEC2 1 197 #define CONFIG_TSEC2_NAME "TSEC1" 198 #define TSEC1_PHY_ADDR 2 199 #define TSEC2_PHY_ADDR 1 200 #define TSEC1_PHYIDX 0 201 #define TSEC2_PHYIDX 0 202 #define TSEC1_FLAGS TSEC_GIGABIT 203 #define TSEC2_FLAGS TSEC_GIGABIT 204 205 /* Options are: TSEC[0-1] */ 206 #define CONFIG_ETHPRIME "TSEC0" 207 208 #endif /* CONFIG_TSEC_ENET */ 209 210 #if defined(CONFIG_PCI) 211 212 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 213 214 /* PCI1 host bridge */ 215 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 216 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 217 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 218 #define CONFIG_SYS_PCI1_MMIO_BASE \ 219 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 220 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 221 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 222 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 223 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 224 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ 225 226 #undef CONFIG_EEPRO100 227 #define CONFIG_EEPRO100 228 #undef CONFIG_TULIP 229 230 #if !defined(CONFIG_PCI_PNP) 231 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE 232 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE 233 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ 234 #endif 235 236 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 237 238 #endif /* CONFIG_PCI */ 239 240 /* 241 * Environment 242 */ 243 #define CONFIG_ENV_ADDR \ 244 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 245 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ 246 #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */ 247 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 248 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 249 250 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 251 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 252 253 /* 254 * BOOTP options 255 */ 256 #define CONFIG_BOOTP_BOOTFILESIZE 257 258 /* 259 * Miscellaneous configurable options 260 */ 261 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 262 263 #undef CONFIG_WATCHDOG /* watchdog disabled */ 264 265 /* 266 * For booting Linux, the board info and command line data 267 * have to be in the first 256 MB of memory, since this is 268 * the maximum mapped by the Linux kernel during initialization. 269 */ 270 /* Initial Memory map for Linux */ 271 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 272 273 #define CONFIG_SYS_HRCW_LOW (\ 274 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 275 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 276 HRCWL_CSB_TO_CLKIN_4X1 |\ 277 HRCWL_VCO_1X2 |\ 278 HRCWL_CORE_TO_CSB_2X1) 279 280 #if defined(PCI_64BIT) 281 #define CONFIG_SYS_HRCW_HIGH (\ 282 HRCWH_PCI_HOST |\ 283 HRCWH_64_BIT_PCI |\ 284 HRCWH_PCI1_ARBITER_ENABLE |\ 285 HRCWH_PCI2_ARBITER_DISABLE |\ 286 HRCWH_CORE_ENABLE |\ 287 HRCWH_FROM_0X00000100 |\ 288 HRCWH_BOOTSEQ_DISABLE |\ 289 HRCWH_SW_WATCHDOG_DISABLE |\ 290 HRCWH_ROM_LOC_LOCAL_16BIT |\ 291 HRCWH_TSEC1M_IN_GMII |\ 292 HRCWH_TSEC2M_IN_GMII) 293 #else 294 #define CONFIG_SYS_HRCW_HIGH (\ 295 HRCWH_PCI_HOST |\ 296 HRCWH_32_BIT_PCI |\ 297 HRCWH_PCI1_ARBITER_ENABLE |\ 298 HRCWH_PCI2_ARBITER_DISABLE |\ 299 HRCWH_CORE_ENABLE |\ 300 HRCWH_FROM_0X00000100 |\ 301 HRCWH_BOOTSEQ_DISABLE |\ 302 HRCWH_SW_WATCHDOG_DISABLE |\ 303 HRCWH_ROM_LOC_LOCAL_16BIT |\ 304 HRCWH_TSEC1M_IN_GMII |\ 305 HRCWH_TSEC2M_IN_GMII) 306 #endif 307 308 /* System IO Config */ 309 #define CONFIG_SYS_SICRH 0 310 #define CONFIG_SYS_SICRL SICRL_LDP_A 311 312 /* i-cache and d-cache disabled */ 313 #define CONFIG_SYS_HID0_INIT 0x000000000 314 #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ 315 HID0_ENABLE_INSTRUCTION_CACHE) 316 #define CONFIG_SYS_HID2 HID2_HBE 317 318 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 319 320 /* DDR 0 - 512M */ 321 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 322 | BATL_PP_RW \ 323 | BATL_MEMCOHERENCE) 324 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 325 | BATU_BL_256M \ 326 | BATU_VS \ 327 | BATU_VP) 328 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 329 | BATL_PP_RW \ 330 | BATL_MEMCOHERENCE) 331 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 332 | BATU_BL_256M \ 333 | BATU_VS \ 334 | BATU_VP) 335 336 /* stack in DCACHE @ 512M (no backing mem) */ 337 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ 338 | BATL_PP_RW \ 339 | BATL_MEMCOHERENCE) 340 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ 341 | BATU_BL_128K \ 342 | BATU_VS \ 343 | BATU_VP) 344 345 /* PCI */ 346 #ifdef CONFIG_PCI 347 #define CONFIG_PCI_INDIRECT_BRIDGE 348 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \ 349 | BATL_PP_RW \ 350 | BATL_MEMCOHERENCE) 351 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \ 352 | BATU_BL_256M \ 353 | BATU_VS \ 354 | BATU_VP) 355 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \ 356 | BATL_PP_RW \ 357 | BATL_MEMCOHERENCE \ 358 | BATL_GUARDEDSTORAGE) 359 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \ 360 | BATU_BL_256M \ 361 | BATU_VS \ 362 | BATU_VP) 363 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \ 364 | BATL_PP_RW \ 365 | BATL_CACHEINHIBIT \ 366 | BATL_GUARDEDSTORAGE) 367 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \ 368 | BATU_BL_16M \ 369 | BATU_VS \ 370 | BATU_VP) 371 #else 372 #define CONFIG_SYS_IBAT3L (0) 373 #define CONFIG_SYS_IBAT3U (0) 374 #define CONFIG_SYS_IBAT4L (0) 375 #define CONFIG_SYS_IBAT4U (0) 376 #define CONFIG_SYS_IBAT5L (0) 377 #define CONFIG_SYS_IBAT5U (0) 378 #endif 379 380 /* IMMRBAR */ 381 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \ 382 | BATL_PP_RW \ 383 | BATL_CACHEINHIBIT \ 384 | BATL_GUARDEDSTORAGE) 385 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \ 386 | BATU_BL_1M \ 387 | BATU_VS \ 388 | BATU_VP) 389 390 /* FLASH */ 391 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \ 392 | BATL_PP_RW \ 393 | BATL_CACHEINHIBIT \ 394 | BATL_GUARDEDSTORAGE) 395 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \ 396 | BATU_BL_256M \ 397 | BATU_VS \ 398 | BATU_VP) 399 400 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 401 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 402 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 403 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 404 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 405 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 406 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 407 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 408 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 409 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 410 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 411 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 412 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 413 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 414 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 415 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 416 417 #if defined(CONFIG_CMD_KGDB) 418 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 419 #endif 420 421 /* 422 * Environment Configuration 423 */ 424 425 /* default location for tftp and bootm */ 426 #define CONFIG_LOADADDR 400000 427 428 #define CONFIG_PREBOOT "echo;" \ 429 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 430 "echo" 431 432 #define CONFIG_EXTRA_ENV_SETTINGS \ 433 "netdev=eth0\0" \ 434 "hostname=tqm834x\0" \ 435 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 436 "nfsroot=${serverip}:${rootpath}\0" \ 437 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 438 "addip=setenv bootargs ${bootargs} " \ 439 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 440 ":${hostname}:${netdev}:off panic=1\0" \ 441 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ 442 "flash_nfs_old=run nfsargs addip addcons;" \ 443 "bootm ${kernel_addr}\0" \ 444 "flash_nfs=run nfsargs addip addcons;" \ 445 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 446 "flash_self_old=run ramargs addip addcons;" \ 447 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 448 "flash_self=run ramargs addip addcons;" \ 449 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 450 "net_nfs_old=tftp 400000 ${bootfile};" \ 451 "run nfsargs addip addcons;bootm\0" \ 452 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 453 "tftp ${fdt_addr_r} ${fdt_file}; " \ 454 "run nfsargs addip addcons; " \ 455 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 456 "rootpath=/opt/eldk/ppc_6xx\0" \ 457 "bootfile=tqm834x/uImage\0" \ 458 "fdtfile=tqm834x/tqm834x.dtb\0" \ 459 "kernel_addr_r=400000\0" \ 460 "fdt_addr_r=600000\0" \ 461 "ramdisk_addr_r=800000\0" \ 462 "kernel_addr=800C0000\0" \ 463 "fdt_addr=800A0000\0" \ 464 "ramdisk_addr=80300000\0" \ 465 "u-boot=tqm834x/u-boot.bin\0" \ 466 "load=tftp 200000 ${u-boot}\0" \ 467 "update=protect off 80000000 +${filesize};" \ 468 "era 80000000 +${filesize};" \ 469 "cp.b 200000 80000000 ${filesize}\0" \ 470 "upd=run load update\0" \ 471 "" 472 473 #define CONFIG_BOOTCOMMAND "run flash_self" 474 475 /* 476 * JFFS2 partitions 477 */ 478 /* mtdparts command line support */ 479 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 480 #define CONFIG_FLASH_CFI_MTD 481 482 /* default mtd partition table */ 483 #endif /* __CONFIG_H */ 484