1 /* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * TQM8349 board configuration file 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 #define CONFIG_E300 1 /* E300 Family */ 19 #define CONFIG_MPC834x 1 /* MPC834x specific */ 20 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 21 #define CONFIG_TQM834X 1 /* TQM834X board specific */ 22 23 #define CONFIG_SYS_TEXT_BASE 0x80000000 24 25 /* IMMR Base Address Register, use Freescale default: 0xff400000 */ 26 #define CONFIG_SYS_IMMR 0xff400000 27 28 /* System clock. Primary input clock when in PCI host mode */ 29 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ 30 31 /* 32 * Local Bus LCRR 33 * LCRR: DLL bypass, Clock divider is 8 34 * 35 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz 36 * 37 * External Local Bus rate is 38 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 39 */ 40 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 41 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 42 43 /* board pre init: do not call, nothing to do */ 44 #undef CONFIG_BOARD_EARLY_INIT_F 45 46 /* detect the number of flash banks */ 47 #define CONFIG_BOARD_EARLY_INIT_R 48 49 /* 50 * DDR Setup 51 */ 52 /* DDR is system memory*/ 53 #define CONFIG_SYS_DDR_BASE 0x00000000 54 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 55 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 56 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ 57 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 58 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ 59 60 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 61 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 62 #define CONFIG_SYS_MEMTEST_END 0x00100000 63 64 /* 65 * FLASH on the Local Bus 66 */ 67 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 68 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 69 #undef CONFIG_SYS_FLASH_CHECKSUM 70 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ 71 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ 72 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ 73 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 74 75 /* 76 * FLASH bank number detection 77 */ 78 79 /* 80 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of 81 * Flash banks has to be determined at runtime and stored in a gloabl variable 82 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is 83 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array 84 * flash_info, and should be made sufficiently large to accomodate the number 85 * of banks that might actually be detected. Since most (all?) Flash related 86 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on 87 * the board, it is defined as tqm834x_num_flash_banks. 88 */ 89 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 90 91 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ 92 93 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ 94 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \ 95 | BR_MS_GPCM \ 96 | BR_PS_32 \ 97 | BR_V) 98 99 /* FLASH timing (0x0000_0c54) */ 100 #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \ 101 | OR_GPCM_ACS_DIV4 \ 102 | OR_GPCM_SCY_5 \ 103 | OR_GPCM_TRLX) 104 105 #define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */ 106 107 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ 108 | CONFIG_SYS_OR_TIMING_FLASH) 109 110 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB) 111 112 /* Window base at flash base */ 113 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 114 115 /* disable remaining mappings */ 116 #define CONFIG_SYS_BR1_PRELIM 0x00000000 117 #define CONFIG_SYS_OR1_PRELIM 0x00000000 118 #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000 119 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000 120 121 #define CONFIG_SYS_BR2_PRELIM 0x00000000 122 #define CONFIG_SYS_OR2_PRELIM 0x00000000 123 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000 124 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000 125 126 #define CONFIG_SYS_BR3_PRELIM 0x00000000 127 #define CONFIG_SYS_OR3_PRELIM 0x00000000 128 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000 129 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000 130 131 /* 132 * Monitor config 133 */ 134 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 135 136 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 137 # define CONFIG_SYS_RAMBOOT 138 #else 139 # undef CONFIG_SYS_RAMBOOT 140 #endif 141 142 #define CONFIG_SYS_INIT_RAM_LOCK 1 143 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ 144 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 145 146 #define CONFIG_SYS_GBL_DATA_OFFSET \ 147 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 148 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 149 150 /* Reserve 384 kB = 3 sect. for Mon */ 151 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 152 /* Reserve 512 kB for malloc */ 153 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 154 155 /* 156 * Serial Port 157 */ 158 #define CONFIG_CONS_INDEX 1 159 #define CONFIG_SYS_NS16550_SERIAL 160 #define CONFIG_SYS_NS16550_REG_SIZE 1 161 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 162 163 #define CONFIG_SYS_BAUDRATE_TABLE \ 164 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 165 166 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 167 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 168 169 /* 170 * I2C 171 */ 172 #define CONFIG_SYS_I2C 173 #define CONFIG_SYS_I2C_FSL 174 #define CONFIG_SYS_FSL_I2C_SPEED 400000 175 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 176 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 177 178 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ 179 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 180 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ 181 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ 182 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ 183 184 /* I2C RTC */ 185 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ 186 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 187 188 /* I2C SYSMON (LM75) */ 189 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ 190 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ 191 #define CONFIG_SYS_DTT_MAX_TEMP 70 192 #define CONFIG_SYS_DTT_LOW_TEMP -30 193 #define CONFIG_SYS_DTT_HYSTERESIS 3 194 195 /* 196 * TSEC 197 */ 198 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 199 #define CONFIG_MII 200 201 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 202 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 203 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 204 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 205 206 #if defined(CONFIG_TSEC_ENET) 207 208 #define CONFIG_TSEC1 1 209 #define CONFIG_TSEC1_NAME "TSEC0" 210 #define CONFIG_TSEC2 1 211 #define CONFIG_TSEC2_NAME "TSEC1" 212 #define TSEC1_PHY_ADDR 2 213 #define TSEC2_PHY_ADDR 1 214 #define TSEC1_PHYIDX 0 215 #define TSEC2_PHYIDX 0 216 #define TSEC1_FLAGS TSEC_GIGABIT 217 #define TSEC2_FLAGS TSEC_GIGABIT 218 219 /* Options are: TSEC[0-1] */ 220 #define CONFIG_ETHPRIME "TSEC0" 221 222 #endif /* CONFIG_TSEC_ENET */ 223 224 /* 225 * General PCI 226 * Addresses are mapped 1-1. 227 */ 228 229 #if defined(CONFIG_PCI) 230 231 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 232 233 /* PCI1 host bridge */ 234 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 235 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 236 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 237 #define CONFIG_SYS_PCI1_MMIO_BASE \ 238 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 239 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 240 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 241 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 242 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 243 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ 244 245 #undef CONFIG_EEPRO100 246 #define CONFIG_EEPRO100 247 #undef CONFIG_TULIP 248 249 #if !defined(CONFIG_PCI_PNP) 250 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE 251 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE 252 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ 253 #endif 254 255 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 256 257 #endif /* CONFIG_PCI */ 258 259 /* 260 * Environment 261 */ 262 #define CONFIG_ENV_IS_IN_FLASH 1 263 #define CONFIG_ENV_ADDR \ 264 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 265 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ 266 #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */ 267 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 268 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 269 270 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 271 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 272 273 /* 274 * BOOTP options 275 */ 276 #define CONFIG_BOOTP_BOOTFILESIZE 277 #define CONFIG_BOOTP_BOOTPATH 278 #define CONFIG_BOOTP_GATEWAY 279 #define CONFIG_BOOTP_HOSTNAME 280 281 /* 282 * Command line configuration. 283 */ 284 #define CONFIG_CMD_DATE 285 #define CONFIG_CMD_DTT 286 #define CONFIG_CMD_EEPROM 287 #define CONFIG_CMD_JFFS2 288 #define CONFIG_CMD_REGINFO 289 290 #if defined(CONFIG_PCI) 291 #define CONFIG_CMD_PCI 292 #endif 293 294 /* 295 * Miscellaneous configurable options 296 */ 297 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 298 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 299 300 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 301 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 302 303 #if defined(CONFIG_CMD_KGDB) 304 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 305 #else 306 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 307 #endif 308 309 /* Print Buffer Size */ 310 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 311 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 312 /* Boot Argument Buffer Size */ 313 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 314 315 #undef CONFIG_WATCHDOG /* watchdog disabled */ 316 317 /* 318 * For booting Linux, the board info and command line data 319 * have to be in the first 256 MB of memory, since this is 320 * the maximum mapped by the Linux kernel during initialization. 321 */ 322 /* Initial Memory map for Linux */ 323 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 324 325 #define CONFIG_SYS_HRCW_LOW (\ 326 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 327 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 328 HRCWL_CSB_TO_CLKIN_4X1 |\ 329 HRCWL_VCO_1X2 |\ 330 HRCWL_CORE_TO_CSB_2X1) 331 332 #if defined(PCI_64BIT) 333 #define CONFIG_SYS_HRCW_HIGH (\ 334 HRCWH_PCI_HOST |\ 335 HRCWH_64_BIT_PCI |\ 336 HRCWH_PCI1_ARBITER_ENABLE |\ 337 HRCWH_PCI2_ARBITER_DISABLE |\ 338 HRCWH_CORE_ENABLE |\ 339 HRCWH_FROM_0X00000100 |\ 340 HRCWH_BOOTSEQ_DISABLE |\ 341 HRCWH_SW_WATCHDOG_DISABLE |\ 342 HRCWH_ROM_LOC_LOCAL_16BIT |\ 343 HRCWH_TSEC1M_IN_GMII |\ 344 HRCWH_TSEC2M_IN_GMII) 345 #else 346 #define CONFIG_SYS_HRCW_HIGH (\ 347 HRCWH_PCI_HOST |\ 348 HRCWH_32_BIT_PCI |\ 349 HRCWH_PCI1_ARBITER_ENABLE |\ 350 HRCWH_PCI2_ARBITER_DISABLE |\ 351 HRCWH_CORE_ENABLE |\ 352 HRCWH_FROM_0X00000100 |\ 353 HRCWH_BOOTSEQ_DISABLE |\ 354 HRCWH_SW_WATCHDOG_DISABLE |\ 355 HRCWH_ROM_LOC_LOCAL_16BIT |\ 356 HRCWH_TSEC1M_IN_GMII |\ 357 HRCWH_TSEC2M_IN_GMII) 358 #endif 359 360 /* System IO Config */ 361 #define CONFIG_SYS_SICRH 0 362 #define CONFIG_SYS_SICRL SICRL_LDP_A 363 364 /* i-cache and d-cache disabled */ 365 #define CONFIG_SYS_HID0_INIT 0x000000000 366 #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ 367 HID0_ENABLE_INSTRUCTION_CACHE) 368 #define CONFIG_SYS_HID2 HID2_HBE 369 370 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 371 372 /* DDR 0 - 512M */ 373 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 374 | BATL_PP_RW \ 375 | BATL_MEMCOHERENCE) 376 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 377 | BATU_BL_256M \ 378 | BATU_VS \ 379 | BATU_VP) 380 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 381 | BATL_PP_RW \ 382 | BATL_MEMCOHERENCE) 383 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 384 | BATU_BL_256M \ 385 | BATU_VS \ 386 | BATU_VP) 387 388 /* stack in DCACHE @ 512M (no backing mem) */ 389 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ 390 | BATL_PP_RW \ 391 | BATL_MEMCOHERENCE) 392 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ 393 | BATU_BL_128K \ 394 | BATU_VS \ 395 | BATU_VP) 396 397 /* PCI */ 398 #ifdef CONFIG_PCI 399 #define CONFIG_PCI_INDIRECT_BRIDGE 400 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \ 401 | BATL_PP_RW \ 402 | BATL_MEMCOHERENCE) 403 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \ 404 | BATU_BL_256M \ 405 | BATU_VS \ 406 | BATU_VP) 407 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \ 408 | BATL_PP_RW \ 409 | BATL_MEMCOHERENCE \ 410 | BATL_GUARDEDSTORAGE) 411 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \ 412 | BATU_BL_256M \ 413 | BATU_VS \ 414 | BATU_VP) 415 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \ 416 | BATL_PP_RW \ 417 | BATL_CACHEINHIBIT \ 418 | BATL_GUARDEDSTORAGE) 419 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \ 420 | BATU_BL_16M \ 421 | BATU_VS \ 422 | BATU_VP) 423 #else 424 #define CONFIG_SYS_IBAT3L (0) 425 #define CONFIG_SYS_IBAT3U (0) 426 #define CONFIG_SYS_IBAT4L (0) 427 #define CONFIG_SYS_IBAT4U (0) 428 #define CONFIG_SYS_IBAT5L (0) 429 #define CONFIG_SYS_IBAT5U (0) 430 #endif 431 432 /* IMMRBAR */ 433 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \ 434 | BATL_PP_RW \ 435 | BATL_CACHEINHIBIT \ 436 | BATL_GUARDEDSTORAGE) 437 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \ 438 | BATU_BL_1M \ 439 | BATU_VS \ 440 | BATU_VP) 441 442 /* FLASH */ 443 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \ 444 | BATL_PP_RW \ 445 | BATL_CACHEINHIBIT \ 446 | BATL_GUARDEDSTORAGE) 447 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \ 448 | BATU_BL_256M \ 449 | BATU_VS \ 450 | BATU_VP) 451 452 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 453 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 454 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 455 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 456 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 457 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 458 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 459 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 460 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 461 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 462 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 463 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 464 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 465 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 466 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 467 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 468 469 #if defined(CONFIG_CMD_KGDB) 470 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 471 #endif 472 473 /* 474 * Environment Configuration 475 */ 476 477 /* default location for tftp and bootm */ 478 #define CONFIG_LOADADDR 400000 479 480 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 481 482 #define CONFIG_BAUDRATE 115200 483 484 #define CONFIG_PREBOOT "echo;" \ 485 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 486 "echo" 487 488 #undef CONFIG_BOOTARGS 489 490 #define CONFIG_EXTRA_ENV_SETTINGS \ 491 "netdev=eth0\0" \ 492 "hostname=tqm834x\0" \ 493 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 494 "nfsroot=${serverip}:${rootpath}\0" \ 495 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 496 "addip=setenv bootargs ${bootargs} " \ 497 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 498 ":${hostname}:${netdev}:off panic=1\0" \ 499 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ 500 "flash_nfs_old=run nfsargs addip addcons;" \ 501 "bootm ${kernel_addr}\0" \ 502 "flash_nfs=run nfsargs addip addcons;" \ 503 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 504 "flash_self_old=run ramargs addip addcons;" \ 505 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 506 "flash_self=run ramargs addip addcons;" \ 507 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 508 "net_nfs_old=tftp 400000 ${bootfile};" \ 509 "run nfsargs addip addcons;bootm\0" \ 510 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 511 "tftp ${fdt_addr_r} ${fdt_file}; " \ 512 "run nfsargs addip addcons; " \ 513 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 514 "rootpath=/opt/eldk/ppc_6xx\0" \ 515 "bootfile=tqm834x/uImage\0" \ 516 "fdtfile=tqm834x/tqm834x.dtb\0" \ 517 "kernel_addr_r=400000\0" \ 518 "fdt_addr_r=600000\0" \ 519 "ramdisk_addr_r=800000\0" \ 520 "kernel_addr=800C0000\0" \ 521 "fdt_addr=800A0000\0" \ 522 "ramdisk_addr=80300000\0" \ 523 "u-boot=tqm834x/u-boot.bin\0" \ 524 "load=tftp 200000 ${u-boot}\0" \ 525 "update=protect off 80000000 +${filesize};" \ 526 "era 80000000 +${filesize};" \ 527 "cp.b 200000 80000000 ${filesize}\0" \ 528 "upd=run load update\0" \ 529 "" 530 531 #define CONFIG_BOOTCOMMAND "run flash_self" 532 533 /* 534 * JFFS2 partitions 535 */ 536 /* mtdparts command line support */ 537 #define CONFIG_CMD_MTDPARTS 538 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 539 #define CONFIG_FLASH_CFI_MTD 540 #define MTDIDS_DEFAULT "nor0=TQM834x-0" 541 542 /* default mtd partition table */ 543 #define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \ 544 "1m(kernel),2m(initrd)," \ 545 "-(user);" \ 546 547 #endif /* __CONFIG_H */ 548