1 /* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * TQM8349 board configuration file 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 #define CONFIG_E300 1 /* E300 Family */ 19 #define CONFIG_MPC834x 1 /* MPC834x specific */ 20 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 21 #define CONFIG_TQM834X 1 /* TQM834X board specific */ 22 23 #define CONFIG_SYS_TEXT_BASE 0x80000000 24 25 /* IMMR Base Address Register, use Freescale default: 0xff400000 */ 26 #define CONFIG_SYS_IMMR 0xff400000 27 28 /* System clock. Primary input clock when in PCI host mode */ 29 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ 30 31 /* 32 * Local Bus LCRR 33 * LCRR: DLL bypass, Clock divider is 8 34 * 35 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz 36 * 37 * External Local Bus rate is 38 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 39 */ 40 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 41 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 42 43 /* board pre init: do not call, nothing to do */ 44 45 /* detect the number of flash banks */ 46 #define CONFIG_BOARD_EARLY_INIT_R 47 48 /* 49 * DDR Setup 50 */ 51 /* DDR is system memory*/ 52 #define CONFIG_SYS_DDR_BASE 0x00000000 53 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 54 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 55 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ 56 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 57 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ 58 59 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 60 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 61 #define CONFIG_SYS_MEMTEST_END 0x00100000 62 63 /* 64 * FLASH on the Local Bus 65 */ 66 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 67 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 68 #undef CONFIG_SYS_FLASH_CHECKSUM 69 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ 70 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ 71 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ 72 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 73 74 /* 75 * FLASH bank number detection 76 */ 77 78 /* 79 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of 80 * Flash banks has to be determined at runtime and stored in a gloabl variable 81 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is 82 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array 83 * flash_info, and should be made sufficiently large to accomodate the number 84 * of banks that might actually be detected. Since most (all?) Flash related 85 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on 86 * the board, it is defined as tqm834x_num_flash_banks. 87 */ 88 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 89 90 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ 91 92 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ 93 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \ 94 | BR_MS_GPCM \ 95 | BR_PS_32 \ 96 | BR_V) 97 98 /* FLASH timing (0x0000_0c54) */ 99 #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \ 100 | OR_GPCM_ACS_DIV4 \ 101 | OR_GPCM_SCY_5 \ 102 | OR_GPCM_TRLX) 103 104 #define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */ 105 106 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ 107 | CONFIG_SYS_OR_TIMING_FLASH) 108 109 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB) 110 111 /* Window base at flash base */ 112 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 113 114 /* disable remaining mappings */ 115 #define CONFIG_SYS_BR1_PRELIM 0x00000000 116 #define CONFIG_SYS_OR1_PRELIM 0x00000000 117 #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000 118 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000 119 120 #define CONFIG_SYS_BR2_PRELIM 0x00000000 121 #define CONFIG_SYS_OR2_PRELIM 0x00000000 122 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000 123 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000 124 125 #define CONFIG_SYS_BR3_PRELIM 0x00000000 126 #define CONFIG_SYS_OR3_PRELIM 0x00000000 127 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000 128 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000 129 130 /* 131 * Monitor config 132 */ 133 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 134 135 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 136 # define CONFIG_SYS_RAMBOOT 137 #else 138 # undef CONFIG_SYS_RAMBOOT 139 #endif 140 141 #define CONFIG_SYS_INIT_RAM_LOCK 1 142 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ 143 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 144 145 #define CONFIG_SYS_GBL_DATA_OFFSET \ 146 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 147 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 148 149 /* Reserve 384 kB = 3 sect. for Mon */ 150 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 151 /* Reserve 512 kB for malloc */ 152 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 153 154 /* 155 * Serial Port 156 */ 157 #define CONFIG_CONS_INDEX 1 158 #define CONFIG_SYS_NS16550_SERIAL 159 #define CONFIG_SYS_NS16550_REG_SIZE 1 160 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 161 162 #define CONFIG_SYS_BAUDRATE_TABLE \ 163 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 164 165 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 166 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 167 168 /* 169 * I2C 170 */ 171 #define CONFIG_SYS_I2C 172 #define CONFIG_SYS_I2C_FSL 173 #define CONFIG_SYS_FSL_I2C_SPEED 400000 174 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 175 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 176 177 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ 178 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 179 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ 180 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ 181 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ 182 183 /* I2C RTC */ 184 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ 185 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 186 187 /* 188 * TSEC 189 */ 190 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 191 #define CONFIG_MII 192 193 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 194 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 195 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 196 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 197 198 #if defined(CONFIG_TSEC_ENET) 199 200 #define CONFIG_TSEC1 1 201 #define CONFIG_TSEC1_NAME "TSEC0" 202 #define CONFIG_TSEC2 1 203 #define CONFIG_TSEC2_NAME "TSEC1" 204 #define TSEC1_PHY_ADDR 2 205 #define TSEC2_PHY_ADDR 1 206 #define TSEC1_PHYIDX 0 207 #define TSEC2_PHYIDX 0 208 #define TSEC1_FLAGS TSEC_GIGABIT 209 #define TSEC2_FLAGS TSEC_GIGABIT 210 211 /* Options are: TSEC[0-1] */ 212 #define CONFIG_ETHPRIME "TSEC0" 213 214 #endif /* CONFIG_TSEC_ENET */ 215 216 #if defined(CONFIG_PCI) 217 218 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 219 220 /* PCI1 host bridge */ 221 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 222 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 223 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 224 #define CONFIG_SYS_PCI1_MMIO_BASE \ 225 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 226 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 227 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 228 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 229 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 230 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ 231 232 #undef CONFIG_EEPRO100 233 #define CONFIG_EEPRO100 234 #undef CONFIG_TULIP 235 236 #if !defined(CONFIG_PCI_PNP) 237 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE 238 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE 239 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ 240 #endif 241 242 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 243 244 #endif /* CONFIG_PCI */ 245 246 /* 247 * Environment 248 */ 249 #define CONFIG_ENV_ADDR \ 250 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 251 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ 252 #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */ 253 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 254 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 255 256 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 257 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 258 259 /* 260 * BOOTP options 261 */ 262 #define CONFIG_BOOTP_BOOTFILESIZE 263 #define CONFIG_BOOTP_BOOTPATH 264 #define CONFIG_BOOTP_GATEWAY 265 #define CONFIG_BOOTP_HOSTNAME 266 267 /* 268 * Miscellaneous configurable options 269 */ 270 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 271 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 272 273 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 274 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 275 276 #undef CONFIG_WATCHDOG /* watchdog disabled */ 277 278 /* 279 * For booting Linux, the board info and command line data 280 * have to be in the first 256 MB of memory, since this is 281 * the maximum mapped by the Linux kernel during initialization. 282 */ 283 /* Initial Memory map for Linux */ 284 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 285 286 #define CONFIG_SYS_HRCW_LOW (\ 287 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 288 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 289 HRCWL_CSB_TO_CLKIN_4X1 |\ 290 HRCWL_VCO_1X2 |\ 291 HRCWL_CORE_TO_CSB_2X1) 292 293 #if defined(PCI_64BIT) 294 #define CONFIG_SYS_HRCW_HIGH (\ 295 HRCWH_PCI_HOST |\ 296 HRCWH_64_BIT_PCI |\ 297 HRCWH_PCI1_ARBITER_ENABLE |\ 298 HRCWH_PCI2_ARBITER_DISABLE |\ 299 HRCWH_CORE_ENABLE |\ 300 HRCWH_FROM_0X00000100 |\ 301 HRCWH_BOOTSEQ_DISABLE |\ 302 HRCWH_SW_WATCHDOG_DISABLE |\ 303 HRCWH_ROM_LOC_LOCAL_16BIT |\ 304 HRCWH_TSEC1M_IN_GMII |\ 305 HRCWH_TSEC2M_IN_GMII) 306 #else 307 #define CONFIG_SYS_HRCW_HIGH (\ 308 HRCWH_PCI_HOST |\ 309 HRCWH_32_BIT_PCI |\ 310 HRCWH_PCI1_ARBITER_ENABLE |\ 311 HRCWH_PCI2_ARBITER_DISABLE |\ 312 HRCWH_CORE_ENABLE |\ 313 HRCWH_FROM_0X00000100 |\ 314 HRCWH_BOOTSEQ_DISABLE |\ 315 HRCWH_SW_WATCHDOG_DISABLE |\ 316 HRCWH_ROM_LOC_LOCAL_16BIT |\ 317 HRCWH_TSEC1M_IN_GMII |\ 318 HRCWH_TSEC2M_IN_GMII) 319 #endif 320 321 /* System IO Config */ 322 #define CONFIG_SYS_SICRH 0 323 #define CONFIG_SYS_SICRL SICRL_LDP_A 324 325 /* i-cache and d-cache disabled */ 326 #define CONFIG_SYS_HID0_INIT 0x000000000 327 #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ 328 HID0_ENABLE_INSTRUCTION_CACHE) 329 #define CONFIG_SYS_HID2 HID2_HBE 330 331 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 332 333 /* DDR 0 - 512M */ 334 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 335 | BATL_PP_RW \ 336 | BATL_MEMCOHERENCE) 337 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 338 | BATU_BL_256M \ 339 | BATU_VS \ 340 | BATU_VP) 341 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 342 | BATL_PP_RW \ 343 | BATL_MEMCOHERENCE) 344 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 345 | BATU_BL_256M \ 346 | BATU_VS \ 347 | BATU_VP) 348 349 /* stack in DCACHE @ 512M (no backing mem) */ 350 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ 351 | BATL_PP_RW \ 352 | BATL_MEMCOHERENCE) 353 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ 354 | BATU_BL_128K \ 355 | BATU_VS \ 356 | BATU_VP) 357 358 /* PCI */ 359 #ifdef CONFIG_PCI 360 #define CONFIG_PCI_INDIRECT_BRIDGE 361 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \ 362 | BATL_PP_RW \ 363 | BATL_MEMCOHERENCE) 364 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \ 365 | BATU_BL_256M \ 366 | BATU_VS \ 367 | BATU_VP) 368 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \ 369 | BATL_PP_RW \ 370 | BATL_MEMCOHERENCE \ 371 | BATL_GUARDEDSTORAGE) 372 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \ 373 | BATU_BL_256M \ 374 | BATU_VS \ 375 | BATU_VP) 376 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \ 377 | BATL_PP_RW \ 378 | BATL_CACHEINHIBIT \ 379 | BATL_GUARDEDSTORAGE) 380 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \ 381 | BATU_BL_16M \ 382 | BATU_VS \ 383 | BATU_VP) 384 #else 385 #define CONFIG_SYS_IBAT3L (0) 386 #define CONFIG_SYS_IBAT3U (0) 387 #define CONFIG_SYS_IBAT4L (0) 388 #define CONFIG_SYS_IBAT4U (0) 389 #define CONFIG_SYS_IBAT5L (0) 390 #define CONFIG_SYS_IBAT5U (0) 391 #endif 392 393 /* IMMRBAR */ 394 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \ 395 | BATL_PP_RW \ 396 | BATL_CACHEINHIBIT \ 397 | BATL_GUARDEDSTORAGE) 398 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \ 399 | BATU_BL_1M \ 400 | BATU_VS \ 401 | BATU_VP) 402 403 /* FLASH */ 404 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \ 405 | BATL_PP_RW \ 406 | BATL_CACHEINHIBIT \ 407 | BATL_GUARDEDSTORAGE) 408 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \ 409 | BATU_BL_256M \ 410 | BATU_VS \ 411 | BATU_VP) 412 413 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 414 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 415 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 416 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 417 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 418 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 419 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 420 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 421 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 422 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 423 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 424 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 425 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 426 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 427 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 428 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 429 430 #if defined(CONFIG_CMD_KGDB) 431 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 432 #endif 433 434 /* 435 * Environment Configuration 436 */ 437 438 /* default location for tftp and bootm */ 439 #define CONFIG_LOADADDR 400000 440 441 #define CONFIG_PREBOOT "echo;" \ 442 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 443 "echo" 444 445 #define CONFIG_EXTRA_ENV_SETTINGS \ 446 "netdev=eth0\0" \ 447 "hostname=tqm834x\0" \ 448 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 449 "nfsroot=${serverip}:${rootpath}\0" \ 450 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 451 "addip=setenv bootargs ${bootargs} " \ 452 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 453 ":${hostname}:${netdev}:off panic=1\0" \ 454 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ 455 "flash_nfs_old=run nfsargs addip addcons;" \ 456 "bootm ${kernel_addr}\0" \ 457 "flash_nfs=run nfsargs addip addcons;" \ 458 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 459 "flash_self_old=run ramargs addip addcons;" \ 460 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 461 "flash_self=run ramargs addip addcons;" \ 462 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 463 "net_nfs_old=tftp 400000 ${bootfile};" \ 464 "run nfsargs addip addcons;bootm\0" \ 465 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 466 "tftp ${fdt_addr_r} ${fdt_file}; " \ 467 "run nfsargs addip addcons; " \ 468 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 469 "rootpath=/opt/eldk/ppc_6xx\0" \ 470 "bootfile=tqm834x/uImage\0" \ 471 "fdtfile=tqm834x/tqm834x.dtb\0" \ 472 "kernel_addr_r=400000\0" \ 473 "fdt_addr_r=600000\0" \ 474 "ramdisk_addr_r=800000\0" \ 475 "kernel_addr=800C0000\0" \ 476 "fdt_addr=800A0000\0" \ 477 "ramdisk_addr=80300000\0" \ 478 "u-boot=tqm834x/u-boot.bin\0" \ 479 "load=tftp 200000 ${u-boot}\0" \ 480 "update=protect off 80000000 +${filesize};" \ 481 "era 80000000 +${filesize};" \ 482 "cp.b 200000 80000000 ${filesize}\0" \ 483 "upd=run load update\0" \ 484 "" 485 486 #define CONFIG_BOOTCOMMAND "run flash_self" 487 488 /* 489 * JFFS2 partitions 490 */ 491 /* mtdparts command line support */ 492 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 493 #define CONFIG_FLASH_CFI_MTD 494 #define MTDIDS_DEFAULT "nor0=TQM834x-0" 495 496 /* default mtd partition table */ 497 #define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \ 498 "1m(kernel),2m(initrd)," \ 499 "-(user);" \ 500 501 #endif /* __CONFIG_H */ 502