xref: /openbmc/u-boot/include/configs/TQM834x.h (revision 2e6e1772c0e34871769be4aef79748fe3e47d953)
1 /*
2  * (C) Copyright 2005
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23 
24 /*
25  * TQM8349 board configuration file
26  */
27 
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
30 
31 /*
32  * High Level Configuration Options
33  */
34 #define CONFIG_E300		1	/* E300 Family */
35 #define CONFIG_MPC83xx		1	/* MPC83xx family */
36 #define CONFIG_MPC834x		1	/* MPC834x specific */
37 #define CONFIG_MPC8349		1	/* MPC8349 specific */
38 #define CONFIG_TQM834X		1	/* TQM834X board specific */
39 
40 /* IMMR Base Addres Register, use Freescale default: 0xff400000 */
41 #define CONFIG_SYS_IMMR		0xff400000
42 
43 /* System clock. Primary input clock when in PCI host mode */
44 #define CONFIG_83XX_CLKIN	66666000	/* 66,666 MHz */
45 
46 /*
47  * Local Bus LCRR
48  *    LCRR:  DLL bypass, Clock divider is 8
49  *
50  *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
51  *
52  * External Local Bus rate is
53  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
54  */
55 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
56 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
57 
58 /* board pre init: do not call, nothing to do */
59 #undef CONFIG_BOARD_EARLY_INIT_F
60 
61 /* detect the number of flash banks */
62 #define CONFIG_BOARD_EARLY_INIT_R
63 
64 /*
65  * DDR Setup
66  */
67 #define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
68 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
69 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
70 #define DDR_CASLAT_25				/* CASLAT set to 2.5 */
71 #undef CONFIG_DDR_ECC				/* only for ECC DDR module */
72 #undef CONFIG_SPD_EEPROM			/* do not use SPD EEPROM for DDR setup */
73 
74 #undef CONFIG_SYS_DRAM_TEST				/* memory test, takes time */
75 #define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
76 #define CONFIG_SYS_MEMTEST_END		0x00100000
77 
78 /*
79  * FLASH on the Local Bus
80  */
81 #define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
82 #define CONFIG_FLASH_CFI_DRIVER				/* use the CFI driver */
83 #undef CONFIG_SYS_FLASH_CHECKSUM
84 #define CONFIG_SYS_FLASH_BASE		0x80000000	/* start of FLASH   */
85 #define CONFIG_SYS_FLASH_SIZE		8		/* FLASH size in MB */
86 #define CONFIG_SYS_FLASH_EMPTY_INFO			/* print 'E' for empty sectors */
87 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
88 
89 /*
90  * FLASH bank number detection
91  */
92 
93 /*
94  * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
95  * banks has to be determined at runtime and stored in a gloabl variable
96  * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is only
97  * used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array flash_info, and
98  * should be made sufficiently large to accomodate the number of banks that
99  * might actually be detected.  Since most (all?) Flash related functions use
100  * CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on the board, it is
101  * defined as tqm834x_num_flash_banks.
102  */
103 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	2
104 
105 #define CONFIG_SYS_MAX_FLASH_SECT		512	/* max sectors per device */
106 
107 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
108 #define CONFIG_SYS_BR0_PRELIM		((CONFIG_SYS_FLASH_BASE & BR_BA) | \
109 					BR_MS_GPCM | BR_PS_32 | BR_V)
110 
111 /* FLASH timing (0x0000_0c54) */
112 #define CONFIG_SYS_OR_TIMING_FLASH	(OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
113 					OR_GPCM_SCY_5 | OR_GPCM_TRLX)
114 
115 #define CONFIG_SYS_PRELIM_OR_AM	0xc0000000	/* OR addr mask: 1 GiB */
116 
117 #define CONFIG_SYS_OR0_PRELIM		(CONFIG_SYS_PRELIM_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
118 
119 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x8000001D	/* 1 GiB window size (2^(size + 1)) */
120 
121 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE	/* Window base at flash base */
122 
123 /* disable remaining mappings */
124 #define CONFIG_SYS_BR1_PRELIM		0x00000000
125 #define CONFIG_SYS_OR1_PRELIM		0x00000000
126 #define CONFIG_SYS_LBLAWBAR1_PRELIM	0x00000000
127 #define CONFIG_SYS_LBLAWAR1_PRELIM	0x00000000
128 
129 #define CONFIG_SYS_BR2_PRELIM		0x00000000
130 #define CONFIG_SYS_OR2_PRELIM		0x00000000
131 #define CONFIG_SYS_LBLAWBAR2_PRELIM	0x00000000
132 #define CONFIG_SYS_LBLAWAR2_PRELIM	0x00000000
133 
134 #define CONFIG_SYS_BR3_PRELIM		0x00000000
135 #define CONFIG_SYS_OR3_PRELIM		0x00000000
136 #define CONFIG_SYS_LBLAWBAR3_PRELIM	0x00000000
137 #define CONFIG_SYS_LBLAWAR3_PRELIM	0x00000000
138 
139 /*
140  * Monitor config
141  */
142 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
143 
144 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
145 # define CONFIG_SYS_RAMBOOT
146 #else
147 # undef  CONFIG_SYS_RAMBOOT
148 #endif
149 
150 #define CONFIG_SYS_INIT_RAM_LOCK	1
151 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000	/* Initial RAM address */
152 #define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
153 
154 #define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
155 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
156 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
157 
158 #define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 384 kB = 3 sect. for Mon */
159 #define CONFIG_SYS_MALLOC_LEN		(512 * 1024) /* Reserve 512 kB for malloc */
160 
161 /*
162  * Serial Port
163  */
164 #define CONFIG_CONS_INDEX	1
165 #define CONFIG_SYS_NS16550
166 #define CONFIG_SYS_NS16550_SERIAL
167 #define CONFIG_SYS_NS16550_REG_SIZE	1
168 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
169 
170 #define CONFIG_SYS_BAUDRATE_TABLE  \
171 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
172 
173 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
174 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
175 
176 /*
177  * I2C
178  */
179 #define CONFIG_HARD_I2C				/* I2C with hardware support	*/
180 #undef CONFIG_SOFT_I2C				/* I2C bit-banged		*/
181 #define CONFIG_FSL_I2C
182 #define CONFIG_SYS_I2C_SPEED			400000	/* I2C speed: 400KHz		*/
183 #define CONFIG_SYS_I2C_SLAVE			0x7F	/* slave address		*/
184 #define CONFIG_SYS_I2C_OFFSET			0x3000
185 
186 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
187 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x			*/
188 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16 bit			*/
189 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 32 bytes per write		*/
190 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	12	/* 10ms +/- 20%			*/
191 #define CONFIG_SYS_I2C_MULTI_EEPROMS		1       /* more than one eeprom		*/
192 
193 /* I2C RTC */
194 #define CONFIG_RTC_DS1337			/* use ds1337 rtc via i2c	*/
195 #define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
196 
197 /* I2C SYSMON (LM75) */
198 #define CONFIG_DTT_LM75			1	/* ON Semi's LM75		*/
199 #define CONFIG_DTT_SENSORS		{0}	/* Sensor addresses		*/
200 #define CONFIG_SYS_DTT_MAX_TEMP		70
201 #define CONFIG_SYS_DTT_LOW_TEMP		-30
202 #define CONFIG_SYS_DTT_HYSTERESIS		3
203 
204 /*
205  * TSEC
206  */
207 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
208 #define CONFIG_MII
209 
210 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
211 #define CONFIG_SYS_TSEC1		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
212 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
213 #define CONFIG_SYS_TSEC2		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
214 
215 #if defined(CONFIG_TSEC_ENET)
216 
217 #ifndef CONFIG_NET_MULTI
218 #define CONFIG_NET_MULTI
219 #endif
220 
221 #define CONFIG_TSEC1		1
222 #define CONFIG_TSEC1_NAME	"TSEC0"
223 #define CONFIG_TSEC2		1
224 #define CONFIG_TSEC2_NAME	"TSEC1"
225 #define TSEC1_PHY_ADDR			2
226 #define TSEC2_PHY_ADDR			1
227 #define TSEC1_PHYIDX			0
228 #define TSEC2_PHYIDX			0
229 #define TSEC1_FLAGS		TSEC_GIGABIT
230 #define TSEC2_FLAGS		TSEC_GIGABIT
231 
232 /* Options are: TSEC[0-1] */
233 #define CONFIG_ETHPRIME			"TSEC0"
234 
235 #endif	/* CONFIG_TSEC_ENET */
236 
237 /*
238  * General PCI
239  * Addresses are mapped 1-1.
240  */
241 #define CONFIG_PCI
242 
243 #if defined(CONFIG_PCI)
244 
245 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
246 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
247 
248 /* PCI1 host bridge */
249 #define CONFIG_SYS_PCI1_MEM_BASE       0x90000000
250 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BASE
251 #define CONFIG_SYS_PCI1_MEM_SIZE       0x10000000      /* 256M */
252 #define CONFIG_SYS_PCI1_MMIO_BASE      (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
253 #define CONFIG_SYS_PCI1_MMIO_PHYS      CONFIG_SYS_PCI1_MMIO_BASE
254 #define CONFIG_SYS_PCI1_MMIO_SIZE      0x10000000     /* 256M */
255 #define CONFIG_SYS_PCI1_IO_BASE        0xe2000000
256 #define CONFIG_SYS_PCI1_IO_PHYS        CONFIG_SYS_PCI1_IO_BASE
257 #define CONFIG_SYS_PCI1_IO_SIZE        0x1000000       /* 16M */
258 
259 #undef CONFIG_EEPRO100
260 #define CONFIG_EEPRO100
261 #undef CONFIG_TULIP
262 
263 #if !defined(CONFIG_PCI_PNP)
264 	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BASE
265 	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_MEM_BASE
266 	#define PCI_IDSEL_NUMBER	0x1c    /* slot0 (IDSEL) = 28 */
267 #endif
268 
269 #define CONFIG_SYS_PCI_SUBSYS_VENDORID		0x1957  /* Freescale */
270 
271 #endif	/* CONFIG_PCI */
272 
273 /*
274  * Environment
275  */
276 #define CONFIG_ENV_IS_IN_FLASH		1
277 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
278 #define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K (one sector) for env */
279 #define CONFIG_ENV_SIZE			0x8000	/*  32K max size */
280 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
281 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
282 
283 #define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
284 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
285 
286 /*
287  * BOOTP options
288  */
289 #define CONFIG_BOOTP_BOOTFILESIZE
290 #define CONFIG_BOOTP_BOOTPATH
291 #define CONFIG_BOOTP_GATEWAY
292 #define CONFIG_BOOTP_HOSTNAME
293 
294 
295 /*
296  * Command line configuration.
297  */
298 #include <config_cmd_default.h>
299 
300 #define CONFIG_CMD_ASKENV
301 #define CONFIG_CMD_DATE
302 #define CONFIG_CMD_DHCP
303 #define CONFIG_CMD_DTT
304 #define CONFIG_CMD_EEPROM
305 #define CONFIG_CMD_I2C
306 #define CONFIG_CMD_NFS
307 #define CONFIG_CMD_JFFS2
308 #define CONFIG_CMD_MII
309 #define CONFIG_CMD_PING
310 #define CONFIG_CMD_REGINFO
311 #define CONFIG_CMD_SNTP
312 
313 #if defined(CONFIG_PCI)
314     #define CONFIG_CMD_PCI
315 #endif
316 
317 #if defined(CONFIG_SYS_RAMBOOT)
318     #undef CONFIG_CMD_SAVEENV
319     #undef CONFIG_CMD_LOADS
320 #endif
321 
322 /*
323  * Miscellaneous configurable options
324  */
325 #define CONFIG_SYS_LONGHELP				/* undef to save memory	*/
326 #define CONFIG_SYS_LOAD_ADDR		0x2000000	/* default load address */
327 #define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
328 
329 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
330 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
331 
332 #define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
333 #ifdef	CONFIG_SYS_HUSH_PARSER
334 #define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
335 #endif
336 
337 #if defined(CONFIG_CMD_KGDB)
338 	#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
339 #else
340 	#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
341 #endif
342 
343 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
344 #define CONFIG_SYS_MAXARGS		16		/* max number of command args */
345 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
346 #define CONFIG_SYS_HZ			1000		/* decrementer freq: 1ms ticks */
347 
348 #undef CONFIG_WATCHDOG				/* watchdog disabled */
349 
350 /* pass open firmware flat tree */
351 #define CONFIG_OF_LIBFDT	1
352 #define CONFIG_OF_BOARD_SETUP	1
353 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
354 
355 /*
356  * For booting Linux, the board info and command line data
357  * have to be in the first 256 MB of memory, since this is
358  * the maximum mapped by the Linux kernel during initialization.
359  */
360 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Initial Memory map for Linux*/
361 
362 #define CONFIG_SYS_HRCW_LOW (\
363 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
364 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
365 	HRCWL_CSB_TO_CLKIN_4X1 |\
366 	HRCWL_VCO_1X2 |\
367 	HRCWL_CORE_TO_CSB_2X1)
368 
369 #if defined(PCI_64BIT)
370 #define CONFIG_SYS_HRCW_HIGH (\
371 	HRCWH_PCI_HOST |\
372 	HRCWH_64_BIT_PCI |\
373 	HRCWH_PCI1_ARBITER_ENABLE |\
374 	HRCWH_PCI2_ARBITER_DISABLE |\
375 	HRCWH_CORE_ENABLE |\
376 	HRCWH_FROM_0X00000100 |\
377 	HRCWH_BOOTSEQ_DISABLE |\
378 	HRCWH_SW_WATCHDOG_DISABLE |\
379 	HRCWH_ROM_LOC_LOCAL_16BIT |\
380 	HRCWH_TSEC1M_IN_GMII |\
381 	HRCWH_TSEC2M_IN_GMII )
382 #else
383 #define CONFIG_SYS_HRCW_HIGH (\
384 	HRCWH_PCI_HOST |\
385 	HRCWH_32_BIT_PCI |\
386 	HRCWH_PCI1_ARBITER_ENABLE |\
387 	HRCWH_PCI2_ARBITER_DISABLE |\
388 	HRCWH_CORE_ENABLE |\
389 	HRCWH_FROM_0X00000100 |\
390 	HRCWH_BOOTSEQ_DISABLE |\
391 	HRCWH_SW_WATCHDOG_DISABLE |\
392 	HRCWH_ROM_LOC_LOCAL_16BIT |\
393 	HRCWH_TSEC1M_IN_GMII |\
394 	HRCWH_TSEC2M_IN_GMII )
395 #endif
396 
397 /* System IO Config */
398 #define CONFIG_SYS_SICRH	0
399 #define CONFIG_SYS_SICRL	SICRL_LDP_A
400 
401 /* i-cache and d-cache disabled */
402 #define CONFIG_SYS_HID0_INIT	0x000000000
403 #define CONFIG_SYS_HID0_FINAL	(CONFIG_SYS_HID0_INIT | \
404 				 HID0_ENABLE_INSTRUCTION_CACHE)
405 #define CONFIG_SYS_HID2	HID2_HBE
406 
407 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
408 
409 /* DDR 0 - 512M */
410 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
411 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
412 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
413 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
414 
415 /* stack in DCACHE @ 512M (no backing mem) */
416 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
417 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
418 
419 /* PCI */
420 #ifdef CONFIG_PCI
421 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
422 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
423 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE)
424 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
425 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
426 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI1_IO_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
427 #else
428 #define CONFIG_SYS_IBAT3L	(0)
429 #define CONFIG_SYS_IBAT3U	(0)
430 #define CONFIG_SYS_IBAT4L	(0)
431 #define CONFIG_SYS_IBAT4U	(0)
432 #define CONFIG_SYS_IBAT5L	(0)
433 #define CONFIG_SYS_IBAT5U	(0)
434 #endif
435 
436 /* IMMRBAR */
437 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
438 #define CONFIG_SYS_IBAT6U	(CONFIG_SYS_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
439 
440 /* FLASH */
441 #define CONFIG_SYS_IBAT7L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
442 #define CONFIG_SYS_IBAT7U	(CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
443 
444 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
445 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
446 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
447 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
448 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
449 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
450 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
451 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
452 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
453 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
454 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
455 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
456 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
457 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
458 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
459 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
460 
461 /*
462  * Internal Definitions
463  *
464  * Boot Flags
465  */
466 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
467 #define BOOTFLAG_WARM		0x02	/* Software reboot */
468 
469 #if defined(CONFIG_CMD_KGDB)
470 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
471 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
472 #endif
473 
474 /*
475  * Environment Configuration
476  */
477 
478 #define CONFIG_LOADADDR		400000	/* default location for tftp and bootm */
479 
480 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
481 #undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
482 
483 #define CONFIG_BAUDRATE		115200
484 
485 #define CONFIG_PREBOOT	"echo;"	\
486 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
487 	"echo"
488 
489 #undef	CONFIG_BOOTARGS
490 
491 #define	CONFIG_EXTRA_ENV_SETTINGS					\
492 	"netdev=eth0\0"							\
493 	"hostname=tqm834x\0"						\
494 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
495 		"nfsroot=${serverip}:${rootpath}\0"			\
496 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
497 	"addip=setenv bootargs ${bootargs} "				\
498 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
499 		":${hostname}:${netdev}:off panic=1\0"			\
500 	"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
501 	"flash_nfs_old=run nfsargs addip addcons;"			\
502 		"bootm ${kernel_addr}\0"				\
503 	"flash_nfs=run nfsargs addip addcons;"				\
504 		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
505 	"flash_self_old=run ramargs addip addcons;"			\
506 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
507 	"flash_self=run ramargs addip addcons;"				\
508 		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
509 	"net_nfs_old=tftp 400000 ${bootfile};"				\
510 		"run nfsargs addip addcons;bootm\0"			\
511 	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
512 		"tftp ${fdt_addr_r} ${fdt_file}; "			\
513 		"run nfsargs addip addcons; "				\
514 		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
515 	"rootpath=/opt/eldk/ppc_6xx\0"					\
516 	"bootfile=tqm834x/uImage\0"					\
517 	"fdtfile=tqm834x/tqm834x.dtb\0"					\
518 	"kernel_addr_r=400000\0"					\
519 	"fdt_addr_r=600000\0"						\
520 	"ramdisk_addr_r=800000\0"					\
521 	"kernel_addr=800C0000\0"					\
522 	"fdt_addr=800A0000\0"						\
523 	"ramdisk_addr=80300000\0"					\
524 	"u-boot=tqm834x/u-boot.bin\0"					\
525 	"load=tftp 200000 ${u-boot}\0"					\
526 	"update=protect off 80000000 +${filesize};"			\
527 		"era 80000000 +${filesize};"				\
528 		"cp.b 200000 80000000 ${filesize}\0"			\
529 	"upd=run load update\0"						\
530 	""
531 
532 #define CONFIG_BOOTCOMMAND	"run flash_self"
533 
534 /*
535  * JFFS2 partitions
536  */
537 /* mtdparts command line support */
538 #define CONFIG_CMD_MTDPARTS
539 #define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
540 #define CONFIG_FLASH_CFI_MTD
541 #define MTDIDS_DEFAULT		"nor0=TQM834x-0"
542 
543 /* default mtd partition table */
544 #define MTDPARTS_DEFAULT	"mtdparts=TQM834x-0:256k(u-boot),256k(env),"\
545 						"1m(kernel),2m(initrd),"\
546 						"-(user);"\
547 
548 #endif	/* __CONFIG_H */
549