1 /* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * TQM8349 board configuration file 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 #define CONFIG_E300 1 /* E300 Family */ 19 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 20 #define CONFIG_MPC834x 1 /* MPC834x specific */ 21 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 22 #define CONFIG_TQM834X 1 /* TQM834X board specific */ 23 24 #define CONFIG_SYS_TEXT_BASE 0x80000000 25 26 /* IMMR Base Address Register, use Freescale default: 0xff400000 */ 27 #define CONFIG_SYS_IMMR 0xff400000 28 29 /* System clock. Primary input clock when in PCI host mode */ 30 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ 31 32 /* 33 * Local Bus LCRR 34 * LCRR: DLL bypass, Clock divider is 8 35 * 36 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz 37 * 38 * External Local Bus rate is 39 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 40 */ 41 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 42 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 43 44 /* board pre init: do not call, nothing to do */ 45 #undef CONFIG_BOARD_EARLY_INIT_F 46 47 /* detect the number of flash banks */ 48 #define CONFIG_BOARD_EARLY_INIT_R 49 50 /* 51 * DDR Setup 52 */ 53 /* DDR is system memory*/ 54 #define CONFIG_SYS_DDR_BASE 0x00000000 55 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 56 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 57 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ 58 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 59 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ 60 61 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 62 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 63 #define CONFIG_SYS_MEMTEST_END 0x00100000 64 65 /* 66 * FLASH on the Local Bus 67 */ 68 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 69 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 70 #undef CONFIG_SYS_FLASH_CHECKSUM 71 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ 72 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ 73 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ 74 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 75 76 /* 77 * FLASH bank number detection 78 */ 79 80 /* 81 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of 82 * Flash banks has to be determined at runtime and stored in a gloabl variable 83 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is 84 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array 85 * flash_info, and should be made sufficiently large to accomodate the number 86 * of banks that might actually be detected. Since most (all?) Flash related 87 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on 88 * the board, it is defined as tqm834x_num_flash_banks. 89 */ 90 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 91 92 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ 93 94 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ 95 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \ 96 | BR_MS_GPCM \ 97 | BR_PS_32 \ 98 | BR_V) 99 100 /* FLASH timing (0x0000_0c54) */ 101 #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \ 102 | OR_GPCM_ACS_DIV4 \ 103 | OR_GPCM_SCY_5 \ 104 | OR_GPCM_TRLX) 105 106 #define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */ 107 108 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ 109 | CONFIG_SYS_OR_TIMING_FLASH) 110 111 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB) 112 113 /* Window base at flash base */ 114 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 115 116 /* disable remaining mappings */ 117 #define CONFIG_SYS_BR1_PRELIM 0x00000000 118 #define CONFIG_SYS_OR1_PRELIM 0x00000000 119 #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000 120 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000 121 122 #define CONFIG_SYS_BR2_PRELIM 0x00000000 123 #define CONFIG_SYS_OR2_PRELIM 0x00000000 124 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000 125 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000 126 127 #define CONFIG_SYS_BR3_PRELIM 0x00000000 128 #define CONFIG_SYS_OR3_PRELIM 0x00000000 129 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000 130 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000 131 132 /* 133 * Monitor config 134 */ 135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 136 137 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 138 # define CONFIG_SYS_RAMBOOT 139 #else 140 # undef CONFIG_SYS_RAMBOOT 141 #endif 142 143 #define CONFIG_SYS_INIT_RAM_LOCK 1 144 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ 145 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 146 147 #define CONFIG_SYS_GBL_DATA_OFFSET \ 148 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 149 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 150 151 /* Reserve 384 kB = 3 sect. for Mon */ 152 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 153 /* Reserve 512 kB for malloc */ 154 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 155 156 /* 157 * Serial Port 158 */ 159 #define CONFIG_CONS_INDEX 1 160 #define CONFIG_SYS_NS16550 161 #define CONFIG_SYS_NS16550_SERIAL 162 #define CONFIG_SYS_NS16550_REG_SIZE 1 163 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 164 165 #define CONFIG_SYS_BAUDRATE_TABLE \ 166 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 167 168 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 169 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 170 171 /* 172 * I2C 173 */ 174 #define CONFIG_SYS_I2C 175 #define CONFIG_SYS_I2C_FSL 176 #define CONFIG_SYS_FSL_I2C_SPEED 400000 177 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 178 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 179 180 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ 181 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 182 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ 183 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ 184 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ 185 #define CONFIG_SYS_I2C_MULTI_EEPROMS /* more than one eeprom */ 186 187 /* I2C RTC */ 188 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ 189 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 190 191 /* I2C SYSMON (LM75) */ 192 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ 193 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ 194 #define CONFIG_SYS_DTT_MAX_TEMP 70 195 #define CONFIG_SYS_DTT_LOW_TEMP -30 196 #define CONFIG_SYS_DTT_HYSTERESIS 3 197 198 /* 199 * TSEC 200 */ 201 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 202 #define CONFIG_MII 203 204 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 205 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 206 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 207 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 208 209 #if defined(CONFIG_TSEC_ENET) 210 211 #define CONFIG_TSEC1 1 212 #define CONFIG_TSEC1_NAME "TSEC0" 213 #define CONFIG_TSEC2 1 214 #define CONFIG_TSEC2_NAME "TSEC1" 215 #define TSEC1_PHY_ADDR 2 216 #define TSEC2_PHY_ADDR 1 217 #define TSEC1_PHYIDX 0 218 #define TSEC2_PHYIDX 0 219 #define TSEC1_FLAGS TSEC_GIGABIT 220 #define TSEC2_FLAGS TSEC_GIGABIT 221 222 /* Options are: TSEC[0-1] */ 223 #define CONFIG_ETHPRIME "TSEC0" 224 225 #endif /* CONFIG_TSEC_ENET */ 226 227 /* 228 * General PCI 229 * Addresses are mapped 1-1. 230 */ 231 #define CONFIG_PCI 232 233 #if defined(CONFIG_PCI) 234 235 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 236 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 237 238 /* PCI1 host bridge */ 239 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 240 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 241 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 242 #define CONFIG_SYS_PCI1_MMIO_BASE \ 243 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 244 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 245 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 246 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 247 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 248 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ 249 250 #undef CONFIG_EEPRO100 251 #define CONFIG_EEPRO100 252 #undef CONFIG_TULIP 253 254 #if !defined(CONFIG_PCI_PNP) 255 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE 256 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE 257 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ 258 #endif 259 260 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 261 262 #endif /* CONFIG_PCI */ 263 264 /* 265 * Environment 266 */ 267 #define CONFIG_ENV_IS_IN_FLASH 1 268 #define CONFIG_ENV_ADDR \ 269 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 270 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ 271 #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */ 272 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 273 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 274 275 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 276 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 277 278 /* 279 * BOOTP options 280 */ 281 #define CONFIG_BOOTP_BOOTFILESIZE 282 #define CONFIG_BOOTP_BOOTPATH 283 #define CONFIG_BOOTP_GATEWAY 284 #define CONFIG_BOOTP_HOSTNAME 285 286 287 /* 288 * Command line configuration. 289 */ 290 #include <config_cmd_default.h> 291 292 #define CONFIG_CMD_ASKENV 293 #define CONFIG_CMD_DATE 294 #define CONFIG_CMD_DHCP 295 #define CONFIG_CMD_DTT 296 #define CONFIG_CMD_EEPROM 297 #define CONFIG_CMD_I2C 298 #define CONFIG_CMD_NFS 299 #define CONFIG_CMD_JFFS2 300 #define CONFIG_CMD_MII 301 #define CONFIG_CMD_PING 302 #define CONFIG_CMD_REGINFO 303 #define CONFIG_CMD_SNTP 304 305 #if defined(CONFIG_PCI) 306 #define CONFIG_CMD_PCI 307 #endif 308 309 #if defined(CONFIG_SYS_RAMBOOT) 310 #undef CONFIG_CMD_SAVEENV 311 #undef CONFIG_CMD_LOADS 312 #endif 313 314 /* 315 * Miscellaneous configurable options 316 */ 317 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 318 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 319 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 320 321 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 322 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 323 324 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 325 326 #if defined(CONFIG_CMD_KGDB) 327 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 328 #else 329 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 330 #endif 331 332 /* Print Buffer Size */ 333 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 334 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 335 /* Boot Argument Buffer Size */ 336 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 337 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 338 339 #undef CONFIG_WATCHDOG /* watchdog disabled */ 340 341 /* pass open firmware flat tree */ 342 #define CONFIG_OF_LIBFDT 1 343 #define CONFIG_OF_BOARD_SETUP 1 344 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 345 346 /* 347 * For booting Linux, the board info and command line data 348 * have to be in the first 256 MB of memory, since this is 349 * the maximum mapped by the Linux kernel during initialization. 350 */ 351 /* Initial Memory map for Linux */ 352 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 353 354 #define CONFIG_SYS_HRCW_LOW (\ 355 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 356 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 357 HRCWL_CSB_TO_CLKIN_4X1 |\ 358 HRCWL_VCO_1X2 |\ 359 HRCWL_CORE_TO_CSB_2X1) 360 361 #if defined(PCI_64BIT) 362 #define CONFIG_SYS_HRCW_HIGH (\ 363 HRCWH_PCI_HOST |\ 364 HRCWH_64_BIT_PCI |\ 365 HRCWH_PCI1_ARBITER_ENABLE |\ 366 HRCWH_PCI2_ARBITER_DISABLE |\ 367 HRCWH_CORE_ENABLE |\ 368 HRCWH_FROM_0X00000100 |\ 369 HRCWH_BOOTSEQ_DISABLE |\ 370 HRCWH_SW_WATCHDOG_DISABLE |\ 371 HRCWH_ROM_LOC_LOCAL_16BIT |\ 372 HRCWH_TSEC1M_IN_GMII |\ 373 HRCWH_TSEC2M_IN_GMII) 374 #else 375 #define CONFIG_SYS_HRCW_HIGH (\ 376 HRCWH_PCI_HOST |\ 377 HRCWH_32_BIT_PCI |\ 378 HRCWH_PCI1_ARBITER_ENABLE |\ 379 HRCWH_PCI2_ARBITER_DISABLE |\ 380 HRCWH_CORE_ENABLE |\ 381 HRCWH_FROM_0X00000100 |\ 382 HRCWH_BOOTSEQ_DISABLE |\ 383 HRCWH_SW_WATCHDOG_DISABLE |\ 384 HRCWH_ROM_LOC_LOCAL_16BIT |\ 385 HRCWH_TSEC1M_IN_GMII |\ 386 HRCWH_TSEC2M_IN_GMII) 387 #endif 388 389 /* System IO Config */ 390 #define CONFIG_SYS_SICRH 0 391 #define CONFIG_SYS_SICRL SICRL_LDP_A 392 393 /* i-cache and d-cache disabled */ 394 #define CONFIG_SYS_HID0_INIT 0x000000000 395 #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ 396 HID0_ENABLE_INSTRUCTION_CACHE) 397 #define CONFIG_SYS_HID2 HID2_HBE 398 399 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 400 401 /* DDR 0 - 512M */ 402 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 403 | BATL_PP_RW \ 404 | BATL_MEMCOHERENCE) 405 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 406 | BATU_BL_256M \ 407 | BATU_VS \ 408 | BATU_VP) 409 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 410 | BATL_PP_RW \ 411 | BATL_MEMCOHERENCE) 412 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 413 | BATU_BL_256M \ 414 | BATU_VS \ 415 | BATU_VP) 416 417 /* stack in DCACHE @ 512M (no backing mem) */ 418 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ 419 | BATL_PP_RW \ 420 | BATL_MEMCOHERENCE) 421 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ 422 | BATU_BL_128K \ 423 | BATU_VS \ 424 | BATU_VP) 425 426 /* PCI */ 427 #ifdef CONFIG_PCI 428 #define CONFIG_PCI_INDIRECT_BRIDGE 429 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \ 430 | BATL_PP_RW \ 431 | BATL_MEMCOHERENCE) 432 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \ 433 | BATU_BL_256M \ 434 | BATU_VS \ 435 | BATU_VP) 436 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \ 437 | BATL_PP_RW \ 438 | BATL_MEMCOHERENCE \ 439 | BATL_GUARDEDSTORAGE) 440 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \ 441 | BATU_BL_256M \ 442 | BATU_VS \ 443 | BATU_VP) 444 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \ 445 | BATL_PP_RW \ 446 | BATL_CACHEINHIBIT \ 447 | BATL_GUARDEDSTORAGE) 448 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \ 449 | BATU_BL_16M \ 450 | BATU_VS \ 451 | BATU_VP) 452 #else 453 #define CONFIG_SYS_IBAT3L (0) 454 #define CONFIG_SYS_IBAT3U (0) 455 #define CONFIG_SYS_IBAT4L (0) 456 #define CONFIG_SYS_IBAT4U (0) 457 #define CONFIG_SYS_IBAT5L (0) 458 #define CONFIG_SYS_IBAT5U (0) 459 #endif 460 461 /* IMMRBAR */ 462 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \ 463 | BATL_PP_RW \ 464 | BATL_CACHEINHIBIT \ 465 | BATL_GUARDEDSTORAGE) 466 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \ 467 | BATU_BL_1M \ 468 | BATU_VS \ 469 | BATU_VP) 470 471 /* FLASH */ 472 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \ 473 | BATL_PP_RW \ 474 | BATL_CACHEINHIBIT \ 475 | BATL_GUARDEDSTORAGE) 476 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \ 477 | BATU_BL_256M \ 478 | BATU_VS \ 479 | BATU_VP) 480 481 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 482 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 483 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 484 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 485 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 486 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 487 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 488 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 489 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 490 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 491 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 492 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 493 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 494 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 495 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 496 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 497 498 #if defined(CONFIG_CMD_KGDB) 499 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 500 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 501 #endif 502 503 /* 504 * Environment Configuration 505 */ 506 507 /* default location for tftp and bootm */ 508 #define CONFIG_LOADADDR 400000 509 510 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 511 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 512 513 #define CONFIG_BAUDRATE 115200 514 515 #define CONFIG_PREBOOT "echo;" \ 516 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 517 "echo" 518 519 #undef CONFIG_BOOTARGS 520 521 #define CONFIG_EXTRA_ENV_SETTINGS \ 522 "netdev=eth0\0" \ 523 "hostname=tqm834x\0" \ 524 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 525 "nfsroot=${serverip}:${rootpath}\0" \ 526 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 527 "addip=setenv bootargs ${bootargs} " \ 528 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 529 ":${hostname}:${netdev}:off panic=1\0" \ 530 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ 531 "flash_nfs_old=run nfsargs addip addcons;" \ 532 "bootm ${kernel_addr}\0" \ 533 "flash_nfs=run nfsargs addip addcons;" \ 534 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 535 "flash_self_old=run ramargs addip addcons;" \ 536 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 537 "flash_self=run ramargs addip addcons;" \ 538 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 539 "net_nfs_old=tftp 400000 ${bootfile};" \ 540 "run nfsargs addip addcons;bootm\0" \ 541 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 542 "tftp ${fdt_addr_r} ${fdt_file}; " \ 543 "run nfsargs addip addcons; " \ 544 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 545 "rootpath=/opt/eldk/ppc_6xx\0" \ 546 "bootfile=tqm834x/uImage\0" \ 547 "fdtfile=tqm834x/tqm834x.dtb\0" \ 548 "kernel_addr_r=400000\0" \ 549 "fdt_addr_r=600000\0" \ 550 "ramdisk_addr_r=800000\0" \ 551 "kernel_addr=800C0000\0" \ 552 "fdt_addr=800A0000\0" \ 553 "ramdisk_addr=80300000\0" \ 554 "u-boot=tqm834x/u-boot.bin\0" \ 555 "load=tftp 200000 ${u-boot}\0" \ 556 "update=protect off 80000000 +${filesize};" \ 557 "era 80000000 +${filesize};" \ 558 "cp.b 200000 80000000 ${filesize}\0" \ 559 "upd=run load update\0" \ 560 "" 561 562 #define CONFIG_BOOTCOMMAND "run flash_self" 563 564 /* 565 * JFFS2 partitions 566 */ 567 /* mtdparts command line support */ 568 #define CONFIG_CMD_MTDPARTS 569 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 570 #define CONFIG_FLASH_CFI_MTD 571 #define MTDIDS_DEFAULT "nor0=TQM834x-0" 572 573 /* default mtd partition table */ 574 #define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \ 575 "1m(kernel),2m(initrd)," \ 576 "-(user);" \ 577 578 #endif /* __CONFIG_H */ 579