1 /* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * TQM8349 board configuration file 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #define CONFIG_DISPLAY_BOARDINFO 16 17 /* 18 * High Level Configuration Options 19 */ 20 #define CONFIG_E300 1 /* E300 Family */ 21 #define CONFIG_MPC834x 1 /* MPC834x specific */ 22 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 23 #define CONFIG_TQM834X 1 /* TQM834X board specific */ 24 25 #define CONFIG_SYS_TEXT_BASE 0x80000000 26 27 /* IMMR Base Address Register, use Freescale default: 0xff400000 */ 28 #define CONFIG_SYS_IMMR 0xff400000 29 30 /* System clock. Primary input clock when in PCI host mode */ 31 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ 32 33 /* 34 * Local Bus LCRR 35 * LCRR: DLL bypass, Clock divider is 8 36 * 37 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz 38 * 39 * External Local Bus rate is 40 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 41 */ 42 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 43 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 44 45 /* board pre init: do not call, nothing to do */ 46 #undef CONFIG_BOARD_EARLY_INIT_F 47 48 /* detect the number of flash banks */ 49 #define CONFIG_BOARD_EARLY_INIT_R 50 51 /* 52 * DDR Setup 53 */ 54 /* DDR is system memory*/ 55 #define CONFIG_SYS_DDR_BASE 0x00000000 56 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 57 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 58 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ 59 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 60 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ 61 62 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 63 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 64 #define CONFIG_SYS_MEMTEST_END 0x00100000 65 66 /* 67 * FLASH on the Local Bus 68 */ 69 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 70 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 71 #undef CONFIG_SYS_FLASH_CHECKSUM 72 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ 73 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ 74 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ 75 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 76 77 /* 78 * FLASH bank number detection 79 */ 80 81 /* 82 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of 83 * Flash banks has to be determined at runtime and stored in a gloabl variable 84 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is 85 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array 86 * flash_info, and should be made sufficiently large to accomodate the number 87 * of banks that might actually be detected. Since most (all?) Flash related 88 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on 89 * the board, it is defined as tqm834x_num_flash_banks. 90 */ 91 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 92 93 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ 94 95 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ 96 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \ 97 | BR_MS_GPCM \ 98 | BR_PS_32 \ 99 | BR_V) 100 101 /* FLASH timing (0x0000_0c54) */ 102 #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \ 103 | OR_GPCM_ACS_DIV4 \ 104 | OR_GPCM_SCY_5 \ 105 | OR_GPCM_TRLX) 106 107 #define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */ 108 109 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ 110 | CONFIG_SYS_OR_TIMING_FLASH) 111 112 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB) 113 114 /* Window base at flash base */ 115 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 116 117 /* disable remaining mappings */ 118 #define CONFIG_SYS_BR1_PRELIM 0x00000000 119 #define CONFIG_SYS_OR1_PRELIM 0x00000000 120 #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000 121 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000 122 123 #define CONFIG_SYS_BR2_PRELIM 0x00000000 124 #define CONFIG_SYS_OR2_PRELIM 0x00000000 125 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000 126 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000 127 128 #define CONFIG_SYS_BR3_PRELIM 0x00000000 129 #define CONFIG_SYS_OR3_PRELIM 0x00000000 130 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000 131 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000 132 133 /* 134 * Monitor config 135 */ 136 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 137 138 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 139 # define CONFIG_SYS_RAMBOOT 140 #else 141 # undef CONFIG_SYS_RAMBOOT 142 #endif 143 144 #define CONFIG_SYS_INIT_RAM_LOCK 1 145 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ 146 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 147 148 #define CONFIG_SYS_GBL_DATA_OFFSET \ 149 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 150 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 151 152 /* Reserve 384 kB = 3 sect. for Mon */ 153 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 154 /* Reserve 512 kB for malloc */ 155 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 156 157 /* 158 * Serial Port 159 */ 160 #define CONFIG_CONS_INDEX 1 161 #define CONFIG_SYS_NS16550 162 #define CONFIG_SYS_NS16550_SERIAL 163 #define CONFIG_SYS_NS16550_REG_SIZE 1 164 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 165 166 #define CONFIG_SYS_BAUDRATE_TABLE \ 167 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 168 169 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 170 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 171 172 /* 173 * I2C 174 */ 175 #define CONFIG_SYS_I2C 176 #define CONFIG_SYS_I2C_FSL 177 #define CONFIG_SYS_FSL_I2C_SPEED 400000 178 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 179 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 180 181 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ 182 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 183 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ 184 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ 185 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ 186 #define CONFIG_SYS_I2C_MULTI_EEPROMS /* more than one eeprom */ 187 188 /* I2C RTC */ 189 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ 190 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 191 192 /* I2C SYSMON (LM75) */ 193 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ 194 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ 195 #define CONFIG_SYS_DTT_MAX_TEMP 70 196 #define CONFIG_SYS_DTT_LOW_TEMP -30 197 #define CONFIG_SYS_DTT_HYSTERESIS 3 198 199 /* 200 * TSEC 201 */ 202 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 203 #define CONFIG_MII 204 205 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 206 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 207 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 208 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 209 210 #if defined(CONFIG_TSEC_ENET) 211 212 #define CONFIG_TSEC1 1 213 #define CONFIG_TSEC1_NAME "TSEC0" 214 #define CONFIG_TSEC2 1 215 #define CONFIG_TSEC2_NAME "TSEC1" 216 #define TSEC1_PHY_ADDR 2 217 #define TSEC2_PHY_ADDR 1 218 #define TSEC1_PHYIDX 0 219 #define TSEC2_PHYIDX 0 220 #define TSEC1_FLAGS TSEC_GIGABIT 221 #define TSEC2_FLAGS TSEC_GIGABIT 222 223 /* Options are: TSEC[0-1] */ 224 #define CONFIG_ETHPRIME "TSEC0" 225 226 #endif /* CONFIG_TSEC_ENET */ 227 228 /* 229 * General PCI 230 * Addresses are mapped 1-1. 231 */ 232 #define CONFIG_PCI 233 234 #if defined(CONFIG_PCI) 235 236 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 237 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 238 239 /* PCI1 host bridge */ 240 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 241 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 242 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 243 #define CONFIG_SYS_PCI1_MMIO_BASE \ 244 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 245 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 246 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 247 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 248 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 249 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ 250 251 #undef CONFIG_EEPRO100 252 #define CONFIG_EEPRO100 253 #undef CONFIG_TULIP 254 255 #if !defined(CONFIG_PCI_PNP) 256 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE 257 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE 258 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ 259 #endif 260 261 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 262 263 #endif /* CONFIG_PCI */ 264 265 /* 266 * Environment 267 */ 268 #define CONFIG_ENV_IS_IN_FLASH 1 269 #define CONFIG_ENV_ADDR \ 270 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 271 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ 272 #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */ 273 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 274 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 275 276 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 277 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 278 279 /* 280 * BOOTP options 281 */ 282 #define CONFIG_BOOTP_BOOTFILESIZE 283 #define CONFIG_BOOTP_BOOTPATH 284 #define CONFIG_BOOTP_GATEWAY 285 #define CONFIG_BOOTP_HOSTNAME 286 287 288 /* 289 * Command line configuration. 290 */ 291 #define CONFIG_CMD_ASKENV 292 #define CONFIG_CMD_DATE 293 #define CONFIG_CMD_DHCP 294 #define CONFIG_CMD_DTT 295 #define CONFIG_CMD_EEPROM 296 #define CONFIG_CMD_I2C 297 #define CONFIG_CMD_JFFS2 298 #define CONFIG_CMD_MII 299 #define CONFIG_CMD_PING 300 #define CONFIG_CMD_REGINFO 301 #define CONFIG_CMD_SNTP 302 303 #if defined(CONFIG_PCI) 304 #define CONFIG_CMD_PCI 305 #endif 306 307 /* 308 * Miscellaneous configurable options 309 */ 310 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 311 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 312 313 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 314 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 315 316 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 317 318 #if defined(CONFIG_CMD_KGDB) 319 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 320 #else 321 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 322 #endif 323 324 /* Print Buffer Size */ 325 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 326 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 327 /* Boot Argument Buffer Size */ 328 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 329 330 #undef CONFIG_WATCHDOG /* watchdog disabled */ 331 332 /* pass open firmware flat tree */ 333 #define CONFIG_OF_LIBFDT 1 334 #define CONFIG_OF_BOARD_SETUP 1 335 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 336 337 /* 338 * For booting Linux, the board info and command line data 339 * have to be in the first 256 MB of memory, since this is 340 * the maximum mapped by the Linux kernel during initialization. 341 */ 342 /* Initial Memory map for Linux */ 343 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 344 345 #define CONFIG_SYS_HRCW_LOW (\ 346 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 347 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 348 HRCWL_CSB_TO_CLKIN_4X1 |\ 349 HRCWL_VCO_1X2 |\ 350 HRCWL_CORE_TO_CSB_2X1) 351 352 #if defined(PCI_64BIT) 353 #define CONFIG_SYS_HRCW_HIGH (\ 354 HRCWH_PCI_HOST |\ 355 HRCWH_64_BIT_PCI |\ 356 HRCWH_PCI1_ARBITER_ENABLE |\ 357 HRCWH_PCI2_ARBITER_DISABLE |\ 358 HRCWH_CORE_ENABLE |\ 359 HRCWH_FROM_0X00000100 |\ 360 HRCWH_BOOTSEQ_DISABLE |\ 361 HRCWH_SW_WATCHDOG_DISABLE |\ 362 HRCWH_ROM_LOC_LOCAL_16BIT |\ 363 HRCWH_TSEC1M_IN_GMII |\ 364 HRCWH_TSEC2M_IN_GMII) 365 #else 366 #define CONFIG_SYS_HRCW_HIGH (\ 367 HRCWH_PCI_HOST |\ 368 HRCWH_32_BIT_PCI |\ 369 HRCWH_PCI1_ARBITER_ENABLE |\ 370 HRCWH_PCI2_ARBITER_DISABLE |\ 371 HRCWH_CORE_ENABLE |\ 372 HRCWH_FROM_0X00000100 |\ 373 HRCWH_BOOTSEQ_DISABLE |\ 374 HRCWH_SW_WATCHDOG_DISABLE |\ 375 HRCWH_ROM_LOC_LOCAL_16BIT |\ 376 HRCWH_TSEC1M_IN_GMII |\ 377 HRCWH_TSEC2M_IN_GMII) 378 #endif 379 380 /* System IO Config */ 381 #define CONFIG_SYS_SICRH 0 382 #define CONFIG_SYS_SICRL SICRL_LDP_A 383 384 /* i-cache and d-cache disabled */ 385 #define CONFIG_SYS_HID0_INIT 0x000000000 386 #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ 387 HID0_ENABLE_INSTRUCTION_CACHE) 388 #define CONFIG_SYS_HID2 HID2_HBE 389 390 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 391 392 /* DDR 0 - 512M */ 393 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 394 | BATL_PP_RW \ 395 | BATL_MEMCOHERENCE) 396 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 397 | BATU_BL_256M \ 398 | BATU_VS \ 399 | BATU_VP) 400 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 401 | BATL_PP_RW \ 402 | BATL_MEMCOHERENCE) 403 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 404 | BATU_BL_256M \ 405 | BATU_VS \ 406 | BATU_VP) 407 408 /* stack in DCACHE @ 512M (no backing mem) */ 409 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ 410 | BATL_PP_RW \ 411 | BATL_MEMCOHERENCE) 412 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ 413 | BATU_BL_128K \ 414 | BATU_VS \ 415 | BATU_VP) 416 417 /* PCI */ 418 #ifdef CONFIG_PCI 419 #define CONFIG_PCI_INDIRECT_BRIDGE 420 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \ 421 | BATL_PP_RW \ 422 | BATL_MEMCOHERENCE) 423 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \ 424 | BATU_BL_256M \ 425 | BATU_VS \ 426 | BATU_VP) 427 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \ 428 | BATL_PP_RW \ 429 | BATL_MEMCOHERENCE \ 430 | BATL_GUARDEDSTORAGE) 431 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \ 432 | BATU_BL_256M \ 433 | BATU_VS \ 434 | BATU_VP) 435 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \ 436 | BATL_PP_RW \ 437 | BATL_CACHEINHIBIT \ 438 | BATL_GUARDEDSTORAGE) 439 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \ 440 | BATU_BL_16M \ 441 | BATU_VS \ 442 | BATU_VP) 443 #else 444 #define CONFIG_SYS_IBAT3L (0) 445 #define CONFIG_SYS_IBAT3U (0) 446 #define CONFIG_SYS_IBAT4L (0) 447 #define CONFIG_SYS_IBAT4U (0) 448 #define CONFIG_SYS_IBAT5L (0) 449 #define CONFIG_SYS_IBAT5U (0) 450 #endif 451 452 /* IMMRBAR */ 453 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \ 454 | BATL_PP_RW \ 455 | BATL_CACHEINHIBIT \ 456 | BATL_GUARDEDSTORAGE) 457 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \ 458 | BATU_BL_1M \ 459 | BATU_VS \ 460 | BATU_VP) 461 462 /* FLASH */ 463 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \ 464 | BATL_PP_RW \ 465 | BATL_CACHEINHIBIT \ 466 | BATL_GUARDEDSTORAGE) 467 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \ 468 | BATU_BL_256M \ 469 | BATU_VS \ 470 | BATU_VP) 471 472 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 473 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 474 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 475 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 476 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 477 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 478 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 479 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 480 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 481 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 482 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 483 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 484 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 485 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 486 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 487 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 488 489 #if defined(CONFIG_CMD_KGDB) 490 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 491 #endif 492 493 /* 494 * Environment Configuration 495 */ 496 497 /* default location for tftp and bootm */ 498 #define CONFIG_LOADADDR 400000 499 500 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 501 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 502 503 #define CONFIG_BAUDRATE 115200 504 505 #define CONFIG_PREBOOT "echo;" \ 506 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 507 "echo" 508 509 #undef CONFIG_BOOTARGS 510 511 #define CONFIG_EXTRA_ENV_SETTINGS \ 512 "netdev=eth0\0" \ 513 "hostname=tqm834x\0" \ 514 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 515 "nfsroot=${serverip}:${rootpath}\0" \ 516 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 517 "addip=setenv bootargs ${bootargs} " \ 518 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 519 ":${hostname}:${netdev}:off panic=1\0" \ 520 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ 521 "flash_nfs_old=run nfsargs addip addcons;" \ 522 "bootm ${kernel_addr}\0" \ 523 "flash_nfs=run nfsargs addip addcons;" \ 524 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 525 "flash_self_old=run ramargs addip addcons;" \ 526 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 527 "flash_self=run ramargs addip addcons;" \ 528 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 529 "net_nfs_old=tftp 400000 ${bootfile};" \ 530 "run nfsargs addip addcons;bootm\0" \ 531 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 532 "tftp ${fdt_addr_r} ${fdt_file}; " \ 533 "run nfsargs addip addcons; " \ 534 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 535 "rootpath=/opt/eldk/ppc_6xx\0" \ 536 "bootfile=tqm834x/uImage\0" \ 537 "fdtfile=tqm834x/tqm834x.dtb\0" \ 538 "kernel_addr_r=400000\0" \ 539 "fdt_addr_r=600000\0" \ 540 "ramdisk_addr_r=800000\0" \ 541 "kernel_addr=800C0000\0" \ 542 "fdt_addr=800A0000\0" \ 543 "ramdisk_addr=80300000\0" \ 544 "u-boot=tqm834x/u-boot.bin\0" \ 545 "load=tftp 200000 ${u-boot}\0" \ 546 "update=protect off 80000000 +${filesize};" \ 547 "era 80000000 +${filesize};" \ 548 "cp.b 200000 80000000 ${filesize}\0" \ 549 "upd=run load update\0" \ 550 "" 551 552 #define CONFIG_BOOTCOMMAND "run flash_self" 553 554 /* 555 * JFFS2 partitions 556 */ 557 /* mtdparts command line support */ 558 #define CONFIG_CMD_MTDPARTS 559 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 560 #define CONFIG_FLASH_CFI_MTD 561 #define MTDIDS_DEFAULT "nor0=TQM834x-0" 562 563 /* default mtd partition table */ 564 #define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \ 565 "1m(kernel),2m(initrd)," \ 566 "-(user);" \ 567 568 #endif /* __CONFIG_H */ 569