1 /* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * TQM8349 board configuration file 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 #define CONFIG_E300 1 /* E300 Family */ 19 #define CONFIG_MPC834x 1 /* MPC834x specific */ 20 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 21 22 /* IMMR Base Address Register, use Freescale default: 0xff400000 */ 23 #define CONFIG_SYS_IMMR 0xff400000 24 25 /* System clock. Primary input clock when in PCI host mode */ 26 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ 27 28 /* 29 * Local Bus LCRR 30 * LCRR: DLL bypass, Clock divider is 8 31 * 32 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz 33 * 34 * External Local Bus rate is 35 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 36 */ 37 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 38 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 39 40 /* board pre init: do not call, nothing to do */ 41 42 /* detect the number of flash banks */ 43 44 /* 45 * DDR Setup 46 */ 47 /* DDR is system memory*/ 48 #define CONFIG_SYS_DDR_BASE 0x00000000 49 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 50 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 51 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ 52 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 53 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ 54 55 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 56 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 57 #define CONFIG_SYS_MEMTEST_END 0x00100000 58 59 /* 60 * FLASH on the Local Bus 61 */ 62 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 63 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 64 #undef CONFIG_SYS_FLASH_CHECKSUM 65 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ 66 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ 67 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ 68 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 69 70 /* 71 * FLASH bank number detection 72 */ 73 74 /* 75 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of 76 * Flash banks has to be determined at runtime and stored in a gloabl variable 77 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is 78 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array 79 * flash_info, and should be made sufficiently large to accomodate the number 80 * of banks that might actually be detected. Since most (all?) Flash related 81 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on 82 * the board, it is defined as tqm834x_num_flash_banks. 83 */ 84 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 85 86 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ 87 88 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ 89 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \ 90 | BR_MS_GPCM \ 91 | BR_PS_32 \ 92 | BR_V) 93 94 /* FLASH timing (0x0000_0c54) */ 95 #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \ 96 | OR_GPCM_ACS_DIV4 \ 97 | OR_GPCM_SCY_5 \ 98 | OR_GPCM_TRLX) 99 100 #define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */ 101 102 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ 103 | CONFIG_SYS_OR_TIMING_FLASH) 104 105 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB) 106 107 /* Window base at flash base */ 108 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 109 110 /* disable remaining mappings */ 111 #define CONFIG_SYS_BR1_PRELIM 0x00000000 112 #define CONFIG_SYS_OR1_PRELIM 0x00000000 113 #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000 114 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000 115 116 #define CONFIG_SYS_BR2_PRELIM 0x00000000 117 #define CONFIG_SYS_OR2_PRELIM 0x00000000 118 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000 119 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000 120 121 #define CONFIG_SYS_BR3_PRELIM 0x00000000 122 #define CONFIG_SYS_OR3_PRELIM 0x00000000 123 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000 124 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000 125 126 /* 127 * Monitor config 128 */ 129 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 130 131 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 132 # define CONFIG_SYS_RAMBOOT 133 #else 134 # undef CONFIG_SYS_RAMBOOT 135 #endif 136 137 #define CONFIG_SYS_INIT_RAM_LOCK 1 138 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ 139 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 140 141 #define CONFIG_SYS_GBL_DATA_OFFSET \ 142 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 143 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 144 145 /* Reserve 384 kB = 3 sect. for Mon */ 146 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 147 /* Reserve 512 kB for malloc */ 148 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 149 150 /* 151 * Serial Port 152 */ 153 #define CONFIG_SYS_NS16550_SERIAL 154 #define CONFIG_SYS_NS16550_REG_SIZE 1 155 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 156 157 #define CONFIG_SYS_BAUDRATE_TABLE \ 158 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 159 160 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 161 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 162 163 /* 164 * I2C 165 */ 166 #define CONFIG_SYS_I2C 167 #define CONFIG_SYS_I2C_FSL 168 #define CONFIG_SYS_FSL_I2C_SPEED 400000 169 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 170 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 171 172 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ 173 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 174 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ 175 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ 176 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ 177 178 /* I2C RTC */ 179 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ 180 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 181 182 /* 183 * TSEC 184 */ 185 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 186 #define CONFIG_MII 187 188 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 189 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 190 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 191 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 192 193 #if defined(CONFIG_TSEC_ENET) 194 195 #define CONFIG_TSEC1 1 196 #define CONFIG_TSEC1_NAME "TSEC0" 197 #define CONFIG_TSEC2 1 198 #define CONFIG_TSEC2_NAME "TSEC1" 199 #define TSEC1_PHY_ADDR 2 200 #define TSEC2_PHY_ADDR 1 201 #define TSEC1_PHYIDX 0 202 #define TSEC2_PHYIDX 0 203 #define TSEC1_FLAGS TSEC_GIGABIT 204 #define TSEC2_FLAGS TSEC_GIGABIT 205 206 /* Options are: TSEC[0-1] */ 207 #define CONFIG_ETHPRIME "TSEC0" 208 209 #endif /* CONFIG_TSEC_ENET */ 210 211 #if defined(CONFIG_PCI) 212 213 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 214 215 /* PCI1 host bridge */ 216 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 217 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 218 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 219 #define CONFIG_SYS_PCI1_MMIO_BASE \ 220 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 221 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 222 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 223 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 224 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 225 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ 226 227 #undef CONFIG_EEPRO100 228 #define CONFIG_EEPRO100 229 #undef CONFIG_TULIP 230 231 #if !defined(CONFIG_PCI_PNP) 232 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE 233 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE 234 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ 235 #endif 236 237 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 238 239 #endif /* CONFIG_PCI */ 240 241 /* 242 * Environment 243 */ 244 #define CONFIG_ENV_ADDR \ 245 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 246 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ 247 #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */ 248 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 249 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 250 251 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 252 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 253 254 /* 255 * BOOTP options 256 */ 257 #define CONFIG_BOOTP_BOOTFILESIZE 258 259 /* 260 * Miscellaneous configurable options 261 */ 262 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 263 264 #undef CONFIG_WATCHDOG /* watchdog disabled */ 265 266 /* 267 * For booting Linux, the board info and command line data 268 * have to be in the first 256 MB of memory, since this is 269 * the maximum mapped by the Linux kernel during initialization. 270 */ 271 /* Initial Memory map for Linux */ 272 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 273 274 #define CONFIG_SYS_HRCW_LOW (\ 275 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 276 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 277 HRCWL_CSB_TO_CLKIN_4X1 |\ 278 HRCWL_VCO_1X2 |\ 279 HRCWL_CORE_TO_CSB_2X1) 280 281 #if defined(PCI_64BIT) 282 #define CONFIG_SYS_HRCW_HIGH (\ 283 HRCWH_PCI_HOST |\ 284 HRCWH_64_BIT_PCI |\ 285 HRCWH_PCI1_ARBITER_ENABLE |\ 286 HRCWH_PCI2_ARBITER_DISABLE |\ 287 HRCWH_CORE_ENABLE |\ 288 HRCWH_FROM_0X00000100 |\ 289 HRCWH_BOOTSEQ_DISABLE |\ 290 HRCWH_SW_WATCHDOG_DISABLE |\ 291 HRCWH_ROM_LOC_LOCAL_16BIT |\ 292 HRCWH_TSEC1M_IN_GMII |\ 293 HRCWH_TSEC2M_IN_GMII) 294 #else 295 #define CONFIG_SYS_HRCW_HIGH (\ 296 HRCWH_PCI_HOST |\ 297 HRCWH_32_BIT_PCI |\ 298 HRCWH_PCI1_ARBITER_ENABLE |\ 299 HRCWH_PCI2_ARBITER_DISABLE |\ 300 HRCWH_CORE_ENABLE |\ 301 HRCWH_FROM_0X00000100 |\ 302 HRCWH_BOOTSEQ_DISABLE |\ 303 HRCWH_SW_WATCHDOG_DISABLE |\ 304 HRCWH_ROM_LOC_LOCAL_16BIT |\ 305 HRCWH_TSEC1M_IN_GMII |\ 306 HRCWH_TSEC2M_IN_GMII) 307 #endif 308 309 /* System IO Config */ 310 #define CONFIG_SYS_SICRH 0 311 #define CONFIG_SYS_SICRL SICRL_LDP_A 312 313 /* i-cache and d-cache disabled */ 314 #define CONFIG_SYS_HID0_INIT 0x000000000 315 #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ 316 HID0_ENABLE_INSTRUCTION_CACHE) 317 #define CONFIG_SYS_HID2 HID2_HBE 318 319 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 320 321 /* DDR 0 - 512M */ 322 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 323 | BATL_PP_RW \ 324 | BATL_MEMCOHERENCE) 325 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 326 | BATU_BL_256M \ 327 | BATU_VS \ 328 | BATU_VP) 329 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 330 | BATL_PP_RW \ 331 | BATL_MEMCOHERENCE) 332 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ 333 | BATU_BL_256M \ 334 | BATU_VS \ 335 | BATU_VP) 336 337 /* stack in DCACHE @ 512M (no backing mem) */ 338 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ 339 | BATL_PP_RW \ 340 | BATL_MEMCOHERENCE) 341 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ 342 | BATU_BL_128K \ 343 | BATU_VS \ 344 | BATU_VP) 345 346 /* PCI */ 347 #ifdef CONFIG_PCI 348 #define CONFIG_PCI_INDIRECT_BRIDGE 349 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \ 350 | BATL_PP_RW \ 351 | BATL_MEMCOHERENCE) 352 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \ 353 | BATU_BL_256M \ 354 | BATU_VS \ 355 | BATU_VP) 356 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \ 357 | BATL_PP_RW \ 358 | BATL_MEMCOHERENCE \ 359 | BATL_GUARDEDSTORAGE) 360 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \ 361 | BATU_BL_256M \ 362 | BATU_VS \ 363 | BATU_VP) 364 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \ 365 | BATL_PP_RW \ 366 | BATL_CACHEINHIBIT \ 367 | BATL_GUARDEDSTORAGE) 368 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \ 369 | BATU_BL_16M \ 370 | BATU_VS \ 371 | BATU_VP) 372 #else 373 #define CONFIG_SYS_IBAT3L (0) 374 #define CONFIG_SYS_IBAT3U (0) 375 #define CONFIG_SYS_IBAT4L (0) 376 #define CONFIG_SYS_IBAT4U (0) 377 #define CONFIG_SYS_IBAT5L (0) 378 #define CONFIG_SYS_IBAT5U (0) 379 #endif 380 381 /* IMMRBAR */ 382 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \ 383 | BATL_PP_RW \ 384 | BATL_CACHEINHIBIT \ 385 | BATL_GUARDEDSTORAGE) 386 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \ 387 | BATU_BL_1M \ 388 | BATU_VS \ 389 | BATU_VP) 390 391 /* FLASH */ 392 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \ 393 | BATL_PP_RW \ 394 | BATL_CACHEINHIBIT \ 395 | BATL_GUARDEDSTORAGE) 396 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \ 397 | BATU_BL_256M \ 398 | BATU_VS \ 399 | BATU_VP) 400 401 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 402 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 403 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 404 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 405 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 406 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 407 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 408 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 409 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 410 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 411 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 412 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 413 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 414 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 415 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 416 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 417 418 #if defined(CONFIG_CMD_KGDB) 419 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 420 #endif 421 422 /* 423 * Environment Configuration 424 */ 425 426 /* default location for tftp and bootm */ 427 #define CONFIG_LOADADDR 400000 428 429 #define CONFIG_PREBOOT "echo;" \ 430 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 431 "echo" 432 433 #define CONFIG_EXTRA_ENV_SETTINGS \ 434 "netdev=eth0\0" \ 435 "hostname=tqm834x\0" \ 436 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 437 "nfsroot=${serverip}:${rootpath}\0" \ 438 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 439 "addip=setenv bootargs ${bootargs} " \ 440 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 441 ":${hostname}:${netdev}:off panic=1\0" \ 442 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ 443 "flash_nfs_old=run nfsargs addip addcons;" \ 444 "bootm ${kernel_addr}\0" \ 445 "flash_nfs=run nfsargs addip addcons;" \ 446 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 447 "flash_self_old=run ramargs addip addcons;" \ 448 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 449 "flash_self=run ramargs addip addcons;" \ 450 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 451 "net_nfs_old=tftp 400000 ${bootfile};" \ 452 "run nfsargs addip addcons;bootm\0" \ 453 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 454 "tftp ${fdt_addr_r} ${fdt_file}; " \ 455 "run nfsargs addip addcons; " \ 456 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 457 "rootpath=/opt/eldk/ppc_6xx\0" \ 458 "bootfile=tqm834x/uImage\0" \ 459 "fdtfile=tqm834x/tqm834x.dtb\0" \ 460 "kernel_addr_r=400000\0" \ 461 "fdt_addr_r=600000\0" \ 462 "ramdisk_addr_r=800000\0" \ 463 "kernel_addr=800C0000\0" \ 464 "fdt_addr=800A0000\0" \ 465 "ramdisk_addr=80300000\0" \ 466 "u-boot=tqm834x/u-boot.bin\0" \ 467 "load=tftp 200000 ${u-boot}\0" \ 468 "update=protect off 80000000 +${filesize};" \ 469 "era 80000000 +${filesize};" \ 470 "cp.b 200000 80000000 ${filesize}\0" \ 471 "upd=run load update\0" \ 472 "" 473 474 #define CONFIG_BOOTCOMMAND "run flash_self" 475 476 /* 477 * JFFS2 partitions 478 */ 479 /* mtdparts command line support */ 480 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 481 #define CONFIG_FLASH_CFI_MTD 482 483 /* default mtd partition table */ 484 #endif /* __CONFIG_H */ 485