1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T4240 RDB board configuration file 8 */ 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_FSL_SATA_V2 13 #define CONFIG_PCIE4 14 15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 16 17 #ifdef CONFIG_RAMBOOT_PBL 18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 19 #ifndef CONFIG_SDCARD 20 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 21 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 22 #else 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 25 #define CONFIG_SPL_PAD_TO 0x40000 26 #define CONFIG_SPL_MAX_SIZE 0x28000 27 #define RESET_VECTOR_OFFSET 0x27FFC 28 #define BOOT_PAGE_OFFSET 0x27000 29 30 #ifdef CONFIG_SDCARD 31 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 32 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 33 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 34 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 35 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 36 #ifndef CONFIG_SPL_BUILD 37 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 38 #endif 39 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 40 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg 41 #define CONFIG_SPL_MMC_BOOT 42 #endif 43 44 #ifdef CONFIG_SPL_BUILD 45 #define CONFIG_SPL_SKIP_RELOCATE 46 #define CONFIG_SPL_COMMON_INIT_DDR 47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 48 #endif 49 50 #endif 51 #endif /* CONFIG_RAMBOOT_PBL */ 52 53 #define CONFIG_DDR_ECC 54 55 /* High Level Configuration Options */ 56 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 57 58 #ifndef CONFIG_RESET_VECTOR_ADDRESS 59 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 60 #endif 61 62 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 63 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 64 #define CONFIG_PCIE1 /* PCIE controller 1 */ 65 #define CONFIG_PCIE2 /* PCIE controller 2 */ 66 #define CONFIG_PCIE3 /* PCIE controller 3 */ 67 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 68 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 69 70 #define CONFIG_ENV_OVERWRITE 71 72 /* 73 * These can be toggled for performance analysis, otherwise use default. 74 */ 75 #define CONFIG_SYS_CACHE_STASHING 76 #define CONFIG_BTB /* toggle branch predition */ 77 #ifdef CONFIG_DDR_ECC 78 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 79 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 80 #endif 81 82 #define CONFIG_ENABLE_36BIT_PHYS 83 84 #define CONFIG_ADDR_MAP 85 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 86 87 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 88 #define CONFIG_SYS_MEMTEST_END 0x00400000 89 90 /* 91 * Config the L3 Cache as L3 SRAM 92 */ 93 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 94 #define CONFIG_SYS_L3_SIZE (512 << 10) 95 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 96 #ifdef CONFIG_RAMBOOT_PBL 97 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 98 #endif 99 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 100 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 101 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 102 103 #define CONFIG_SYS_DCSRBAR 0xf0000000 104 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 105 106 /* 107 * DDR Setup 108 */ 109 #define CONFIG_VERY_BIG_RAM 110 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 111 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 112 113 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 114 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 115 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 116 117 #define CONFIG_DDR_SPD 118 119 /* 120 * IFC Definitions 121 */ 122 #define CONFIG_SYS_FLASH_BASE 0xe0000000 123 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 124 125 #ifdef CONFIG_SPL_BUILD 126 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 127 #else 128 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 129 #endif 130 131 #define CONFIG_HWCONFIG 132 133 /* define to use L1 as initial stack */ 134 #define CONFIG_L1_INIT_RAM 135 #define CONFIG_SYS_INIT_RAM_LOCK 136 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 137 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 138 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 139 /* The assembler doesn't like typecast */ 140 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 141 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 142 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 143 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 144 145 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 146 GENERATED_GBL_DATA_SIZE) 147 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 148 149 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 150 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 151 152 /* Serial Port - controlled on board with jumper J8 153 * open - index 2 154 * shorted - index 1 155 */ 156 #define CONFIG_SYS_NS16550_SERIAL 157 #define CONFIG_SYS_NS16550_REG_SIZE 1 158 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 159 160 #define CONFIG_SYS_BAUDRATE_TABLE \ 161 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 162 163 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 164 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 165 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 166 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 167 168 /* I2C */ 169 #define CONFIG_SYS_I2C 170 #define CONFIG_SYS_I2C_FSL 171 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 172 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 173 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 174 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 175 176 /* 177 * General PCI 178 * Memory space is mapped 1-1, but I/O space must start from 0. 179 */ 180 181 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 182 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 183 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 184 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 185 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 186 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 187 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 188 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 189 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 190 191 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 192 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 193 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 194 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 195 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 196 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 197 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 198 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 199 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 200 201 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 202 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 203 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 204 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 205 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 206 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 207 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 208 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 209 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 210 211 /* controller 4, Base address 203000 */ 212 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 213 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 214 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 215 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 216 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 217 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 218 219 #ifdef CONFIG_PCI 220 #define CONFIG_PCI_INDIRECT_BRIDGE 221 222 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 223 #endif /* CONFIG_PCI */ 224 225 /* SATA */ 226 #ifdef CONFIG_FSL_SATA_V2 227 #define CONFIG_SYS_SATA_MAX_DEVICE 2 228 #define CONFIG_SATA1 229 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 230 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 231 #define CONFIG_SATA2 232 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 233 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 234 235 #define CONFIG_LBA48 236 #endif 237 238 #ifdef CONFIG_FMAN_ENET 239 #define CONFIG_ETHPRIME "FM1@DTSEC1" 240 #endif 241 242 /* 243 * Environment 244 */ 245 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 246 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 247 248 /* 249 * Command line configuration. 250 */ 251 252 /* 253 * Miscellaneous configurable options 254 */ 255 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 256 257 /* 258 * For booting Linux, the board info and command line data 259 * have to be in the first 64 MB of memory, since this is 260 * the maximum mapped by the Linux kernel during initialization. 261 */ 262 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 263 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 264 265 #ifdef CONFIG_CMD_KGDB 266 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 267 #endif 268 269 /* 270 * Environment Configuration 271 */ 272 #define CONFIG_ROOTPATH "/opt/nfsroot" 273 #define CONFIG_BOOTFILE "uImage" 274 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 275 276 /* default location for tftp and bootm */ 277 #define CONFIG_LOADADDR 1000000 278 279 #define CONFIG_HVBOOT \ 280 "setenv bootargs config-addr=0x60000000; " \ 281 "bootm 0x01000000 - 0x00f00000" 282 283 #ifndef CONFIG_MTD_NOR_FLASH 284 #else 285 #define CONFIG_FLASH_CFI_DRIVER 286 #define CONFIG_SYS_FLASH_CFI 287 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 288 #endif 289 290 #if defined(CONFIG_SPIFLASH) 291 #define CONFIG_ENV_SPI_BUS 0 292 #define CONFIG_ENV_SPI_CS 0 293 #define CONFIG_ENV_SPI_MAX_HZ 10000000 294 #define CONFIG_ENV_SPI_MODE 0 295 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 296 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 297 #define CONFIG_ENV_SECT_SIZE 0x10000 298 #elif defined(CONFIG_SDCARD) 299 #define CONFIG_SYS_MMC_ENV_DEV 0 300 #define CONFIG_ENV_SIZE 0x2000 301 #define CONFIG_ENV_OFFSET (512 * 0x800) 302 #elif defined(CONFIG_NAND) 303 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 304 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 305 #elif defined(CONFIG_ENV_IS_NOWHERE) 306 #define CONFIG_ENV_SIZE 0x2000 307 #else 308 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 309 #define CONFIG_ENV_SIZE 0x2000 310 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 311 #endif 312 313 #define CONFIG_SYS_CLK_FREQ 66666666 314 #define CONFIG_DDR_CLK_FREQ 133333333 315 316 #ifndef __ASSEMBLY__ 317 unsigned long get_board_sys_clk(void); 318 unsigned long get_board_ddr_clk(void); 319 #endif 320 321 /* 322 * DDR Setup 323 */ 324 #define CONFIG_SYS_SPD_BUS_NUM 0 325 #define SPD_EEPROM_ADDRESS1 0x52 326 #define SPD_EEPROM_ADDRESS2 0x54 327 #define SPD_EEPROM_ADDRESS3 0x56 328 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 329 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 330 331 /* 332 * IFC Definitions 333 */ 334 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 335 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 336 + 0x8000000) | \ 337 CSPR_PORT_SIZE_16 | \ 338 CSPR_MSEL_NOR | \ 339 CSPR_V) 340 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 341 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 342 CSPR_PORT_SIZE_16 | \ 343 CSPR_MSEL_NOR | \ 344 CSPR_V) 345 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 346 /* NOR Flash Timing Params */ 347 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 348 349 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 350 FTIM0_NOR_TEADC(0x5) | \ 351 FTIM0_NOR_TEAHC(0x5)) 352 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 353 FTIM1_NOR_TRAD_NOR(0x1A) |\ 354 FTIM1_NOR_TSEQRAD_NOR(0x13)) 355 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 356 FTIM2_NOR_TCH(0x4) | \ 357 FTIM2_NOR_TWPH(0x0E) | \ 358 FTIM2_NOR_TWP(0x1c)) 359 #define CONFIG_SYS_NOR_FTIM3 0x0 360 361 #define CONFIG_SYS_FLASH_QUIET_TEST 362 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 363 364 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 365 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 366 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 367 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 368 369 #define CONFIG_SYS_FLASH_EMPTY_INFO 370 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 371 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 372 373 /* NAND Flash on IFC */ 374 #define CONFIG_NAND_FSL_IFC 375 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 376 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 377 #define CONFIG_SYS_NAND_BASE 0xff800000 378 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 379 380 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 381 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 382 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 383 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 384 | CSPR_V) 385 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 386 387 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 388 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 389 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 390 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 391 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 392 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 393 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 394 395 #define CONFIG_SYS_NAND_ONFI_DETECTION 396 397 /* ONFI NAND Flash mode0 Timing Params */ 398 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 399 FTIM0_NAND_TWP(0x18) | \ 400 FTIM0_NAND_TWCHT(0x07) | \ 401 FTIM0_NAND_TWH(0x0a)) 402 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 403 FTIM1_NAND_TWBE(0x39) | \ 404 FTIM1_NAND_TRR(0x0e) | \ 405 FTIM1_NAND_TRP(0x18)) 406 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 407 FTIM2_NAND_TREH(0x0a) | \ 408 FTIM2_NAND_TWHRE(0x1e)) 409 #define CONFIG_SYS_NAND_FTIM3 0x0 410 411 #define CONFIG_SYS_NAND_DDR_LAW 11 412 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 413 #define CONFIG_SYS_MAX_NAND_DEVICE 1 414 415 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 416 417 #if defined(CONFIG_NAND) 418 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 419 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 420 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 421 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 422 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 423 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 424 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 425 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 426 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 427 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 428 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 429 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 430 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 431 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 432 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 433 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 434 #else 435 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 436 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 437 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 438 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 439 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 440 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 441 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 442 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 443 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 444 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 445 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 446 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 447 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 448 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 449 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 450 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 451 #endif 452 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 453 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 454 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 455 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 456 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 457 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 458 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 459 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 460 461 /* CPLD on IFC */ 462 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 463 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 464 #define CONFIG_SYS_CSPR3_EXT (0xf) 465 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 466 | CSPR_PORT_SIZE_8 \ 467 | CSPR_MSEL_GPCM \ 468 | CSPR_V) 469 470 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 471 #define CONFIG_SYS_CSOR3 0x0 472 473 /* CPLD Timing parameters for IFC CS3 */ 474 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 475 FTIM0_GPCM_TEADC(0x0e) | \ 476 FTIM0_GPCM_TEAHC(0x0e)) 477 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 478 FTIM1_GPCM_TRAD(0x1f)) 479 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 480 FTIM2_GPCM_TCH(0x8) | \ 481 FTIM2_GPCM_TWP(0x1f)) 482 #define CONFIG_SYS_CS3_FTIM3 0x0 483 484 #if defined(CONFIG_RAMBOOT_PBL) 485 #define CONFIG_SYS_RAMBOOT 486 #endif 487 488 /* I2C */ 489 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 490 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 491 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 492 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 493 494 #define I2C_MUX_CH_DEFAULT 0x8 495 #define I2C_MUX_CH_VOL_MONITOR 0xa 496 #define I2C_MUX_CH_VSC3316_FS 0xc 497 #define I2C_MUX_CH_VSC3316_BS 0xd 498 499 /* Voltage monitor on channel 2*/ 500 #define I2C_VOL_MONITOR_ADDR 0x40 501 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 502 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 503 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 504 505 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 506 #ifndef CONFIG_SPL_BUILD 507 #define CONFIG_VID 508 #endif 509 #define CONFIG_VOL_MONITOR_IR36021_SET 510 #define CONFIG_VOL_MONITOR_IR36021_READ 511 /* The lowest and highest voltage allowed for T4240RDB */ 512 #define VDD_MV_MIN 819 513 #define VDD_MV_MAX 1212 514 515 /* 516 * eSPI - Enhanced SPI 517 */ 518 #define CONFIG_SF_DEFAULT_SPEED 10000000 519 #define CONFIG_SF_DEFAULT_MODE 0 520 521 /* Qman/Bman */ 522 #ifndef CONFIG_NOBQFMAN 523 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 524 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 525 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 526 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 527 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 528 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 529 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 530 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 531 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 532 CONFIG_SYS_BMAN_CENA_SIZE) 533 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 534 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 535 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 536 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 537 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 538 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 539 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 540 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 541 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 542 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 543 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 544 CONFIG_SYS_QMAN_CENA_SIZE) 545 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 546 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 547 548 #define CONFIG_SYS_DPAA_FMAN 549 #define CONFIG_SYS_DPAA_PME 550 #define CONFIG_SYS_PMAN 551 #define CONFIG_SYS_DPAA_DCE 552 #define CONFIG_SYS_DPAA_RMAN 553 #define CONFIG_SYS_INTERLAKEN 554 555 /* Default address of microcode for the Linux Fman driver */ 556 #if defined(CONFIG_SPIFLASH) 557 /* 558 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 559 * env, so we got 0x110000. 560 */ 561 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 562 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 563 #elif defined(CONFIG_SDCARD) 564 /* 565 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 566 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 567 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 568 */ 569 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 570 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 571 #elif defined(CONFIG_NAND) 572 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 573 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 574 #else 575 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 576 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 577 #endif 578 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 579 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 580 #endif /* CONFIG_NOBQFMAN */ 581 582 #ifdef CONFIG_SYS_DPAA_FMAN 583 #define CONFIG_FMAN_ENET 584 #define CONFIG_PHYLIB_10G 585 #define CONFIG_PHY_VITESSE 586 #define CONFIG_PHY_CORTINA 587 #define CONFIG_SYS_CORTINA_FW_IN_NOR 588 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 589 #define CONFIG_CORTINA_FW_LENGTH 0x40000 590 #define CONFIG_PHY_TERANETICS 591 #define SGMII_PHY_ADDR1 0x0 592 #define SGMII_PHY_ADDR2 0x1 593 #define SGMII_PHY_ADDR3 0x2 594 #define SGMII_PHY_ADDR4 0x3 595 #define SGMII_PHY_ADDR5 0x4 596 #define SGMII_PHY_ADDR6 0x5 597 #define SGMII_PHY_ADDR7 0x6 598 #define SGMII_PHY_ADDR8 0x7 599 #define FM1_10GEC1_PHY_ADDR 0x10 600 #define FM1_10GEC2_PHY_ADDR 0x11 601 #define FM2_10GEC1_PHY_ADDR 0x12 602 #define FM2_10GEC2_PHY_ADDR 0x13 603 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 604 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 605 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 606 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 607 #endif 608 609 /* SATA */ 610 #ifdef CONFIG_FSL_SATA_V2 611 #define CONFIG_SYS_SATA_MAX_DEVICE 2 612 #define CONFIG_SATA1 613 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 614 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 615 #define CONFIG_SATA2 616 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 617 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 618 619 #define CONFIG_LBA48 620 #endif 621 622 #ifdef CONFIG_FMAN_ENET 623 #define CONFIG_ETHPRIME "FM1@DTSEC1" 624 #endif 625 626 /* 627 * USB 628 */ 629 #define CONFIG_USB_EHCI_FSL 630 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 631 #define CONFIG_HAS_FSL_DR_USB 632 633 #ifdef CONFIG_MMC 634 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 635 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 636 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 637 #endif 638 639 640 #define __USB_PHY_TYPE utmi 641 642 /* 643 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 644 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 645 * interleaving. It can be cacheline, page, bank, superbank. 646 * See doc/README.fsl-ddr for details. 647 */ 648 #ifdef CONFIG_ARCH_T4240 649 #define CTRL_INTLV_PREFERED 3way_4KB 650 #else 651 #define CTRL_INTLV_PREFERED cacheline 652 #endif 653 654 #define CONFIG_EXTRA_ENV_SETTINGS \ 655 "hwconfig=fsl_ddr:" \ 656 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 657 "bank_intlv=auto;" \ 658 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 659 "netdev=eth0\0" \ 660 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 661 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 662 "tftpflash=tftpboot $loadaddr $uboot && " \ 663 "protect off $ubootaddr +$filesize && " \ 664 "erase $ubootaddr +$filesize && " \ 665 "cp.b $loadaddr $ubootaddr $filesize && " \ 666 "protect on $ubootaddr +$filesize && " \ 667 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 668 "consoledev=ttyS0\0" \ 669 "ramdiskaddr=2000000\0" \ 670 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 671 "fdtaddr=1e00000\0" \ 672 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 673 "bdev=sda3\0" 674 675 #define CONFIG_HVBOOT \ 676 "setenv bootargs config-addr=0x60000000; " \ 677 "bootm 0x01000000 - 0x00f00000" 678 679 #define CONFIG_LINUX \ 680 "setenv bootargs root=/dev/ram rw " \ 681 "console=$consoledev,$baudrate $othbootargs;" \ 682 "setenv ramdiskaddr 0x02000000;" \ 683 "setenv fdtaddr 0x00c00000;" \ 684 "setenv loadaddr 0x1000000;" \ 685 "bootm $loadaddr $ramdiskaddr $fdtaddr" 686 687 #define CONFIG_HDBOOT \ 688 "setenv bootargs root=/dev/$bdev rw " \ 689 "console=$consoledev,$baudrate $othbootargs;" \ 690 "tftp $loadaddr $bootfile;" \ 691 "tftp $fdtaddr $fdtfile;" \ 692 "bootm $loadaddr - $fdtaddr" 693 694 #define CONFIG_NFSBOOTCOMMAND \ 695 "setenv bootargs root=/dev/nfs rw " \ 696 "nfsroot=$serverip:$rootpath " \ 697 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 698 "console=$consoledev,$baudrate $othbootargs;" \ 699 "tftp $loadaddr $bootfile;" \ 700 "tftp $fdtaddr $fdtfile;" \ 701 "bootm $loadaddr - $fdtaddr" 702 703 #define CONFIG_RAMBOOTCOMMAND \ 704 "setenv bootargs root=/dev/ram rw " \ 705 "console=$consoledev,$baudrate $othbootargs;" \ 706 "tftp $ramdiskaddr $ramdiskfile;" \ 707 "tftp $loadaddr $bootfile;" \ 708 "tftp $fdtaddr $fdtfile;" \ 709 "bootm $loadaddr $ramdiskaddr $fdtaddr" 710 711 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 712 713 #include <asm/fsl_secure_boot.h> 714 715 #endif /* __CONFIG_H */ 716