1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_FSL_SATA_V2 14 #define CONFIG_PCIE4 15 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 20 #ifndef CONFIG_SDCARD 21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 23 #else 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SYS_TEXT_BASE 0x00201000 27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 #define CONFIG_SPL_MAX_SIZE 0x28000 30 #define RESET_VECTOR_OFFSET 0x27FFC 31 #define BOOT_PAGE_OFFSET 0x27000 32 33 #ifdef CONFIG_SDCARD 34 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 35 #define CONFIG_SPL_MMC_MINIMAL 36 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 37 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 38 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 39 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 40 #ifndef CONFIG_SPL_BUILD 41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 42 #endif 43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 44 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg 45 #define CONFIG_SPL_MMC_BOOT 46 #endif 47 48 #ifdef CONFIG_SPL_BUILD 49 #define CONFIG_SPL_SKIP_RELOCATE 50 #define CONFIG_SPL_COMMON_INIT_DDR 51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 52 #endif 53 54 #endif 55 #endif /* CONFIG_RAMBOOT_PBL */ 56 57 #define CONFIG_DDR_ECC 58 59 #define CONFIG_CMD_REGINFO 60 61 /* High Level Configuration Options */ 62 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 63 #define CONFIG_MP /* support multiple processors */ 64 65 #ifndef CONFIG_SYS_TEXT_BASE 66 #define CONFIG_SYS_TEXT_BASE 0xeff40000 67 #endif 68 69 #ifndef CONFIG_RESET_VECTOR_ADDRESS 70 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 71 #endif 72 73 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 74 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 75 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 76 #define CONFIG_PCIE1 /* PCIE controller 1 */ 77 #define CONFIG_PCIE2 /* PCIE controller 2 */ 78 #define CONFIG_PCIE3 /* PCIE controller 3 */ 79 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 80 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 81 82 #define CONFIG_ENV_OVERWRITE 83 84 /* 85 * These can be toggled for performance analysis, otherwise use default. 86 */ 87 #define CONFIG_SYS_CACHE_STASHING 88 #define CONFIG_BTB /* toggle branch predition */ 89 #ifdef CONFIG_DDR_ECC 90 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 91 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 92 #endif 93 94 #define CONFIG_ENABLE_36BIT_PHYS 95 96 #define CONFIG_ADDR_MAP 97 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 98 99 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 100 #define CONFIG_SYS_MEMTEST_END 0x00400000 101 #define CONFIG_SYS_ALT_MEMTEST 102 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 103 104 /* 105 * Config the L3 Cache as L3 SRAM 106 */ 107 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 108 #define CONFIG_SYS_L3_SIZE (512 << 10) 109 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 110 #ifdef CONFIG_RAMBOOT_PBL 111 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 112 #endif 113 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 114 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 115 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 116 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 117 118 #define CONFIG_SYS_DCSRBAR 0xf0000000 119 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 120 121 /* 122 * DDR Setup 123 */ 124 #define CONFIG_VERY_BIG_RAM 125 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 126 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 127 128 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 129 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 130 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 131 132 #define CONFIG_DDR_SPD 133 134 /* 135 * IFC Definitions 136 */ 137 #define CONFIG_SYS_FLASH_BASE 0xe0000000 138 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 139 140 #ifdef CONFIG_SPL_BUILD 141 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 142 #else 143 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 144 #endif 145 146 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 147 #define CONFIG_MISC_INIT_R 148 149 #define CONFIG_HWCONFIG 150 151 /* define to use L1 as initial stack */ 152 #define CONFIG_L1_INIT_RAM 153 #define CONFIG_SYS_INIT_RAM_LOCK 154 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 155 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 156 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 157 /* The assembler doesn't like typecast */ 158 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 159 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 160 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 161 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 162 163 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 164 GENERATED_GBL_DATA_SIZE) 165 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 166 167 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 168 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 169 170 /* Serial Port - controlled on board with jumper J8 171 * open - index 2 172 * shorted - index 1 173 */ 174 #define CONFIG_CONS_INDEX 1 175 #define CONFIG_SYS_NS16550_SERIAL 176 #define CONFIG_SYS_NS16550_REG_SIZE 1 177 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 178 179 #define CONFIG_SYS_BAUDRATE_TABLE \ 180 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 181 182 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 183 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 184 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 185 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 186 187 /* I2C */ 188 #define CONFIG_SYS_I2C 189 #define CONFIG_SYS_I2C_FSL 190 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 191 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 192 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 193 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 194 195 /* 196 * General PCI 197 * Memory space is mapped 1-1, but I/O space must start from 0. 198 */ 199 200 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 201 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 202 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 203 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 204 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 205 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 206 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 207 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 208 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 209 210 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 211 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 212 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 213 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 214 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 215 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 216 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 217 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 218 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 219 220 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 221 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 222 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 223 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 224 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 225 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 226 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 227 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 228 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 229 230 /* controller 4, Base address 203000 */ 231 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 232 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 233 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 234 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 235 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 236 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 237 238 #ifdef CONFIG_PCI 239 #define CONFIG_PCI_INDIRECT_BRIDGE 240 241 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 242 #endif /* CONFIG_PCI */ 243 244 /* SATA */ 245 #ifdef CONFIG_FSL_SATA_V2 246 #define CONFIG_LIBATA 247 #define CONFIG_FSL_SATA 248 249 #define CONFIG_SYS_SATA_MAX_DEVICE 2 250 #define CONFIG_SATA1 251 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 252 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 253 #define CONFIG_SATA2 254 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 255 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 256 257 #define CONFIG_LBA48 258 #define CONFIG_CMD_SATA 259 #endif 260 261 #ifdef CONFIG_FMAN_ENET 262 #define CONFIG_MII /* MII PHY management */ 263 #define CONFIG_ETHPRIME "FM1@DTSEC1" 264 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 265 #endif 266 267 /* 268 * Environment 269 */ 270 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 271 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 272 273 /* 274 * Command line configuration. 275 */ 276 #define CONFIG_CMD_ERRATA 277 #define CONFIG_CMD_IRQ 278 279 #ifdef CONFIG_PCI 280 #define CONFIG_CMD_PCI 281 #endif 282 283 /* 284 * Miscellaneous configurable options 285 */ 286 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 287 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 288 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 289 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 290 #ifdef CONFIG_CMD_KGDB 291 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 292 #else 293 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 294 #endif 295 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 296 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 297 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 298 299 /* 300 * For booting Linux, the board info and command line data 301 * have to be in the first 64 MB of memory, since this is 302 * the maximum mapped by the Linux kernel during initialization. 303 */ 304 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 305 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 306 307 #ifdef CONFIG_CMD_KGDB 308 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 309 #endif 310 311 /* 312 * Environment Configuration 313 */ 314 #define CONFIG_ROOTPATH "/opt/nfsroot" 315 #define CONFIG_BOOTFILE "uImage" 316 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 317 318 /* default location for tftp and bootm */ 319 #define CONFIG_LOADADDR 1000000 320 321 #define CONFIG_BAUDRATE 115200 322 323 #define CONFIG_HVBOOT \ 324 "setenv bootargs config-addr=0x60000000; " \ 325 "bootm 0x01000000 - 0x00f00000" 326 327 #ifndef CONFIG_MTD_NOR_FLASH 328 #ifndef CONFIG_RAMBOOT_PBL 329 #define CONFIG_ENV_IS_NOWHERE 330 #endif 331 #else 332 #define CONFIG_FLASH_CFI_DRIVER 333 #define CONFIG_SYS_FLASH_CFI 334 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 335 #endif 336 337 #if defined(CONFIG_SPIFLASH) 338 #define CONFIG_SYS_EXTRA_ENV_RELOC 339 #define CONFIG_ENV_IS_IN_SPI_FLASH 340 #define CONFIG_ENV_SPI_BUS 0 341 #define CONFIG_ENV_SPI_CS 0 342 #define CONFIG_ENV_SPI_MAX_HZ 10000000 343 #define CONFIG_ENV_SPI_MODE 0 344 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 345 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 346 #define CONFIG_ENV_SECT_SIZE 0x10000 347 #elif defined(CONFIG_SDCARD) 348 #define CONFIG_SYS_EXTRA_ENV_RELOC 349 #define CONFIG_ENV_IS_IN_MMC 350 #define CONFIG_SYS_MMC_ENV_DEV 0 351 #define CONFIG_ENV_SIZE 0x2000 352 #define CONFIG_ENV_OFFSET (512 * 0x800) 353 #elif defined(CONFIG_NAND) 354 #define CONFIG_SYS_EXTRA_ENV_RELOC 355 #define CONFIG_ENV_IS_IN_NAND 356 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 357 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 358 #elif defined(CONFIG_ENV_IS_NOWHERE) 359 #define CONFIG_ENV_SIZE 0x2000 360 #else 361 #define CONFIG_ENV_IS_IN_FLASH 362 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 363 #define CONFIG_ENV_SIZE 0x2000 364 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 365 #endif 366 367 #define CONFIG_SYS_CLK_FREQ 66666666 368 #define CONFIG_DDR_CLK_FREQ 133333333 369 370 #ifndef __ASSEMBLY__ 371 unsigned long get_board_sys_clk(void); 372 unsigned long get_board_ddr_clk(void); 373 #endif 374 375 /* 376 * DDR Setup 377 */ 378 #define CONFIG_SYS_SPD_BUS_NUM 0 379 #define SPD_EEPROM_ADDRESS1 0x52 380 #define SPD_EEPROM_ADDRESS2 0x54 381 #define SPD_EEPROM_ADDRESS3 0x56 382 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 383 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 384 385 /* 386 * IFC Definitions 387 */ 388 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 389 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 390 + 0x8000000) | \ 391 CSPR_PORT_SIZE_16 | \ 392 CSPR_MSEL_NOR | \ 393 CSPR_V) 394 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 395 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 396 CSPR_PORT_SIZE_16 | \ 397 CSPR_MSEL_NOR | \ 398 CSPR_V) 399 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 400 /* NOR Flash Timing Params */ 401 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 402 403 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 404 FTIM0_NOR_TEADC(0x5) | \ 405 FTIM0_NOR_TEAHC(0x5)) 406 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 407 FTIM1_NOR_TRAD_NOR(0x1A) |\ 408 FTIM1_NOR_TSEQRAD_NOR(0x13)) 409 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 410 FTIM2_NOR_TCH(0x4) | \ 411 FTIM2_NOR_TWPH(0x0E) | \ 412 FTIM2_NOR_TWP(0x1c)) 413 #define CONFIG_SYS_NOR_FTIM3 0x0 414 415 #define CONFIG_SYS_FLASH_QUIET_TEST 416 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 417 418 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 419 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 420 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 421 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 422 423 #define CONFIG_SYS_FLASH_EMPTY_INFO 424 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 425 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 426 427 /* NAND Flash on IFC */ 428 #define CONFIG_NAND_FSL_IFC 429 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 430 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 431 #define CONFIG_SYS_NAND_BASE 0xff800000 432 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 433 434 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 435 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 436 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 437 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 438 | CSPR_V) 439 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 440 441 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 442 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 443 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 444 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 445 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 446 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 447 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 448 449 #define CONFIG_SYS_NAND_ONFI_DETECTION 450 451 /* ONFI NAND Flash mode0 Timing Params */ 452 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 453 FTIM0_NAND_TWP(0x18) | \ 454 FTIM0_NAND_TWCHT(0x07) | \ 455 FTIM0_NAND_TWH(0x0a)) 456 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 457 FTIM1_NAND_TWBE(0x39) | \ 458 FTIM1_NAND_TRR(0x0e) | \ 459 FTIM1_NAND_TRP(0x18)) 460 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 461 FTIM2_NAND_TREH(0x0a) | \ 462 FTIM2_NAND_TWHRE(0x1e)) 463 #define CONFIG_SYS_NAND_FTIM3 0x0 464 465 #define CONFIG_SYS_NAND_DDR_LAW 11 466 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 467 #define CONFIG_SYS_MAX_NAND_DEVICE 1 468 #define CONFIG_CMD_NAND 469 470 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 471 472 #if defined(CONFIG_NAND) 473 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 474 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 475 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 476 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 477 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 478 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 479 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 480 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 481 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 482 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 483 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 484 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 485 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 486 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 487 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 488 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 489 #else 490 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 491 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 492 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 493 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 494 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 495 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 496 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 497 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 498 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 499 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 500 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 501 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 502 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 503 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 504 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 505 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 506 #endif 507 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 508 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 509 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 510 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 511 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 512 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 513 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 514 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 515 516 /* CPLD on IFC */ 517 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 518 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 519 #define CONFIG_SYS_CSPR3_EXT (0xf) 520 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 521 | CSPR_PORT_SIZE_8 \ 522 | CSPR_MSEL_GPCM \ 523 | CSPR_V) 524 525 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 526 #define CONFIG_SYS_CSOR3 0x0 527 528 /* CPLD Timing parameters for IFC CS3 */ 529 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 530 FTIM0_GPCM_TEADC(0x0e) | \ 531 FTIM0_GPCM_TEAHC(0x0e)) 532 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 533 FTIM1_GPCM_TRAD(0x1f)) 534 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 535 FTIM2_GPCM_TCH(0x8) | \ 536 FTIM2_GPCM_TWP(0x1f)) 537 #define CONFIG_SYS_CS3_FTIM3 0x0 538 539 #if defined(CONFIG_RAMBOOT_PBL) 540 #define CONFIG_SYS_RAMBOOT 541 #endif 542 543 /* I2C */ 544 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 545 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 546 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 547 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 548 549 #define I2C_MUX_CH_DEFAULT 0x8 550 #define I2C_MUX_CH_VOL_MONITOR 0xa 551 #define I2C_MUX_CH_VSC3316_FS 0xc 552 #define I2C_MUX_CH_VSC3316_BS 0xd 553 554 /* Voltage monitor on channel 2*/ 555 #define I2C_VOL_MONITOR_ADDR 0x40 556 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 557 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 558 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 559 560 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 561 #ifndef CONFIG_SPL_BUILD 562 #define CONFIG_VID 563 #endif 564 #define CONFIG_VOL_MONITOR_IR36021_SET 565 #define CONFIG_VOL_MONITOR_IR36021_READ 566 /* The lowest and highest voltage allowed for T4240RDB */ 567 #define VDD_MV_MIN 819 568 #define VDD_MV_MAX 1212 569 570 /* 571 * eSPI - Enhanced SPI 572 */ 573 #define CONFIG_SF_DEFAULT_SPEED 10000000 574 #define CONFIG_SF_DEFAULT_MODE 0 575 576 /* Qman/Bman */ 577 #ifndef CONFIG_NOBQFMAN 578 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 579 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 580 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 581 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 582 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 583 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 584 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 585 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 586 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 587 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 588 CONFIG_SYS_BMAN_CENA_SIZE) 589 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 590 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 591 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 592 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 593 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 594 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 595 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 596 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 597 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 598 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 599 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 600 CONFIG_SYS_QMAN_CENA_SIZE) 601 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 602 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 603 604 #define CONFIG_SYS_DPAA_FMAN 605 #define CONFIG_SYS_DPAA_PME 606 #define CONFIG_SYS_PMAN 607 #define CONFIG_SYS_DPAA_DCE 608 #define CONFIG_SYS_DPAA_RMAN 609 #define CONFIG_SYS_INTERLAKEN 610 611 /* Default address of microcode for the Linux Fman driver */ 612 #if defined(CONFIG_SPIFLASH) 613 /* 614 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 615 * env, so we got 0x110000. 616 */ 617 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 618 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 619 #elif defined(CONFIG_SDCARD) 620 /* 621 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 622 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 623 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 624 */ 625 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 626 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 627 #elif defined(CONFIG_NAND) 628 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 629 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 630 #else 631 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 632 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 633 #endif 634 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 635 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 636 #endif /* CONFIG_NOBQFMAN */ 637 638 #ifdef CONFIG_SYS_DPAA_FMAN 639 #define CONFIG_FMAN_ENET 640 #define CONFIG_PHYLIB_10G 641 #define CONFIG_PHY_VITESSE 642 #define CONFIG_PHY_CORTINA 643 #define CONFIG_SYS_CORTINA_FW_IN_NOR 644 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 645 #define CONFIG_CORTINA_FW_LENGTH 0x40000 646 #define CONFIG_PHY_TERANETICS 647 #define SGMII_PHY_ADDR1 0x0 648 #define SGMII_PHY_ADDR2 0x1 649 #define SGMII_PHY_ADDR3 0x2 650 #define SGMII_PHY_ADDR4 0x3 651 #define SGMII_PHY_ADDR5 0x4 652 #define SGMII_PHY_ADDR6 0x5 653 #define SGMII_PHY_ADDR7 0x6 654 #define SGMII_PHY_ADDR8 0x7 655 #define FM1_10GEC1_PHY_ADDR 0x10 656 #define FM1_10GEC2_PHY_ADDR 0x11 657 #define FM2_10GEC1_PHY_ADDR 0x12 658 #define FM2_10GEC2_PHY_ADDR 0x13 659 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 660 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 661 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 662 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 663 #endif 664 665 /* SATA */ 666 #ifdef CONFIG_FSL_SATA_V2 667 #define CONFIG_LIBATA 668 #define CONFIG_FSL_SATA 669 670 #define CONFIG_SYS_SATA_MAX_DEVICE 2 671 #define CONFIG_SATA1 672 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 673 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 674 #define CONFIG_SATA2 675 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 676 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 677 678 #define CONFIG_LBA48 679 #define CONFIG_CMD_SATA 680 #endif 681 682 #ifdef CONFIG_FMAN_ENET 683 #define CONFIG_MII /* MII PHY management */ 684 #define CONFIG_ETHPRIME "FM1@DTSEC1" 685 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 686 #endif 687 688 /* 689 * USB 690 */ 691 #define CONFIG_USB_EHCI 692 #define CONFIG_USB_EHCI_FSL 693 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 694 #define CONFIG_HAS_FSL_DR_USB 695 696 #ifdef CONFIG_MMC 697 #define CONFIG_FSL_ESDHC 698 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 699 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 700 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 701 #endif 702 703 /* Hash command with SHA acceleration supported in hardware */ 704 #ifdef CONFIG_FSL_CAAM 705 #define CONFIG_CMD_HASH 706 #define CONFIG_SHA_HW_ACCEL 707 #endif 708 709 710 #define __USB_PHY_TYPE utmi 711 712 /* 713 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 714 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 715 * interleaving. It can be cacheline, page, bank, superbank. 716 * See doc/README.fsl-ddr for details. 717 */ 718 #ifdef CONFIG_ARCH_T4240 719 #define CTRL_INTLV_PREFERED 3way_4KB 720 #else 721 #define CTRL_INTLV_PREFERED cacheline 722 #endif 723 724 #define CONFIG_EXTRA_ENV_SETTINGS \ 725 "hwconfig=fsl_ddr:" \ 726 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 727 "bank_intlv=auto;" \ 728 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 729 "netdev=eth0\0" \ 730 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 731 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 732 "tftpflash=tftpboot $loadaddr $uboot && " \ 733 "protect off $ubootaddr +$filesize && " \ 734 "erase $ubootaddr +$filesize && " \ 735 "cp.b $loadaddr $ubootaddr $filesize && " \ 736 "protect on $ubootaddr +$filesize && " \ 737 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 738 "consoledev=ttyS0\0" \ 739 "ramdiskaddr=2000000\0" \ 740 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 741 "fdtaddr=1e00000\0" \ 742 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 743 "bdev=sda3\0" 744 745 #define CONFIG_HVBOOT \ 746 "setenv bootargs config-addr=0x60000000; " \ 747 "bootm 0x01000000 - 0x00f00000" 748 749 #define CONFIG_LINUX \ 750 "setenv bootargs root=/dev/ram rw " \ 751 "console=$consoledev,$baudrate $othbootargs;" \ 752 "setenv ramdiskaddr 0x02000000;" \ 753 "setenv fdtaddr 0x00c00000;" \ 754 "setenv loadaddr 0x1000000;" \ 755 "bootm $loadaddr $ramdiskaddr $fdtaddr" 756 757 #define CONFIG_HDBOOT \ 758 "setenv bootargs root=/dev/$bdev rw " \ 759 "console=$consoledev,$baudrate $othbootargs;" \ 760 "tftp $loadaddr $bootfile;" \ 761 "tftp $fdtaddr $fdtfile;" \ 762 "bootm $loadaddr - $fdtaddr" 763 764 #define CONFIG_NFSBOOTCOMMAND \ 765 "setenv bootargs root=/dev/nfs rw " \ 766 "nfsroot=$serverip:$rootpath " \ 767 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 768 "console=$consoledev,$baudrate $othbootargs;" \ 769 "tftp $loadaddr $bootfile;" \ 770 "tftp $fdtaddr $fdtfile;" \ 771 "bootm $loadaddr - $fdtaddr" 772 773 #define CONFIG_RAMBOOTCOMMAND \ 774 "setenv bootargs root=/dev/ram rw " \ 775 "console=$consoledev,$baudrate $othbootargs;" \ 776 "tftp $ramdiskaddr $ramdiskfile;" \ 777 "tftp $loadaddr $bootfile;" \ 778 "tftp $fdtaddr $fdtfile;" \ 779 "bootm $loadaddr $ramdiskaddr $fdtaddr" 780 781 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 782 783 #include <asm/fsl_secure_boot.h> 784 785 #endif /* __CONFIG_H */ 786