1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240RDB 14 #define CONFIG_PHYS_64BIT 15 #define CONFIG_SYS_GENERIC_BOARD 16 #define CONFIG_DISPLAY_BOARDINFO 17 18 #define CONFIG_FSL_SATA_V2 19 #define CONFIG_PCIE4 20 21 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 22 23 #ifdef CONFIG_RAMBOOT_PBL 24 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 25 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg 26 #ifndef CONFIG_SDCARD 27 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 28 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 29 #else 30 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 31 #define CONFIG_SPL_ENV_SUPPORT 32 #define CONFIG_SPL_SERIAL_SUPPORT 33 #define CONFIG_SPL_FLUSH_IMAGE 34 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 35 #define CONFIG_SPL_LIBGENERIC_SUPPORT 36 #define CONFIG_SPL_LIBCOMMON_SUPPORT 37 #define CONFIG_SPL_I2C_SUPPORT 38 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 39 #define CONFIG_FSL_LAW /* Use common FSL init code */ 40 #define CONFIG_SYS_TEXT_BASE 0x00201000 41 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 42 #define CONFIG_SPL_PAD_TO 0x40000 43 #define CONFIG_SPL_MAX_SIZE 0x28000 44 #define RESET_VECTOR_OFFSET 0x27FFC 45 #define BOOT_PAGE_OFFSET 0x27000 46 47 #ifdef CONFIG_SDCARD 48 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 49 #define CONFIG_SPL_MMC_SUPPORT 50 #define CONFIG_SPL_MMC_MINIMAL 51 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 52 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 53 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 54 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 55 #ifndef CONFIG_SPL_BUILD 56 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 57 #endif 58 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 59 #define CONFIG_SPL_MMC_BOOT 60 #endif 61 62 #ifdef CONFIG_SPL_BUILD 63 #define CONFIG_SPL_SKIP_RELOCATE 64 #define CONFIG_SPL_COMMON_INIT_DDR 65 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 66 #define CONFIG_SYS_NO_FLASH 67 #endif 68 69 #endif 70 #endif /* CONFIG_RAMBOOT_PBL */ 71 72 #define CONFIG_DDR_ECC 73 74 #define CONFIG_CMD_REGINFO 75 76 /* High Level Configuration Options */ 77 #define CONFIG_BOOKE 78 #define CONFIG_E500 /* BOOKE e500 family */ 79 #define CONFIG_E500MC /* BOOKE e500mc family */ 80 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 81 #define CONFIG_MP /* support multiple processors */ 82 83 #ifndef CONFIG_SYS_TEXT_BASE 84 #define CONFIG_SYS_TEXT_BASE 0xeff40000 85 #endif 86 87 #ifndef CONFIG_RESET_VECTOR_ADDRESS 88 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 89 #endif 90 91 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 92 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 93 #define CONFIG_FSL_IFC /* Enable IFC Support */ 94 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 95 #define CONFIG_PCI /* Enable PCI/PCIE */ 96 #define CONFIG_PCIE1 /* PCIE controler 1 */ 97 #define CONFIG_PCIE2 /* PCIE controler 2 */ 98 #define CONFIG_PCIE3 /* PCIE controler 3 */ 99 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 100 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 101 102 #define CONFIG_FSL_LAW /* Use common FSL init code */ 103 104 #define CONFIG_ENV_OVERWRITE 105 106 /* 107 * These can be toggled for performance analysis, otherwise use default. 108 */ 109 #define CONFIG_SYS_CACHE_STASHING 110 #define CONFIG_BTB /* toggle branch predition */ 111 #ifdef CONFIG_DDR_ECC 112 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 113 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 114 #endif 115 116 #define CONFIG_ENABLE_36BIT_PHYS 117 118 #define CONFIG_ADDR_MAP 119 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 120 121 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 122 #define CONFIG_SYS_MEMTEST_END 0x00400000 123 #define CONFIG_SYS_ALT_MEMTEST 124 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 125 126 /* 127 * Config the L3 Cache as L3 SRAM 128 */ 129 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 130 #define CONFIG_SYS_L3_SIZE (512 << 10) 131 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 132 #ifdef CONFIG_RAMBOOT_PBL 133 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 134 #endif 135 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 136 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 137 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 138 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 139 140 #define CONFIG_SYS_DCSRBAR 0xf0000000 141 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 142 143 /* 144 * DDR Setup 145 */ 146 #define CONFIG_VERY_BIG_RAM 147 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 148 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 149 150 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 151 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 152 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 153 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 154 155 #define CONFIG_DDR_SPD 156 #define CONFIG_SYS_FSL_DDR3 157 158 159 /* 160 * IFC Definitions 161 */ 162 #define CONFIG_SYS_FLASH_BASE 0xe0000000 163 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 164 165 166 #ifdef CONFIG_SPL_BUILD 167 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 168 #else 169 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 170 #endif 171 172 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 173 #define CONFIG_MISC_INIT_R 174 175 #define CONFIG_HWCONFIG 176 177 /* define to use L1 as initial stack */ 178 #define CONFIG_L1_INIT_RAM 179 #define CONFIG_SYS_INIT_RAM_LOCK 180 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 181 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 182 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 183 /* The assembler doesn't like typecast */ 184 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 185 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 186 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 187 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 188 189 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 190 GENERATED_GBL_DATA_SIZE) 191 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 192 193 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 194 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 195 196 /* Serial Port - controlled on board with jumper J8 197 * open - index 2 198 * shorted - index 1 199 */ 200 #define CONFIG_CONS_INDEX 1 201 #define CONFIG_SYS_NS16550 202 #define CONFIG_SYS_NS16550_SERIAL 203 #define CONFIG_SYS_NS16550_REG_SIZE 1 204 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 205 206 #define CONFIG_SYS_BAUDRATE_TABLE \ 207 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 208 209 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 210 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 211 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 212 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 213 214 /* Use the HUSH parser */ 215 #define CONFIG_SYS_HUSH_PARSER 216 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 217 218 /* pass open firmware flat tree */ 219 #define CONFIG_OF_LIBFDT 220 #define CONFIG_OF_BOARD_SETUP 221 #define CONFIG_OF_STDOUT_VIA_ALIAS 222 223 /* new uImage format support */ 224 #define CONFIG_FIT 225 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 226 227 /* I2C */ 228 #define CONFIG_SYS_I2C 229 #define CONFIG_SYS_I2C_FSL 230 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 231 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 232 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 233 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 234 235 /* 236 * General PCI 237 * Memory space is mapped 1-1, but I/O space must start from 0. 238 */ 239 240 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 241 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 242 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 243 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 244 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 245 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 246 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 247 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 248 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 249 250 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 251 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 252 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 253 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 254 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 255 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 256 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 257 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 258 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 259 260 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 261 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 262 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 263 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 264 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 265 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 266 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 267 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 268 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 269 270 /* controller 4, Base address 203000 */ 271 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 272 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 273 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 274 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 275 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 276 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 277 278 #ifdef CONFIG_PCI 279 #define CONFIG_PCI_INDIRECT_BRIDGE 280 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 281 282 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 283 #define CONFIG_DOS_PARTITION 284 #endif /* CONFIG_PCI */ 285 286 /* SATA */ 287 #ifdef CONFIG_FSL_SATA_V2 288 #define CONFIG_LIBATA 289 #define CONFIG_FSL_SATA 290 291 #define CONFIG_SYS_SATA_MAX_DEVICE 2 292 #define CONFIG_SATA1 293 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 294 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 295 #define CONFIG_SATA2 296 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 297 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 298 299 #define CONFIG_LBA48 300 #define CONFIG_CMD_SATA 301 #define CONFIG_DOS_PARTITION 302 #define CONFIG_CMD_EXT2 303 #endif 304 305 #ifdef CONFIG_FMAN_ENET 306 #define CONFIG_MII /* MII PHY management */ 307 #define CONFIG_ETHPRIME "FM1@DTSEC1" 308 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 309 #endif 310 311 /* 312 * Environment 313 */ 314 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 315 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 316 317 /* 318 * Command line configuration. 319 */ 320 #define CONFIG_CMD_DHCP 321 #define CONFIG_CMD_ERRATA 322 #define CONFIG_CMD_GREPENV 323 #define CONFIG_CMD_IRQ 324 #define CONFIG_CMD_I2C 325 #define CONFIG_CMD_MII 326 #define CONFIG_CMD_PING 327 328 #ifdef CONFIG_PCI 329 #define CONFIG_CMD_PCI 330 #endif 331 332 /* 333 * Miscellaneous configurable options 334 */ 335 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 336 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 337 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 338 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 339 #ifdef CONFIG_CMD_KGDB 340 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 341 #else 342 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 343 #endif 344 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 345 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 346 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 347 348 /* 349 * For booting Linux, the board info and command line data 350 * have to be in the first 64 MB of memory, since this is 351 * the maximum mapped by the Linux kernel during initialization. 352 */ 353 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 354 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 355 356 #ifdef CONFIG_CMD_KGDB 357 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 358 #endif 359 360 /* 361 * Environment Configuration 362 */ 363 #define CONFIG_ROOTPATH "/opt/nfsroot" 364 #define CONFIG_BOOTFILE "uImage" 365 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 366 367 /* default location for tftp and bootm */ 368 #define CONFIG_LOADADDR 1000000 369 370 371 #define CONFIG_BAUDRATE 115200 372 373 #define CONFIG_HVBOOT \ 374 "setenv bootargs config-addr=0x60000000; " \ 375 "bootm 0x01000000 - 0x00f00000" 376 377 #ifdef CONFIG_SYS_NO_FLASH 378 #ifndef CONFIG_RAMBOOT_PBL 379 #define CONFIG_ENV_IS_NOWHERE 380 #endif 381 #else 382 #define CONFIG_FLASH_CFI_DRIVER 383 #define CONFIG_SYS_FLASH_CFI 384 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 385 #endif 386 387 #if defined(CONFIG_SPIFLASH) 388 #define CONFIG_SYS_EXTRA_ENV_RELOC 389 #define CONFIG_ENV_IS_IN_SPI_FLASH 390 #define CONFIG_ENV_SPI_BUS 0 391 #define CONFIG_ENV_SPI_CS 0 392 #define CONFIG_ENV_SPI_MAX_HZ 10000000 393 #define CONFIG_ENV_SPI_MODE 0 394 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 395 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 396 #define CONFIG_ENV_SECT_SIZE 0x10000 397 #elif defined(CONFIG_SDCARD) 398 #define CONFIG_SYS_EXTRA_ENV_RELOC 399 #define CONFIG_ENV_IS_IN_MMC 400 #define CONFIG_SYS_MMC_ENV_DEV 0 401 #define CONFIG_ENV_SIZE 0x2000 402 #define CONFIG_ENV_OFFSET (512 * 0x800) 403 #elif defined(CONFIG_NAND) 404 #define CONFIG_SYS_EXTRA_ENV_RELOC 405 #define CONFIG_ENV_IS_IN_NAND 406 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 407 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 408 #elif defined(CONFIG_ENV_IS_NOWHERE) 409 #define CONFIG_ENV_SIZE 0x2000 410 #else 411 #define CONFIG_ENV_IS_IN_FLASH 412 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 413 #define CONFIG_ENV_SIZE 0x2000 414 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 415 #endif 416 417 #define CONFIG_SYS_CLK_FREQ 66666666 418 #define CONFIG_DDR_CLK_FREQ 133333333 419 420 #ifndef __ASSEMBLY__ 421 unsigned long get_board_sys_clk(void); 422 unsigned long get_board_ddr_clk(void); 423 #endif 424 425 /* 426 * DDR Setup 427 */ 428 #define CONFIG_SYS_SPD_BUS_NUM 0 429 #define SPD_EEPROM_ADDRESS1 0x52 430 #define SPD_EEPROM_ADDRESS2 0x54 431 #define SPD_EEPROM_ADDRESS3 0x56 432 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 433 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 434 435 /* 436 * IFC Definitions 437 */ 438 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 439 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 440 + 0x8000000) | \ 441 CSPR_PORT_SIZE_16 | \ 442 CSPR_MSEL_NOR | \ 443 CSPR_V) 444 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 445 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 446 CSPR_PORT_SIZE_16 | \ 447 CSPR_MSEL_NOR | \ 448 CSPR_V) 449 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 450 /* NOR Flash Timing Params */ 451 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 452 453 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 454 FTIM0_NOR_TEADC(0x5) | \ 455 FTIM0_NOR_TEAHC(0x5)) 456 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 457 FTIM1_NOR_TRAD_NOR(0x1A) |\ 458 FTIM1_NOR_TSEQRAD_NOR(0x13)) 459 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 460 FTIM2_NOR_TCH(0x4) | \ 461 FTIM2_NOR_TWPH(0x0E) | \ 462 FTIM2_NOR_TWP(0x1c)) 463 #define CONFIG_SYS_NOR_FTIM3 0x0 464 465 #define CONFIG_SYS_FLASH_QUIET_TEST 466 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 467 468 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 469 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 470 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 471 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 472 473 #define CONFIG_SYS_FLASH_EMPTY_INFO 474 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 475 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 476 477 /* NAND Flash on IFC */ 478 #define CONFIG_NAND_FSL_IFC 479 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 480 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 481 #define CONFIG_SYS_NAND_BASE 0xff800000 482 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 483 484 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 485 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 486 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 487 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 488 | CSPR_V) 489 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 490 491 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 492 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 493 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 494 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 495 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 496 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 497 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 498 499 #define CONFIG_SYS_NAND_ONFI_DETECTION 500 501 /* ONFI NAND Flash mode0 Timing Params */ 502 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 503 FTIM0_NAND_TWP(0x18) | \ 504 FTIM0_NAND_TWCHT(0x07) | \ 505 FTIM0_NAND_TWH(0x0a)) 506 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 507 FTIM1_NAND_TWBE(0x39) | \ 508 FTIM1_NAND_TRR(0x0e) | \ 509 FTIM1_NAND_TRP(0x18)) 510 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 511 FTIM2_NAND_TREH(0x0a) | \ 512 FTIM2_NAND_TWHRE(0x1e)) 513 #define CONFIG_SYS_NAND_FTIM3 0x0 514 515 #define CONFIG_SYS_NAND_DDR_LAW 11 516 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 517 #define CONFIG_SYS_MAX_NAND_DEVICE 1 518 #define CONFIG_CMD_NAND 519 520 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 521 522 #if defined(CONFIG_NAND) 523 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 524 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 525 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 526 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 527 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 528 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 529 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 530 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 531 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 532 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 533 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 534 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 535 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 536 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 537 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 538 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 539 #else 540 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 541 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 542 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 543 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 544 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 545 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 546 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 547 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 548 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 549 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 550 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 551 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 552 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 553 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 554 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 555 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 556 #endif 557 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 558 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 559 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 560 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 561 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 562 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 563 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 564 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 565 566 /* CPLD on IFC */ 567 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 568 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 569 #define CONFIG_SYS_CSPR3_EXT (0xf) 570 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 571 | CSPR_PORT_SIZE_8 \ 572 | CSPR_MSEL_GPCM \ 573 | CSPR_V) 574 575 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 576 #define CONFIG_SYS_CSOR3 0x0 577 578 /* CPLD Timing parameters for IFC CS3 */ 579 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 580 FTIM0_GPCM_TEADC(0x0e) | \ 581 FTIM0_GPCM_TEAHC(0x0e)) 582 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 583 FTIM1_GPCM_TRAD(0x1f)) 584 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 585 FTIM2_GPCM_TCH(0x8) | \ 586 FTIM2_GPCM_TWP(0x1f)) 587 #define CONFIG_SYS_CS3_FTIM3 0x0 588 589 #if defined(CONFIG_RAMBOOT_PBL) 590 #define CONFIG_SYS_RAMBOOT 591 #endif 592 593 594 /* I2C */ 595 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 596 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 597 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 598 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 599 600 #define I2C_MUX_CH_DEFAULT 0x8 601 #define I2C_MUX_CH_VOL_MONITOR 0xa 602 #define I2C_MUX_CH_VSC3316_FS 0xc 603 #define I2C_MUX_CH_VSC3316_BS 0xd 604 605 /* Voltage monitor on channel 2*/ 606 #define I2C_VOL_MONITOR_ADDR 0x40 607 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 608 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 609 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 610 611 /* 612 * eSPI - Enhanced SPI 613 */ 614 #define CONFIG_FSL_ESPI 615 #define CONFIG_SPI_FLASH_SST 616 #define CONFIG_CMD_SF 617 #define CONFIG_SF_DEFAULT_SPEED 10000000 618 #define CONFIG_SF_DEFAULT_MODE 0 619 620 621 /* Qman/Bman */ 622 #ifndef CONFIG_NOBQFMAN 623 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 624 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 625 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 626 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 627 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 628 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 629 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 630 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 631 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 632 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 633 CONFIG_SYS_BMAN_CENA_SIZE) 634 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 635 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 636 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 637 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 638 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 639 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 640 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 641 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 642 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 643 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 644 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 645 CONFIG_SYS_QMAN_CENA_SIZE) 646 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 647 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 648 649 #define CONFIG_SYS_DPAA_FMAN 650 #define CONFIG_SYS_DPAA_PME 651 #define CONFIG_SYS_PMAN 652 #define CONFIG_SYS_DPAA_DCE 653 #define CONFIG_SYS_DPAA_RMAN 654 #define CONFIG_SYS_INTERLAKEN 655 656 /* Default address of microcode for the Linux Fman driver */ 657 #if defined(CONFIG_SPIFLASH) 658 /* 659 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 660 * env, so we got 0x110000. 661 */ 662 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 663 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 664 #elif defined(CONFIG_SDCARD) 665 /* 666 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 667 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 668 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 669 */ 670 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 671 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 672 #elif defined(CONFIG_NAND) 673 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 674 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 675 #else 676 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 677 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 678 #endif 679 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 680 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 681 #endif /* CONFIG_NOBQFMAN */ 682 683 #ifdef CONFIG_SYS_DPAA_FMAN 684 #define CONFIG_FMAN_ENET 685 #define CONFIG_PHYLIB_10G 686 #define CONFIG_PHY_VITESSE 687 #define CONFIG_PHY_CORTINA 688 #define CONFIG_SYS_CORTINA_FW_IN_NOR 689 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 690 #define CONFIG_CORTINA_FW_LENGTH 0x40000 691 #define CONFIG_PHY_TERANETICS 692 #define SGMII_PHY_ADDR1 0x0 693 #define SGMII_PHY_ADDR2 0x1 694 #define SGMII_PHY_ADDR3 0x2 695 #define SGMII_PHY_ADDR4 0x3 696 #define SGMII_PHY_ADDR5 0x4 697 #define SGMII_PHY_ADDR6 0x5 698 #define SGMII_PHY_ADDR7 0x6 699 #define SGMII_PHY_ADDR8 0x7 700 #define FM1_10GEC1_PHY_ADDR 0x10 701 #define FM1_10GEC2_PHY_ADDR 0x11 702 #define FM2_10GEC1_PHY_ADDR 0x12 703 #define FM2_10GEC2_PHY_ADDR 0x13 704 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 705 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 706 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 707 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 708 #endif 709 710 711 /* SATA */ 712 #ifdef CONFIG_FSL_SATA_V2 713 #define CONFIG_LIBATA 714 #define CONFIG_FSL_SATA 715 716 #define CONFIG_SYS_SATA_MAX_DEVICE 2 717 #define CONFIG_SATA1 718 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 719 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 720 #define CONFIG_SATA2 721 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 722 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 723 724 #define CONFIG_LBA48 725 #define CONFIG_CMD_SATA 726 #define CONFIG_DOS_PARTITION 727 #define CONFIG_CMD_EXT2 728 #endif 729 730 #ifdef CONFIG_FMAN_ENET 731 #define CONFIG_MII /* MII PHY management */ 732 #define CONFIG_ETHPRIME "FM1@DTSEC1" 733 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 734 #endif 735 736 /* 737 * USB 738 */ 739 #define CONFIG_CMD_USB 740 #define CONFIG_USB_STORAGE 741 #define CONFIG_USB_EHCI 742 #define CONFIG_USB_EHCI_FSL 743 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 744 #define CONFIG_CMD_EXT2 745 #define CONFIG_HAS_FSL_DR_USB 746 747 #define CONFIG_MMC 748 749 #ifdef CONFIG_MMC 750 #define CONFIG_FSL_ESDHC 751 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 752 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 753 #define CONFIG_CMD_MMC 754 #define CONFIG_GENERIC_MMC 755 #define CONFIG_CMD_EXT2 756 #define CONFIG_CMD_FAT 757 #define CONFIG_DOS_PARTITION 758 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 759 #endif 760 761 /* Hash command with SHA acceleration supported in hardware */ 762 #ifdef CONFIG_FSL_CAAM 763 #define CONFIG_CMD_HASH 764 #define CONFIG_SHA_HW_ACCEL 765 #endif 766 767 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 768 769 #define __USB_PHY_TYPE utmi 770 771 /* 772 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 773 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 774 * interleaving. It can be cacheline, page, bank, superbank. 775 * See doc/README.fsl-ddr for details. 776 */ 777 #ifdef CONFIG_PPC_T4240 778 #define CTRL_INTLV_PREFERED 3way_4KB 779 #else 780 #define CTRL_INTLV_PREFERED cacheline 781 #endif 782 783 #define CONFIG_EXTRA_ENV_SETTINGS \ 784 "hwconfig=fsl_ddr:" \ 785 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 786 "bank_intlv=auto;" \ 787 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 788 "netdev=eth0\0" \ 789 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 790 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 791 "tftpflash=tftpboot $loadaddr $uboot && " \ 792 "protect off $ubootaddr +$filesize && " \ 793 "erase $ubootaddr +$filesize && " \ 794 "cp.b $loadaddr $ubootaddr $filesize && " \ 795 "protect on $ubootaddr +$filesize && " \ 796 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 797 "consoledev=ttyS0\0" \ 798 "ramdiskaddr=2000000\0" \ 799 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 800 "fdtaddr=c00000\0" \ 801 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 802 "bdev=sda3\0" 803 804 #define CONFIG_HVBOOT \ 805 "setenv bootargs config-addr=0x60000000; " \ 806 "bootm 0x01000000 - 0x00f00000" 807 808 #define CONFIG_LINUX \ 809 "setenv bootargs root=/dev/ram rw " \ 810 "console=$consoledev,$baudrate $othbootargs;" \ 811 "setenv ramdiskaddr 0x02000000;" \ 812 "setenv fdtaddr 0x00c00000;" \ 813 "setenv loadaddr 0x1000000;" \ 814 "bootm $loadaddr $ramdiskaddr $fdtaddr" 815 816 #define CONFIG_HDBOOT \ 817 "setenv bootargs root=/dev/$bdev rw " \ 818 "console=$consoledev,$baudrate $othbootargs;" \ 819 "tftp $loadaddr $bootfile;" \ 820 "tftp $fdtaddr $fdtfile;" \ 821 "bootm $loadaddr - $fdtaddr" 822 823 #define CONFIG_NFSBOOTCOMMAND \ 824 "setenv bootargs root=/dev/nfs rw " \ 825 "nfsroot=$serverip:$rootpath " \ 826 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 827 "console=$consoledev,$baudrate $othbootargs;" \ 828 "tftp $loadaddr $bootfile;" \ 829 "tftp $fdtaddr $fdtfile;" \ 830 "bootm $loadaddr - $fdtaddr" 831 832 #define CONFIG_RAMBOOTCOMMAND \ 833 "setenv bootargs root=/dev/ram rw " \ 834 "console=$consoledev,$baudrate $othbootargs;" \ 835 "tftp $ramdiskaddr $ramdiskfile;" \ 836 "tftp $loadaddr $bootfile;" \ 837 "tftp $fdtaddr $fdtfile;" \ 838 "bootm $loadaddr $ramdiskaddr $fdtaddr" 839 840 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 841 842 #include <asm/fsl_secure_boot.h> 843 844 #ifdef CONFIG_SECURE_BOOT 845 /* Secure Boot target was not getting build for T4240 because of 846 * increased binary size. So the size is being reduced by removing USB 847 * which is anyways not used in Secure Environment. 848 */ 849 #undef CONFIG_CMD_USB 850 #define CONFIG_CMD_BLOB 851 #endif 852 853 #endif /* __CONFIG_H */ 854