1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240RDB 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_FSL_SATA_V2 17 #define CONFIG_PCIE4 18 19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 23 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg 24 #ifndef CONFIG_SDCARD 25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #else 28 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 29 #define CONFIG_SPL_ENV_SUPPORT 30 #define CONFIG_SPL_SERIAL_SUPPORT 31 #define CONFIG_SPL_FLUSH_IMAGE 32 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 33 #define CONFIG_SPL_LIBGENERIC_SUPPORT 34 #define CONFIG_SPL_LIBCOMMON_SUPPORT 35 #define CONFIG_SPL_I2C_SUPPORT 36 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 37 #define CONFIG_FSL_LAW /* Use common FSL init code */ 38 #define CONFIG_SYS_TEXT_BASE 0x00201000 39 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 40 #define CONFIG_SPL_PAD_TO 0x40000 41 #define CONFIG_SPL_MAX_SIZE 0x28000 42 #define RESET_VECTOR_OFFSET 0x27FFC 43 #define BOOT_PAGE_OFFSET 0x27000 44 45 #ifdef CONFIG_SDCARD 46 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 47 #define CONFIG_SPL_MMC_SUPPORT 48 #define CONFIG_SPL_MMC_MINIMAL 49 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 50 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 51 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 52 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 53 #ifndef CONFIG_SPL_BUILD 54 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 55 #endif 56 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 57 #define CONFIG_SPL_MMC_BOOT 58 #endif 59 60 #ifdef CONFIG_SPL_BUILD 61 #define CONFIG_SPL_SKIP_RELOCATE 62 #define CONFIG_SPL_COMMON_INIT_DDR 63 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 64 #define CONFIG_SYS_NO_FLASH 65 #endif 66 67 #endif 68 #endif /* CONFIG_RAMBOOT_PBL */ 69 70 #define CONFIG_DDR_ECC 71 72 #define CONFIG_CMD_REGINFO 73 74 /* High Level Configuration Options */ 75 #define CONFIG_BOOKE 76 #define CONFIG_E500 /* BOOKE e500 family */ 77 #define CONFIG_E500MC /* BOOKE e500mc family */ 78 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 79 #define CONFIG_MP /* support multiple processors */ 80 81 #ifndef CONFIG_SYS_TEXT_BASE 82 #define CONFIG_SYS_TEXT_BASE 0xeff40000 83 #endif 84 85 #ifndef CONFIG_RESET_VECTOR_ADDRESS 86 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 87 #endif 88 89 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 90 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 91 #define CONFIG_FSL_IFC /* Enable IFC Support */ 92 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 93 #define CONFIG_PCI /* Enable PCI/PCIE */ 94 #define CONFIG_PCIE1 /* PCIE controller 1 */ 95 #define CONFIG_PCIE2 /* PCIE controller 2 */ 96 #define CONFIG_PCIE3 /* PCIE controller 3 */ 97 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 98 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 99 100 #define CONFIG_FSL_LAW /* Use common FSL init code */ 101 102 #define CONFIG_ENV_OVERWRITE 103 104 /* 105 * These can be toggled for performance analysis, otherwise use default. 106 */ 107 #define CONFIG_SYS_CACHE_STASHING 108 #define CONFIG_BTB /* toggle branch predition */ 109 #ifdef CONFIG_DDR_ECC 110 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 111 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 112 #endif 113 114 #define CONFIG_ENABLE_36BIT_PHYS 115 116 #define CONFIG_ADDR_MAP 117 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 118 119 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 120 #define CONFIG_SYS_MEMTEST_END 0x00400000 121 #define CONFIG_SYS_ALT_MEMTEST 122 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 123 124 /* 125 * Config the L3 Cache as L3 SRAM 126 */ 127 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 128 #define CONFIG_SYS_L3_SIZE (512 << 10) 129 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 130 #ifdef CONFIG_RAMBOOT_PBL 131 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 132 #endif 133 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 134 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 135 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 136 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 137 138 #define CONFIG_SYS_DCSRBAR 0xf0000000 139 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 140 141 /* 142 * DDR Setup 143 */ 144 #define CONFIG_VERY_BIG_RAM 145 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 146 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 147 148 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 149 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 150 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 151 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 152 153 #define CONFIG_DDR_SPD 154 #define CONFIG_SYS_FSL_DDR3 155 156 /* 157 * IFC Definitions 158 */ 159 #define CONFIG_SYS_FLASH_BASE 0xe0000000 160 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 161 162 #ifdef CONFIG_SPL_BUILD 163 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 164 #else 165 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 166 #endif 167 168 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 169 #define CONFIG_MISC_INIT_R 170 171 #define CONFIG_HWCONFIG 172 173 /* define to use L1 as initial stack */ 174 #define CONFIG_L1_INIT_RAM 175 #define CONFIG_SYS_INIT_RAM_LOCK 176 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 177 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 178 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 179 /* The assembler doesn't like typecast */ 180 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 181 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 182 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 183 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 184 185 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 186 GENERATED_GBL_DATA_SIZE) 187 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 188 189 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 190 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 191 192 /* Serial Port - controlled on board with jumper J8 193 * open - index 2 194 * shorted - index 1 195 */ 196 #define CONFIG_CONS_INDEX 1 197 #define CONFIG_SYS_NS16550_SERIAL 198 #define CONFIG_SYS_NS16550_REG_SIZE 1 199 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 200 201 #define CONFIG_SYS_BAUDRATE_TABLE \ 202 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 203 204 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 205 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 206 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 207 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 208 209 /* I2C */ 210 #define CONFIG_SYS_I2C 211 #define CONFIG_SYS_I2C_FSL 212 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 213 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 214 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 215 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 216 217 /* 218 * General PCI 219 * Memory space is mapped 1-1, but I/O space must start from 0. 220 */ 221 222 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 223 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 224 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 225 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 226 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 227 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 228 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 229 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 230 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 231 232 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 233 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 234 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 235 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 236 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 237 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 238 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 239 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 240 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 241 242 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 243 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 244 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 245 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 246 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 247 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 248 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 249 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 250 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 251 252 /* controller 4, Base address 203000 */ 253 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 254 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 255 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 256 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 257 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 258 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 259 260 #ifdef CONFIG_PCI 261 #define CONFIG_PCI_INDIRECT_BRIDGE 262 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 263 264 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 265 #define CONFIG_DOS_PARTITION 266 #endif /* CONFIG_PCI */ 267 268 /* SATA */ 269 #ifdef CONFIG_FSL_SATA_V2 270 #define CONFIG_LIBATA 271 #define CONFIG_FSL_SATA 272 273 #define CONFIG_SYS_SATA_MAX_DEVICE 2 274 #define CONFIG_SATA1 275 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 276 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 277 #define CONFIG_SATA2 278 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 279 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 280 281 #define CONFIG_LBA48 282 #define CONFIG_CMD_SATA 283 #define CONFIG_DOS_PARTITION 284 #endif 285 286 #ifdef CONFIG_FMAN_ENET 287 #define CONFIG_MII /* MII PHY management */ 288 #define CONFIG_ETHPRIME "FM1@DTSEC1" 289 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 290 #endif 291 292 /* 293 * Environment 294 */ 295 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 296 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 297 298 /* 299 * Command line configuration. 300 */ 301 #define CONFIG_CMD_ERRATA 302 #define CONFIG_CMD_IRQ 303 304 #ifdef CONFIG_PCI 305 #define CONFIG_CMD_PCI 306 #endif 307 308 /* 309 * Miscellaneous configurable options 310 */ 311 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 312 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 313 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 314 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 315 #ifdef CONFIG_CMD_KGDB 316 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 317 #else 318 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 319 #endif 320 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 321 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 322 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 323 324 /* 325 * For booting Linux, the board info and command line data 326 * have to be in the first 64 MB of memory, since this is 327 * the maximum mapped by the Linux kernel during initialization. 328 */ 329 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 330 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 331 332 #ifdef CONFIG_CMD_KGDB 333 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 334 #endif 335 336 /* 337 * Environment Configuration 338 */ 339 #define CONFIG_ROOTPATH "/opt/nfsroot" 340 #define CONFIG_BOOTFILE "uImage" 341 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 342 343 /* default location for tftp and bootm */ 344 #define CONFIG_LOADADDR 1000000 345 346 #define CONFIG_BAUDRATE 115200 347 348 #define CONFIG_HVBOOT \ 349 "setenv bootargs config-addr=0x60000000; " \ 350 "bootm 0x01000000 - 0x00f00000" 351 352 #ifdef CONFIG_SYS_NO_FLASH 353 #ifndef CONFIG_RAMBOOT_PBL 354 #define CONFIG_ENV_IS_NOWHERE 355 #endif 356 #else 357 #define CONFIG_FLASH_CFI_DRIVER 358 #define CONFIG_SYS_FLASH_CFI 359 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 360 #endif 361 362 #if defined(CONFIG_SPIFLASH) 363 #define CONFIG_SYS_EXTRA_ENV_RELOC 364 #define CONFIG_ENV_IS_IN_SPI_FLASH 365 #define CONFIG_ENV_SPI_BUS 0 366 #define CONFIG_ENV_SPI_CS 0 367 #define CONFIG_ENV_SPI_MAX_HZ 10000000 368 #define CONFIG_ENV_SPI_MODE 0 369 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 370 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 371 #define CONFIG_ENV_SECT_SIZE 0x10000 372 #elif defined(CONFIG_SDCARD) 373 #define CONFIG_SYS_EXTRA_ENV_RELOC 374 #define CONFIG_ENV_IS_IN_MMC 375 #define CONFIG_SYS_MMC_ENV_DEV 0 376 #define CONFIG_ENV_SIZE 0x2000 377 #define CONFIG_ENV_OFFSET (512 * 0x800) 378 #elif defined(CONFIG_NAND) 379 #define CONFIG_SYS_EXTRA_ENV_RELOC 380 #define CONFIG_ENV_IS_IN_NAND 381 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 382 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 383 #elif defined(CONFIG_ENV_IS_NOWHERE) 384 #define CONFIG_ENV_SIZE 0x2000 385 #else 386 #define CONFIG_ENV_IS_IN_FLASH 387 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 388 #define CONFIG_ENV_SIZE 0x2000 389 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 390 #endif 391 392 #define CONFIG_SYS_CLK_FREQ 66666666 393 #define CONFIG_DDR_CLK_FREQ 133333333 394 395 #ifndef __ASSEMBLY__ 396 unsigned long get_board_sys_clk(void); 397 unsigned long get_board_ddr_clk(void); 398 #endif 399 400 /* 401 * DDR Setup 402 */ 403 #define CONFIG_SYS_SPD_BUS_NUM 0 404 #define SPD_EEPROM_ADDRESS1 0x52 405 #define SPD_EEPROM_ADDRESS2 0x54 406 #define SPD_EEPROM_ADDRESS3 0x56 407 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 408 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 409 410 /* 411 * IFC Definitions 412 */ 413 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 414 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 415 + 0x8000000) | \ 416 CSPR_PORT_SIZE_16 | \ 417 CSPR_MSEL_NOR | \ 418 CSPR_V) 419 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 420 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 421 CSPR_PORT_SIZE_16 | \ 422 CSPR_MSEL_NOR | \ 423 CSPR_V) 424 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 425 /* NOR Flash Timing Params */ 426 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 427 428 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 429 FTIM0_NOR_TEADC(0x5) | \ 430 FTIM0_NOR_TEAHC(0x5)) 431 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 432 FTIM1_NOR_TRAD_NOR(0x1A) |\ 433 FTIM1_NOR_TSEQRAD_NOR(0x13)) 434 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 435 FTIM2_NOR_TCH(0x4) | \ 436 FTIM2_NOR_TWPH(0x0E) | \ 437 FTIM2_NOR_TWP(0x1c)) 438 #define CONFIG_SYS_NOR_FTIM3 0x0 439 440 #define CONFIG_SYS_FLASH_QUIET_TEST 441 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 442 443 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 444 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 445 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 446 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 447 448 #define CONFIG_SYS_FLASH_EMPTY_INFO 449 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 450 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 451 452 /* NAND Flash on IFC */ 453 #define CONFIG_NAND_FSL_IFC 454 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 455 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 456 #define CONFIG_SYS_NAND_BASE 0xff800000 457 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 458 459 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 460 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 461 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 462 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 463 | CSPR_V) 464 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 465 466 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 467 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 468 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 469 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 470 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 471 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 472 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 473 474 #define CONFIG_SYS_NAND_ONFI_DETECTION 475 476 /* ONFI NAND Flash mode0 Timing Params */ 477 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 478 FTIM0_NAND_TWP(0x18) | \ 479 FTIM0_NAND_TWCHT(0x07) | \ 480 FTIM0_NAND_TWH(0x0a)) 481 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 482 FTIM1_NAND_TWBE(0x39) | \ 483 FTIM1_NAND_TRR(0x0e) | \ 484 FTIM1_NAND_TRP(0x18)) 485 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 486 FTIM2_NAND_TREH(0x0a) | \ 487 FTIM2_NAND_TWHRE(0x1e)) 488 #define CONFIG_SYS_NAND_FTIM3 0x0 489 490 #define CONFIG_SYS_NAND_DDR_LAW 11 491 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 492 #define CONFIG_SYS_MAX_NAND_DEVICE 1 493 #define CONFIG_CMD_NAND 494 495 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 496 497 #if defined(CONFIG_NAND) 498 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 499 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 500 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 501 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 502 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 503 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 504 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 505 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 506 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 507 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 508 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 509 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 510 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 511 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 512 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 513 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 514 #else 515 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 516 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 517 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 518 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 519 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 520 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 521 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 522 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 523 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 524 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 525 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 526 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 527 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 528 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 529 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 530 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 531 #endif 532 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 533 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 534 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 535 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 536 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 537 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 538 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 539 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 540 541 /* CPLD on IFC */ 542 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 543 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 544 #define CONFIG_SYS_CSPR3_EXT (0xf) 545 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 546 | CSPR_PORT_SIZE_8 \ 547 | CSPR_MSEL_GPCM \ 548 | CSPR_V) 549 550 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 551 #define CONFIG_SYS_CSOR3 0x0 552 553 /* CPLD Timing parameters for IFC CS3 */ 554 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 555 FTIM0_GPCM_TEADC(0x0e) | \ 556 FTIM0_GPCM_TEAHC(0x0e)) 557 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 558 FTIM1_GPCM_TRAD(0x1f)) 559 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 560 FTIM2_GPCM_TCH(0x8) | \ 561 FTIM2_GPCM_TWP(0x1f)) 562 #define CONFIG_SYS_CS3_FTIM3 0x0 563 564 #if defined(CONFIG_RAMBOOT_PBL) 565 #define CONFIG_SYS_RAMBOOT 566 #endif 567 568 /* I2C */ 569 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 570 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 571 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 572 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 573 574 #define I2C_MUX_CH_DEFAULT 0x8 575 #define I2C_MUX_CH_VOL_MONITOR 0xa 576 #define I2C_MUX_CH_VSC3316_FS 0xc 577 #define I2C_MUX_CH_VSC3316_BS 0xd 578 579 /* Voltage monitor on channel 2*/ 580 #define I2C_VOL_MONITOR_ADDR 0x40 581 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 582 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 583 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 584 585 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 586 #ifndef CONFIG_SPL_BUILD 587 #define CONFIG_VID 588 #endif 589 #define CONFIG_VOL_MONITOR_IR36021_SET 590 #define CONFIG_VOL_MONITOR_IR36021_READ 591 /* The lowest and highest voltage allowed for T4240RDB */ 592 #define VDD_MV_MIN 819 593 #define VDD_MV_MAX 1212 594 595 /* 596 * eSPI - Enhanced SPI 597 */ 598 #define CONFIG_SF_DEFAULT_SPEED 10000000 599 #define CONFIG_SF_DEFAULT_MODE 0 600 601 /* Qman/Bman */ 602 #ifndef CONFIG_NOBQFMAN 603 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 604 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 605 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 606 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 607 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 608 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 609 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 610 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 611 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 612 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 613 CONFIG_SYS_BMAN_CENA_SIZE) 614 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 615 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 616 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 617 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 618 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 619 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 620 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 621 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 622 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 623 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 624 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 625 CONFIG_SYS_QMAN_CENA_SIZE) 626 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 627 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 628 629 #define CONFIG_SYS_DPAA_FMAN 630 #define CONFIG_SYS_DPAA_PME 631 #define CONFIG_SYS_PMAN 632 #define CONFIG_SYS_DPAA_DCE 633 #define CONFIG_SYS_DPAA_RMAN 634 #define CONFIG_SYS_INTERLAKEN 635 636 /* Default address of microcode for the Linux Fman driver */ 637 #if defined(CONFIG_SPIFLASH) 638 /* 639 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 640 * env, so we got 0x110000. 641 */ 642 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 643 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 644 #elif defined(CONFIG_SDCARD) 645 /* 646 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 647 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 648 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 649 */ 650 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 651 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 652 #elif defined(CONFIG_NAND) 653 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 654 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 655 #else 656 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 657 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 658 #endif 659 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 660 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 661 #endif /* CONFIG_NOBQFMAN */ 662 663 #ifdef CONFIG_SYS_DPAA_FMAN 664 #define CONFIG_FMAN_ENET 665 #define CONFIG_PHYLIB_10G 666 #define CONFIG_PHY_VITESSE 667 #define CONFIG_PHY_CORTINA 668 #define CONFIG_SYS_CORTINA_FW_IN_NOR 669 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 670 #define CONFIG_CORTINA_FW_LENGTH 0x40000 671 #define CONFIG_PHY_TERANETICS 672 #define SGMII_PHY_ADDR1 0x0 673 #define SGMII_PHY_ADDR2 0x1 674 #define SGMII_PHY_ADDR3 0x2 675 #define SGMII_PHY_ADDR4 0x3 676 #define SGMII_PHY_ADDR5 0x4 677 #define SGMII_PHY_ADDR6 0x5 678 #define SGMII_PHY_ADDR7 0x6 679 #define SGMII_PHY_ADDR8 0x7 680 #define FM1_10GEC1_PHY_ADDR 0x10 681 #define FM1_10GEC2_PHY_ADDR 0x11 682 #define FM2_10GEC1_PHY_ADDR 0x12 683 #define FM2_10GEC2_PHY_ADDR 0x13 684 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 685 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 686 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 687 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 688 #endif 689 690 /* SATA */ 691 #ifdef CONFIG_FSL_SATA_V2 692 #define CONFIG_LIBATA 693 #define CONFIG_FSL_SATA 694 695 #define CONFIG_SYS_SATA_MAX_DEVICE 2 696 #define CONFIG_SATA1 697 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 698 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 699 #define CONFIG_SATA2 700 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 701 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 702 703 #define CONFIG_LBA48 704 #define CONFIG_CMD_SATA 705 #define CONFIG_DOS_PARTITION 706 #endif 707 708 #ifdef CONFIG_FMAN_ENET 709 #define CONFIG_MII /* MII PHY management */ 710 #define CONFIG_ETHPRIME "FM1@DTSEC1" 711 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 712 #endif 713 714 /* 715 * USB 716 */ 717 #define CONFIG_USB_STORAGE 718 #define CONFIG_USB_EHCI 719 #define CONFIG_USB_EHCI_FSL 720 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 721 #define CONFIG_HAS_FSL_DR_USB 722 723 #define CONFIG_MMC 724 725 #ifdef CONFIG_MMC 726 #define CONFIG_FSL_ESDHC 727 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 728 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 729 #define CONFIG_GENERIC_MMC 730 #define CONFIG_DOS_PARTITION 731 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 732 #endif 733 734 /* Hash command with SHA acceleration supported in hardware */ 735 #ifdef CONFIG_FSL_CAAM 736 #define CONFIG_CMD_HASH 737 #define CONFIG_SHA_HW_ACCEL 738 #endif 739 740 741 #define __USB_PHY_TYPE utmi 742 743 /* 744 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 745 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 746 * interleaving. It can be cacheline, page, bank, superbank. 747 * See doc/README.fsl-ddr for details. 748 */ 749 #ifdef CONFIG_PPC_T4240 750 #define CTRL_INTLV_PREFERED 3way_4KB 751 #else 752 #define CTRL_INTLV_PREFERED cacheline 753 #endif 754 755 #define CONFIG_EXTRA_ENV_SETTINGS \ 756 "hwconfig=fsl_ddr:" \ 757 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 758 "bank_intlv=auto;" \ 759 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 760 "netdev=eth0\0" \ 761 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 762 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 763 "tftpflash=tftpboot $loadaddr $uboot && " \ 764 "protect off $ubootaddr +$filesize && " \ 765 "erase $ubootaddr +$filesize && " \ 766 "cp.b $loadaddr $ubootaddr $filesize && " \ 767 "protect on $ubootaddr +$filesize && " \ 768 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 769 "consoledev=ttyS0\0" \ 770 "ramdiskaddr=2000000\0" \ 771 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 772 "fdtaddr=1e00000\0" \ 773 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 774 "bdev=sda3\0" 775 776 #define CONFIG_HVBOOT \ 777 "setenv bootargs config-addr=0x60000000; " \ 778 "bootm 0x01000000 - 0x00f00000" 779 780 #define CONFIG_LINUX \ 781 "setenv bootargs root=/dev/ram rw " \ 782 "console=$consoledev,$baudrate $othbootargs;" \ 783 "setenv ramdiskaddr 0x02000000;" \ 784 "setenv fdtaddr 0x00c00000;" \ 785 "setenv loadaddr 0x1000000;" \ 786 "bootm $loadaddr $ramdiskaddr $fdtaddr" 787 788 #define CONFIG_HDBOOT \ 789 "setenv bootargs root=/dev/$bdev rw " \ 790 "console=$consoledev,$baudrate $othbootargs;" \ 791 "tftp $loadaddr $bootfile;" \ 792 "tftp $fdtaddr $fdtfile;" \ 793 "bootm $loadaddr - $fdtaddr" 794 795 #define CONFIG_NFSBOOTCOMMAND \ 796 "setenv bootargs root=/dev/nfs rw " \ 797 "nfsroot=$serverip:$rootpath " \ 798 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 799 "console=$consoledev,$baudrate $othbootargs;" \ 800 "tftp $loadaddr $bootfile;" \ 801 "tftp $fdtaddr $fdtfile;" \ 802 "bootm $loadaddr - $fdtaddr" 803 804 #define CONFIG_RAMBOOTCOMMAND \ 805 "setenv bootargs root=/dev/ram rw " \ 806 "console=$consoledev,$baudrate $othbootargs;" \ 807 "tftp $ramdiskaddr $ramdiskfile;" \ 808 "tftp $loadaddr $bootfile;" \ 809 "tftp $fdtaddr $fdtfile;" \ 810 "bootm $loadaddr $ramdiskaddr $fdtaddr" 811 812 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 813 814 #include <asm/fsl_secure_boot.h> 815 816 #endif /* __CONFIG_H */ 817