1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_FSL_SATA_V2 14 #define CONFIG_PCIE4 15 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 20 #ifndef CONFIG_SDCARD 21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 23 #else 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 27 #define CONFIG_SPL_PAD_TO 0x40000 28 #define CONFIG_SPL_MAX_SIZE 0x28000 29 #define RESET_VECTOR_OFFSET 0x27FFC 30 #define BOOT_PAGE_OFFSET 0x27000 31 32 #ifdef CONFIG_SDCARD 33 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 34 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 35 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 36 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 37 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 38 #ifndef CONFIG_SPL_BUILD 39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 40 #endif 41 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 42 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg 43 #define CONFIG_SPL_MMC_BOOT 44 #endif 45 46 #ifdef CONFIG_SPL_BUILD 47 #define CONFIG_SPL_SKIP_RELOCATE 48 #define CONFIG_SPL_COMMON_INIT_DDR 49 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 50 #endif 51 52 #endif 53 #endif /* CONFIG_RAMBOOT_PBL */ 54 55 #define CONFIG_DDR_ECC 56 57 /* High Level Configuration Options */ 58 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 59 #define CONFIG_MP /* support multiple processors */ 60 61 #ifndef CONFIG_RESET_VECTOR_ADDRESS 62 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 63 #endif 64 65 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 66 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 67 #define CONFIG_PCIE1 /* PCIE controller 1 */ 68 #define CONFIG_PCIE2 /* PCIE controller 2 */ 69 #define CONFIG_PCIE3 /* PCIE controller 3 */ 70 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 71 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 72 73 #define CONFIG_ENV_OVERWRITE 74 75 /* 76 * These can be toggled for performance analysis, otherwise use default. 77 */ 78 #define CONFIG_SYS_CACHE_STASHING 79 #define CONFIG_BTB /* toggle branch predition */ 80 #ifdef CONFIG_DDR_ECC 81 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 82 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 83 #endif 84 85 #define CONFIG_ENABLE_36BIT_PHYS 86 87 #define CONFIG_ADDR_MAP 88 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 89 90 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 91 #define CONFIG_SYS_MEMTEST_END 0x00400000 92 #define CONFIG_SYS_ALT_MEMTEST 93 94 /* 95 * Config the L3 Cache as L3 SRAM 96 */ 97 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 98 #define CONFIG_SYS_L3_SIZE (512 << 10) 99 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 100 #ifdef CONFIG_RAMBOOT_PBL 101 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 102 #endif 103 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 104 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 105 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 106 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 107 108 #define CONFIG_SYS_DCSRBAR 0xf0000000 109 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 110 111 /* 112 * DDR Setup 113 */ 114 #define CONFIG_VERY_BIG_RAM 115 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 116 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 117 118 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 119 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 120 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 121 122 #define CONFIG_DDR_SPD 123 124 /* 125 * IFC Definitions 126 */ 127 #define CONFIG_SYS_FLASH_BASE 0xe0000000 128 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 129 130 #ifdef CONFIG_SPL_BUILD 131 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 132 #else 133 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 134 #endif 135 136 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 137 #define CONFIG_MISC_INIT_R 138 139 #define CONFIG_HWCONFIG 140 141 /* define to use L1 as initial stack */ 142 #define CONFIG_L1_INIT_RAM 143 #define CONFIG_SYS_INIT_RAM_LOCK 144 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 145 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 146 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 147 /* The assembler doesn't like typecast */ 148 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 149 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 150 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 151 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 152 153 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 154 GENERATED_GBL_DATA_SIZE) 155 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 156 157 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 158 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 159 160 /* Serial Port - controlled on board with jumper J8 161 * open - index 2 162 * shorted - index 1 163 */ 164 #define CONFIG_CONS_INDEX 1 165 #define CONFIG_SYS_NS16550_SERIAL 166 #define CONFIG_SYS_NS16550_REG_SIZE 1 167 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 168 169 #define CONFIG_SYS_BAUDRATE_TABLE \ 170 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 171 172 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 173 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 174 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 175 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 176 177 /* I2C */ 178 #define CONFIG_SYS_I2C 179 #define CONFIG_SYS_I2C_FSL 180 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 181 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 182 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 183 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 184 185 /* 186 * General PCI 187 * Memory space is mapped 1-1, but I/O space must start from 0. 188 */ 189 190 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 191 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 192 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 193 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 194 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 195 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 196 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 197 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 198 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 199 200 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 201 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 202 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 203 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 204 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 205 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 206 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 207 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 208 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 209 210 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 211 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 212 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 213 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 214 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 215 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 216 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 217 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 218 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 219 220 /* controller 4, Base address 203000 */ 221 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 222 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 223 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 224 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 225 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 226 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 227 228 #ifdef CONFIG_PCI 229 #define CONFIG_PCI_INDIRECT_BRIDGE 230 231 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 232 #endif /* CONFIG_PCI */ 233 234 /* SATA */ 235 #ifdef CONFIG_FSL_SATA_V2 236 #define CONFIG_SYS_SATA_MAX_DEVICE 2 237 #define CONFIG_SATA1 238 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 239 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 240 #define CONFIG_SATA2 241 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 242 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 243 244 #define CONFIG_LBA48 245 #endif 246 247 #ifdef CONFIG_FMAN_ENET 248 #define CONFIG_MII /* MII PHY management */ 249 #define CONFIG_ETHPRIME "FM1@DTSEC1" 250 #endif 251 252 /* 253 * Environment 254 */ 255 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 256 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 257 258 /* 259 * Command line configuration. 260 */ 261 262 /* 263 * Miscellaneous configurable options 264 */ 265 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 266 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 267 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 268 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 269 270 /* 271 * For booting Linux, the board info and command line data 272 * have to be in the first 64 MB of memory, since this is 273 * the maximum mapped by the Linux kernel during initialization. 274 */ 275 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 276 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 277 278 #ifdef CONFIG_CMD_KGDB 279 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 280 #endif 281 282 /* 283 * Environment Configuration 284 */ 285 #define CONFIG_ROOTPATH "/opt/nfsroot" 286 #define CONFIG_BOOTFILE "uImage" 287 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 288 289 /* default location for tftp and bootm */ 290 #define CONFIG_LOADADDR 1000000 291 292 #define CONFIG_HVBOOT \ 293 "setenv bootargs config-addr=0x60000000; " \ 294 "bootm 0x01000000 - 0x00f00000" 295 296 #ifndef CONFIG_MTD_NOR_FLASH 297 #else 298 #define CONFIG_FLASH_CFI_DRIVER 299 #define CONFIG_SYS_FLASH_CFI 300 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 301 #endif 302 303 #if defined(CONFIG_SPIFLASH) 304 #define CONFIG_SYS_EXTRA_ENV_RELOC 305 #define CONFIG_ENV_SPI_BUS 0 306 #define CONFIG_ENV_SPI_CS 0 307 #define CONFIG_ENV_SPI_MAX_HZ 10000000 308 #define CONFIG_ENV_SPI_MODE 0 309 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 310 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 311 #define CONFIG_ENV_SECT_SIZE 0x10000 312 #elif defined(CONFIG_SDCARD) 313 #define CONFIG_SYS_EXTRA_ENV_RELOC 314 #define CONFIG_SYS_MMC_ENV_DEV 0 315 #define CONFIG_ENV_SIZE 0x2000 316 #define CONFIG_ENV_OFFSET (512 * 0x800) 317 #elif defined(CONFIG_NAND) 318 #define CONFIG_SYS_EXTRA_ENV_RELOC 319 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 320 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 321 #elif defined(CONFIG_ENV_IS_NOWHERE) 322 #define CONFIG_ENV_SIZE 0x2000 323 #else 324 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 325 #define CONFIG_ENV_SIZE 0x2000 326 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 327 #endif 328 329 #define CONFIG_SYS_CLK_FREQ 66666666 330 #define CONFIG_DDR_CLK_FREQ 133333333 331 332 #ifndef __ASSEMBLY__ 333 unsigned long get_board_sys_clk(void); 334 unsigned long get_board_ddr_clk(void); 335 #endif 336 337 /* 338 * DDR Setup 339 */ 340 #define CONFIG_SYS_SPD_BUS_NUM 0 341 #define SPD_EEPROM_ADDRESS1 0x52 342 #define SPD_EEPROM_ADDRESS2 0x54 343 #define SPD_EEPROM_ADDRESS3 0x56 344 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 345 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 346 347 /* 348 * IFC Definitions 349 */ 350 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 351 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 352 + 0x8000000) | \ 353 CSPR_PORT_SIZE_16 | \ 354 CSPR_MSEL_NOR | \ 355 CSPR_V) 356 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 357 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 358 CSPR_PORT_SIZE_16 | \ 359 CSPR_MSEL_NOR | \ 360 CSPR_V) 361 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 362 /* NOR Flash Timing Params */ 363 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 364 365 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 366 FTIM0_NOR_TEADC(0x5) | \ 367 FTIM0_NOR_TEAHC(0x5)) 368 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 369 FTIM1_NOR_TRAD_NOR(0x1A) |\ 370 FTIM1_NOR_TSEQRAD_NOR(0x13)) 371 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 372 FTIM2_NOR_TCH(0x4) | \ 373 FTIM2_NOR_TWPH(0x0E) | \ 374 FTIM2_NOR_TWP(0x1c)) 375 #define CONFIG_SYS_NOR_FTIM3 0x0 376 377 #define CONFIG_SYS_FLASH_QUIET_TEST 378 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 379 380 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 381 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 382 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 383 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 384 385 #define CONFIG_SYS_FLASH_EMPTY_INFO 386 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 387 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 388 389 /* NAND Flash on IFC */ 390 #define CONFIG_NAND_FSL_IFC 391 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 392 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 393 #define CONFIG_SYS_NAND_BASE 0xff800000 394 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 395 396 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 397 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 398 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 399 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 400 | CSPR_V) 401 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 402 403 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 404 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 405 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 406 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 407 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 408 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 409 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 410 411 #define CONFIG_SYS_NAND_ONFI_DETECTION 412 413 /* ONFI NAND Flash mode0 Timing Params */ 414 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 415 FTIM0_NAND_TWP(0x18) | \ 416 FTIM0_NAND_TWCHT(0x07) | \ 417 FTIM0_NAND_TWH(0x0a)) 418 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 419 FTIM1_NAND_TWBE(0x39) | \ 420 FTIM1_NAND_TRR(0x0e) | \ 421 FTIM1_NAND_TRP(0x18)) 422 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 423 FTIM2_NAND_TREH(0x0a) | \ 424 FTIM2_NAND_TWHRE(0x1e)) 425 #define CONFIG_SYS_NAND_FTIM3 0x0 426 427 #define CONFIG_SYS_NAND_DDR_LAW 11 428 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 429 #define CONFIG_SYS_MAX_NAND_DEVICE 1 430 431 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 432 433 #if defined(CONFIG_NAND) 434 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 435 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 436 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 437 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 438 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 439 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 440 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 441 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 442 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 443 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 444 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 445 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 446 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 447 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 448 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 449 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 450 #else 451 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 452 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 453 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 454 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 455 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 456 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 457 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 458 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 459 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 460 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 461 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 462 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 463 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 464 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 465 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 466 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 467 #endif 468 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 469 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 470 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 471 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 472 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 473 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 474 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 475 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 476 477 /* CPLD on IFC */ 478 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 479 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 480 #define CONFIG_SYS_CSPR3_EXT (0xf) 481 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 482 | CSPR_PORT_SIZE_8 \ 483 | CSPR_MSEL_GPCM \ 484 | CSPR_V) 485 486 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 487 #define CONFIG_SYS_CSOR3 0x0 488 489 /* CPLD Timing parameters for IFC CS3 */ 490 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 491 FTIM0_GPCM_TEADC(0x0e) | \ 492 FTIM0_GPCM_TEAHC(0x0e)) 493 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 494 FTIM1_GPCM_TRAD(0x1f)) 495 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 496 FTIM2_GPCM_TCH(0x8) | \ 497 FTIM2_GPCM_TWP(0x1f)) 498 #define CONFIG_SYS_CS3_FTIM3 0x0 499 500 #if defined(CONFIG_RAMBOOT_PBL) 501 #define CONFIG_SYS_RAMBOOT 502 #endif 503 504 /* I2C */ 505 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 506 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 507 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 508 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 509 510 #define I2C_MUX_CH_DEFAULT 0x8 511 #define I2C_MUX_CH_VOL_MONITOR 0xa 512 #define I2C_MUX_CH_VSC3316_FS 0xc 513 #define I2C_MUX_CH_VSC3316_BS 0xd 514 515 /* Voltage monitor on channel 2*/ 516 #define I2C_VOL_MONITOR_ADDR 0x40 517 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 518 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 519 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 520 521 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 522 #ifndef CONFIG_SPL_BUILD 523 #define CONFIG_VID 524 #endif 525 #define CONFIG_VOL_MONITOR_IR36021_SET 526 #define CONFIG_VOL_MONITOR_IR36021_READ 527 /* The lowest and highest voltage allowed for T4240RDB */ 528 #define VDD_MV_MIN 819 529 #define VDD_MV_MAX 1212 530 531 /* 532 * eSPI - Enhanced SPI 533 */ 534 #define CONFIG_SF_DEFAULT_SPEED 10000000 535 #define CONFIG_SF_DEFAULT_MODE 0 536 537 /* Qman/Bman */ 538 #ifndef CONFIG_NOBQFMAN 539 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 540 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 541 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 542 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 543 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 544 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 545 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 546 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 547 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 548 CONFIG_SYS_BMAN_CENA_SIZE) 549 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 550 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 551 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 552 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 553 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 554 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 555 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 556 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 557 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 558 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 559 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 560 CONFIG_SYS_QMAN_CENA_SIZE) 561 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 562 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 563 564 #define CONFIG_SYS_DPAA_FMAN 565 #define CONFIG_SYS_DPAA_PME 566 #define CONFIG_SYS_PMAN 567 #define CONFIG_SYS_DPAA_DCE 568 #define CONFIG_SYS_DPAA_RMAN 569 #define CONFIG_SYS_INTERLAKEN 570 571 /* Default address of microcode for the Linux Fman driver */ 572 #if defined(CONFIG_SPIFLASH) 573 /* 574 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 575 * env, so we got 0x110000. 576 */ 577 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 578 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 579 #elif defined(CONFIG_SDCARD) 580 /* 581 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 582 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 583 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 584 */ 585 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 586 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 587 #elif defined(CONFIG_NAND) 588 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 589 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 590 #else 591 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 592 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 593 #endif 594 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 595 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 596 #endif /* CONFIG_NOBQFMAN */ 597 598 #ifdef CONFIG_SYS_DPAA_FMAN 599 #define CONFIG_FMAN_ENET 600 #define CONFIG_PHYLIB_10G 601 #define CONFIG_PHY_VITESSE 602 #define CONFIG_PHY_CORTINA 603 #define CONFIG_SYS_CORTINA_FW_IN_NOR 604 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 605 #define CONFIG_CORTINA_FW_LENGTH 0x40000 606 #define CONFIG_PHY_TERANETICS 607 #define SGMII_PHY_ADDR1 0x0 608 #define SGMII_PHY_ADDR2 0x1 609 #define SGMII_PHY_ADDR3 0x2 610 #define SGMII_PHY_ADDR4 0x3 611 #define SGMII_PHY_ADDR5 0x4 612 #define SGMII_PHY_ADDR6 0x5 613 #define SGMII_PHY_ADDR7 0x6 614 #define SGMII_PHY_ADDR8 0x7 615 #define FM1_10GEC1_PHY_ADDR 0x10 616 #define FM1_10GEC2_PHY_ADDR 0x11 617 #define FM2_10GEC1_PHY_ADDR 0x12 618 #define FM2_10GEC2_PHY_ADDR 0x13 619 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 620 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 621 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 622 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 623 #endif 624 625 /* SATA */ 626 #ifdef CONFIG_FSL_SATA_V2 627 #define CONFIG_SYS_SATA_MAX_DEVICE 2 628 #define CONFIG_SATA1 629 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 630 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 631 #define CONFIG_SATA2 632 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 633 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 634 635 #define CONFIG_LBA48 636 #endif 637 638 #ifdef CONFIG_FMAN_ENET 639 #define CONFIG_MII /* MII PHY management */ 640 #define CONFIG_ETHPRIME "FM1@DTSEC1" 641 #endif 642 643 /* 644 * USB 645 */ 646 #define CONFIG_USB_EHCI_FSL 647 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 648 #define CONFIG_HAS_FSL_DR_USB 649 650 #ifdef CONFIG_MMC 651 #define CONFIG_FSL_ESDHC 652 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 653 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 654 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 655 #endif 656 657 658 #define __USB_PHY_TYPE utmi 659 660 /* 661 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 662 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 663 * interleaving. It can be cacheline, page, bank, superbank. 664 * See doc/README.fsl-ddr for details. 665 */ 666 #ifdef CONFIG_ARCH_T4240 667 #define CTRL_INTLV_PREFERED 3way_4KB 668 #else 669 #define CTRL_INTLV_PREFERED cacheline 670 #endif 671 672 #define CONFIG_EXTRA_ENV_SETTINGS \ 673 "hwconfig=fsl_ddr:" \ 674 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 675 "bank_intlv=auto;" \ 676 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 677 "netdev=eth0\0" \ 678 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 679 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 680 "tftpflash=tftpboot $loadaddr $uboot && " \ 681 "protect off $ubootaddr +$filesize && " \ 682 "erase $ubootaddr +$filesize && " \ 683 "cp.b $loadaddr $ubootaddr $filesize && " \ 684 "protect on $ubootaddr +$filesize && " \ 685 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 686 "consoledev=ttyS0\0" \ 687 "ramdiskaddr=2000000\0" \ 688 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 689 "fdtaddr=1e00000\0" \ 690 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 691 "bdev=sda3\0" 692 693 #define CONFIG_HVBOOT \ 694 "setenv bootargs config-addr=0x60000000; " \ 695 "bootm 0x01000000 - 0x00f00000" 696 697 #define CONFIG_LINUX \ 698 "setenv bootargs root=/dev/ram rw " \ 699 "console=$consoledev,$baudrate $othbootargs;" \ 700 "setenv ramdiskaddr 0x02000000;" \ 701 "setenv fdtaddr 0x00c00000;" \ 702 "setenv loadaddr 0x1000000;" \ 703 "bootm $loadaddr $ramdiskaddr $fdtaddr" 704 705 #define CONFIG_HDBOOT \ 706 "setenv bootargs root=/dev/$bdev rw " \ 707 "console=$consoledev,$baudrate $othbootargs;" \ 708 "tftp $loadaddr $bootfile;" \ 709 "tftp $fdtaddr $fdtfile;" \ 710 "bootm $loadaddr - $fdtaddr" 711 712 #define CONFIG_NFSBOOTCOMMAND \ 713 "setenv bootargs root=/dev/nfs rw " \ 714 "nfsroot=$serverip:$rootpath " \ 715 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 716 "console=$consoledev,$baudrate $othbootargs;" \ 717 "tftp $loadaddr $bootfile;" \ 718 "tftp $fdtaddr $fdtfile;" \ 719 "bootm $loadaddr - $fdtaddr" 720 721 #define CONFIG_RAMBOOTCOMMAND \ 722 "setenv bootargs root=/dev/ram rw " \ 723 "console=$consoledev,$baudrate $othbootargs;" \ 724 "tftp $ramdiskaddr $ramdiskfile;" \ 725 "tftp $loadaddr $bootfile;" \ 726 "tftp $fdtaddr $fdtfile;" \ 727 "bootm $loadaddr $ramdiskaddr $fdtaddr" 728 729 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 730 731 #include <asm/fsl_secure_boot.h> 732 733 #endif /* __CONFIG_H */ 734