1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240RDB 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_FSL_SATA_V2 17 #define CONFIG_PCIE4 18 19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 23 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg 24 #ifndef CONFIG_SDCARD 25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #else 28 #define CONFIG_SPL_FLUSH_IMAGE 29 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 30 #define CONFIG_FSL_LAW /* Use common FSL init code */ 31 #define CONFIG_SYS_TEXT_BASE 0x00201000 32 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 33 #define CONFIG_SPL_PAD_TO 0x40000 34 #define CONFIG_SPL_MAX_SIZE 0x28000 35 #define RESET_VECTOR_OFFSET 0x27FFC 36 #define BOOT_PAGE_OFFSET 0x27000 37 38 #ifdef CONFIG_SDCARD 39 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 40 #define CONFIG_SPL_MMC_MINIMAL 41 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 42 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 43 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 44 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 45 #ifndef CONFIG_SPL_BUILD 46 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 47 #endif 48 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 49 #define CONFIG_SPL_MMC_BOOT 50 #endif 51 52 #ifdef CONFIG_SPL_BUILD 53 #define CONFIG_SPL_SKIP_RELOCATE 54 #define CONFIG_SPL_COMMON_INIT_DDR 55 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 56 #define CONFIG_SYS_NO_FLASH 57 #endif 58 59 #endif 60 #endif /* CONFIG_RAMBOOT_PBL */ 61 62 #define CONFIG_DDR_ECC 63 64 #define CONFIG_CMD_REGINFO 65 66 /* High Level Configuration Options */ 67 #define CONFIG_BOOKE 68 #define CONFIG_E500 /* BOOKE e500 family */ 69 #define CONFIG_E500MC /* BOOKE e500mc family */ 70 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 71 #define CONFIG_MP /* support multiple processors */ 72 73 #ifndef CONFIG_SYS_TEXT_BASE 74 #define CONFIG_SYS_TEXT_BASE 0xeff40000 75 #endif 76 77 #ifndef CONFIG_RESET_VECTOR_ADDRESS 78 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 79 #endif 80 81 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 82 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 83 #define CONFIG_FSL_IFC /* Enable IFC Support */ 84 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 85 #define CONFIG_PCI /* Enable PCI/PCIE */ 86 #define CONFIG_PCIE1 /* PCIE controller 1 */ 87 #define CONFIG_PCIE2 /* PCIE controller 2 */ 88 #define CONFIG_PCIE3 /* PCIE controller 3 */ 89 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 90 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 91 92 #define CONFIG_FSL_LAW /* Use common FSL init code */ 93 94 #define CONFIG_ENV_OVERWRITE 95 96 /* 97 * These can be toggled for performance analysis, otherwise use default. 98 */ 99 #define CONFIG_SYS_CACHE_STASHING 100 #define CONFIG_BTB /* toggle branch predition */ 101 #ifdef CONFIG_DDR_ECC 102 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 103 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 104 #endif 105 106 #define CONFIG_ENABLE_36BIT_PHYS 107 108 #define CONFIG_ADDR_MAP 109 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 110 111 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 112 #define CONFIG_SYS_MEMTEST_END 0x00400000 113 #define CONFIG_SYS_ALT_MEMTEST 114 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 115 116 /* 117 * Config the L3 Cache as L3 SRAM 118 */ 119 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 120 #define CONFIG_SYS_L3_SIZE (512 << 10) 121 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 122 #ifdef CONFIG_RAMBOOT_PBL 123 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 124 #endif 125 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 126 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 127 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 128 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 129 130 #define CONFIG_SYS_DCSRBAR 0xf0000000 131 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 132 133 /* 134 * DDR Setup 135 */ 136 #define CONFIG_VERY_BIG_RAM 137 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 138 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 139 140 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 141 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 142 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 143 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 144 145 #define CONFIG_DDR_SPD 146 #define CONFIG_SYS_FSL_DDR3 147 148 /* 149 * IFC Definitions 150 */ 151 #define CONFIG_SYS_FLASH_BASE 0xe0000000 152 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 153 154 #ifdef CONFIG_SPL_BUILD 155 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 156 #else 157 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 158 #endif 159 160 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 161 #define CONFIG_MISC_INIT_R 162 163 #define CONFIG_HWCONFIG 164 165 /* define to use L1 as initial stack */ 166 #define CONFIG_L1_INIT_RAM 167 #define CONFIG_SYS_INIT_RAM_LOCK 168 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 169 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 170 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 171 /* The assembler doesn't like typecast */ 172 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 173 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 174 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 175 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 176 177 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 178 GENERATED_GBL_DATA_SIZE) 179 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 180 181 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 182 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 183 184 /* Serial Port - controlled on board with jumper J8 185 * open - index 2 186 * shorted - index 1 187 */ 188 #define CONFIG_CONS_INDEX 1 189 #define CONFIG_SYS_NS16550_SERIAL 190 #define CONFIG_SYS_NS16550_REG_SIZE 1 191 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 192 193 #define CONFIG_SYS_BAUDRATE_TABLE \ 194 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 195 196 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 197 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 198 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 199 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 200 201 /* I2C */ 202 #define CONFIG_SYS_I2C 203 #define CONFIG_SYS_I2C_FSL 204 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 205 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 206 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 207 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 208 209 /* 210 * General PCI 211 * Memory space is mapped 1-1, but I/O space must start from 0. 212 */ 213 214 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 215 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 216 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 217 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 218 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 219 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 220 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 221 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 222 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 223 224 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 225 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 226 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 227 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 228 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 229 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 230 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 231 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 232 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 233 234 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 235 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 236 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 237 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 238 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 239 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 240 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 241 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 242 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 243 244 /* controller 4, Base address 203000 */ 245 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 246 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 247 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 248 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 249 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 250 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 251 252 #ifdef CONFIG_PCI 253 #define CONFIG_PCI_INDIRECT_BRIDGE 254 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 255 256 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 257 #define CONFIG_DOS_PARTITION 258 #endif /* CONFIG_PCI */ 259 260 /* SATA */ 261 #ifdef CONFIG_FSL_SATA_V2 262 #define CONFIG_LIBATA 263 #define CONFIG_FSL_SATA 264 265 #define CONFIG_SYS_SATA_MAX_DEVICE 2 266 #define CONFIG_SATA1 267 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 268 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 269 #define CONFIG_SATA2 270 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 271 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 272 273 #define CONFIG_LBA48 274 #define CONFIG_CMD_SATA 275 #define CONFIG_DOS_PARTITION 276 #endif 277 278 #ifdef CONFIG_FMAN_ENET 279 #define CONFIG_MII /* MII PHY management */ 280 #define CONFIG_ETHPRIME "FM1@DTSEC1" 281 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 282 #endif 283 284 /* 285 * Environment 286 */ 287 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 288 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 289 290 /* 291 * Command line configuration. 292 */ 293 #define CONFIG_CMD_ERRATA 294 #define CONFIG_CMD_IRQ 295 296 #ifdef CONFIG_PCI 297 #define CONFIG_CMD_PCI 298 #endif 299 300 /* 301 * Miscellaneous configurable options 302 */ 303 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 304 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 305 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 306 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 307 #ifdef CONFIG_CMD_KGDB 308 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 309 #else 310 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 311 #endif 312 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 313 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 314 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 315 316 /* 317 * For booting Linux, the board info and command line data 318 * have to be in the first 64 MB of memory, since this is 319 * the maximum mapped by the Linux kernel during initialization. 320 */ 321 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 322 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 323 324 #ifdef CONFIG_CMD_KGDB 325 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 326 #endif 327 328 /* 329 * Environment Configuration 330 */ 331 #define CONFIG_ROOTPATH "/opt/nfsroot" 332 #define CONFIG_BOOTFILE "uImage" 333 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 334 335 /* default location for tftp and bootm */ 336 #define CONFIG_LOADADDR 1000000 337 338 #define CONFIG_BAUDRATE 115200 339 340 #define CONFIG_HVBOOT \ 341 "setenv bootargs config-addr=0x60000000; " \ 342 "bootm 0x01000000 - 0x00f00000" 343 344 #ifdef CONFIG_SYS_NO_FLASH 345 #ifndef CONFIG_RAMBOOT_PBL 346 #define CONFIG_ENV_IS_NOWHERE 347 #endif 348 #else 349 #define CONFIG_FLASH_CFI_DRIVER 350 #define CONFIG_SYS_FLASH_CFI 351 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 352 #endif 353 354 #if defined(CONFIG_SPIFLASH) 355 #define CONFIG_SYS_EXTRA_ENV_RELOC 356 #define CONFIG_ENV_IS_IN_SPI_FLASH 357 #define CONFIG_ENV_SPI_BUS 0 358 #define CONFIG_ENV_SPI_CS 0 359 #define CONFIG_ENV_SPI_MAX_HZ 10000000 360 #define CONFIG_ENV_SPI_MODE 0 361 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 362 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 363 #define CONFIG_ENV_SECT_SIZE 0x10000 364 #elif defined(CONFIG_SDCARD) 365 #define CONFIG_SYS_EXTRA_ENV_RELOC 366 #define CONFIG_ENV_IS_IN_MMC 367 #define CONFIG_SYS_MMC_ENV_DEV 0 368 #define CONFIG_ENV_SIZE 0x2000 369 #define CONFIG_ENV_OFFSET (512 * 0x800) 370 #elif defined(CONFIG_NAND) 371 #define CONFIG_SYS_EXTRA_ENV_RELOC 372 #define CONFIG_ENV_IS_IN_NAND 373 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 374 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 375 #elif defined(CONFIG_ENV_IS_NOWHERE) 376 #define CONFIG_ENV_SIZE 0x2000 377 #else 378 #define CONFIG_ENV_IS_IN_FLASH 379 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 380 #define CONFIG_ENV_SIZE 0x2000 381 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 382 #endif 383 384 #define CONFIG_SYS_CLK_FREQ 66666666 385 #define CONFIG_DDR_CLK_FREQ 133333333 386 387 #ifndef __ASSEMBLY__ 388 unsigned long get_board_sys_clk(void); 389 unsigned long get_board_ddr_clk(void); 390 #endif 391 392 /* 393 * DDR Setup 394 */ 395 #define CONFIG_SYS_SPD_BUS_NUM 0 396 #define SPD_EEPROM_ADDRESS1 0x52 397 #define SPD_EEPROM_ADDRESS2 0x54 398 #define SPD_EEPROM_ADDRESS3 0x56 399 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 400 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 401 402 /* 403 * IFC Definitions 404 */ 405 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 406 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 407 + 0x8000000) | \ 408 CSPR_PORT_SIZE_16 | \ 409 CSPR_MSEL_NOR | \ 410 CSPR_V) 411 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 412 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 413 CSPR_PORT_SIZE_16 | \ 414 CSPR_MSEL_NOR | \ 415 CSPR_V) 416 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 417 /* NOR Flash Timing Params */ 418 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 419 420 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 421 FTIM0_NOR_TEADC(0x5) | \ 422 FTIM0_NOR_TEAHC(0x5)) 423 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 424 FTIM1_NOR_TRAD_NOR(0x1A) |\ 425 FTIM1_NOR_TSEQRAD_NOR(0x13)) 426 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 427 FTIM2_NOR_TCH(0x4) | \ 428 FTIM2_NOR_TWPH(0x0E) | \ 429 FTIM2_NOR_TWP(0x1c)) 430 #define CONFIG_SYS_NOR_FTIM3 0x0 431 432 #define CONFIG_SYS_FLASH_QUIET_TEST 433 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 434 435 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 436 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 437 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 438 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 439 440 #define CONFIG_SYS_FLASH_EMPTY_INFO 441 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 442 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 443 444 /* NAND Flash on IFC */ 445 #define CONFIG_NAND_FSL_IFC 446 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 447 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 448 #define CONFIG_SYS_NAND_BASE 0xff800000 449 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 450 451 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 452 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 453 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 454 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 455 | CSPR_V) 456 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 457 458 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 459 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 460 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 461 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 462 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 463 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 464 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 465 466 #define CONFIG_SYS_NAND_ONFI_DETECTION 467 468 /* ONFI NAND Flash mode0 Timing Params */ 469 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 470 FTIM0_NAND_TWP(0x18) | \ 471 FTIM0_NAND_TWCHT(0x07) | \ 472 FTIM0_NAND_TWH(0x0a)) 473 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 474 FTIM1_NAND_TWBE(0x39) | \ 475 FTIM1_NAND_TRR(0x0e) | \ 476 FTIM1_NAND_TRP(0x18)) 477 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 478 FTIM2_NAND_TREH(0x0a) | \ 479 FTIM2_NAND_TWHRE(0x1e)) 480 #define CONFIG_SYS_NAND_FTIM3 0x0 481 482 #define CONFIG_SYS_NAND_DDR_LAW 11 483 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 484 #define CONFIG_SYS_MAX_NAND_DEVICE 1 485 #define CONFIG_CMD_NAND 486 487 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 488 489 #if defined(CONFIG_NAND) 490 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 491 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 492 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 493 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 494 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 495 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 496 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 497 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 498 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 499 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 500 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 501 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 502 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 503 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 504 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 505 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 506 #else 507 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 508 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 509 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 510 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 511 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 512 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 513 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 514 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 515 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 516 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 517 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 518 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 519 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 520 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 521 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 522 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 523 #endif 524 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 525 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 526 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 527 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 528 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 529 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 530 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 531 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 532 533 /* CPLD on IFC */ 534 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 535 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 536 #define CONFIG_SYS_CSPR3_EXT (0xf) 537 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 538 | CSPR_PORT_SIZE_8 \ 539 | CSPR_MSEL_GPCM \ 540 | CSPR_V) 541 542 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 543 #define CONFIG_SYS_CSOR3 0x0 544 545 /* CPLD Timing parameters for IFC CS3 */ 546 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 547 FTIM0_GPCM_TEADC(0x0e) | \ 548 FTIM0_GPCM_TEAHC(0x0e)) 549 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 550 FTIM1_GPCM_TRAD(0x1f)) 551 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 552 FTIM2_GPCM_TCH(0x8) | \ 553 FTIM2_GPCM_TWP(0x1f)) 554 #define CONFIG_SYS_CS3_FTIM3 0x0 555 556 #if defined(CONFIG_RAMBOOT_PBL) 557 #define CONFIG_SYS_RAMBOOT 558 #endif 559 560 /* I2C */ 561 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 562 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 563 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 564 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 565 566 #define I2C_MUX_CH_DEFAULT 0x8 567 #define I2C_MUX_CH_VOL_MONITOR 0xa 568 #define I2C_MUX_CH_VSC3316_FS 0xc 569 #define I2C_MUX_CH_VSC3316_BS 0xd 570 571 /* Voltage monitor on channel 2*/ 572 #define I2C_VOL_MONITOR_ADDR 0x40 573 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 574 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 575 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 576 577 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 578 #ifndef CONFIG_SPL_BUILD 579 #define CONFIG_VID 580 #endif 581 #define CONFIG_VOL_MONITOR_IR36021_SET 582 #define CONFIG_VOL_MONITOR_IR36021_READ 583 /* The lowest and highest voltage allowed for T4240RDB */ 584 #define VDD_MV_MIN 819 585 #define VDD_MV_MAX 1212 586 587 /* 588 * eSPI - Enhanced SPI 589 */ 590 #define CONFIG_SF_DEFAULT_SPEED 10000000 591 #define CONFIG_SF_DEFAULT_MODE 0 592 593 /* Qman/Bman */ 594 #ifndef CONFIG_NOBQFMAN 595 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 596 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 597 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 598 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 599 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 600 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 601 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 602 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 603 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 604 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 605 CONFIG_SYS_BMAN_CENA_SIZE) 606 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 607 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 608 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 609 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 610 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 611 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 612 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 613 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 614 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 615 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 616 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 617 CONFIG_SYS_QMAN_CENA_SIZE) 618 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 619 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 620 621 #define CONFIG_SYS_DPAA_FMAN 622 #define CONFIG_SYS_DPAA_PME 623 #define CONFIG_SYS_PMAN 624 #define CONFIG_SYS_DPAA_DCE 625 #define CONFIG_SYS_DPAA_RMAN 626 #define CONFIG_SYS_INTERLAKEN 627 628 /* Default address of microcode for the Linux Fman driver */ 629 #if defined(CONFIG_SPIFLASH) 630 /* 631 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 632 * env, so we got 0x110000. 633 */ 634 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 635 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 636 #elif defined(CONFIG_SDCARD) 637 /* 638 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 639 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 640 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 641 */ 642 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 643 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 644 #elif defined(CONFIG_NAND) 645 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 646 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 647 #else 648 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 649 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 650 #endif 651 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 652 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 653 #endif /* CONFIG_NOBQFMAN */ 654 655 #ifdef CONFIG_SYS_DPAA_FMAN 656 #define CONFIG_FMAN_ENET 657 #define CONFIG_PHYLIB_10G 658 #define CONFIG_PHY_VITESSE 659 #define CONFIG_PHY_CORTINA 660 #define CONFIG_SYS_CORTINA_FW_IN_NOR 661 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 662 #define CONFIG_CORTINA_FW_LENGTH 0x40000 663 #define CONFIG_PHY_TERANETICS 664 #define SGMII_PHY_ADDR1 0x0 665 #define SGMII_PHY_ADDR2 0x1 666 #define SGMII_PHY_ADDR3 0x2 667 #define SGMII_PHY_ADDR4 0x3 668 #define SGMII_PHY_ADDR5 0x4 669 #define SGMII_PHY_ADDR6 0x5 670 #define SGMII_PHY_ADDR7 0x6 671 #define SGMII_PHY_ADDR8 0x7 672 #define FM1_10GEC1_PHY_ADDR 0x10 673 #define FM1_10GEC2_PHY_ADDR 0x11 674 #define FM2_10GEC1_PHY_ADDR 0x12 675 #define FM2_10GEC2_PHY_ADDR 0x13 676 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 677 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 678 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 679 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 680 #endif 681 682 /* SATA */ 683 #ifdef CONFIG_FSL_SATA_V2 684 #define CONFIG_LIBATA 685 #define CONFIG_FSL_SATA 686 687 #define CONFIG_SYS_SATA_MAX_DEVICE 2 688 #define CONFIG_SATA1 689 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 690 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 691 #define CONFIG_SATA2 692 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 693 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 694 695 #define CONFIG_LBA48 696 #define CONFIG_CMD_SATA 697 #define CONFIG_DOS_PARTITION 698 #endif 699 700 #ifdef CONFIG_FMAN_ENET 701 #define CONFIG_MII /* MII PHY management */ 702 #define CONFIG_ETHPRIME "FM1@DTSEC1" 703 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 704 #endif 705 706 /* 707 * USB 708 */ 709 #define CONFIG_USB_EHCI 710 #define CONFIG_USB_EHCI_FSL 711 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 712 #define CONFIG_HAS_FSL_DR_USB 713 714 #define CONFIG_MMC 715 716 #ifdef CONFIG_MMC 717 #define CONFIG_FSL_ESDHC 718 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 719 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 720 #define CONFIG_GENERIC_MMC 721 #define CONFIG_DOS_PARTITION 722 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 723 #endif 724 725 /* Hash command with SHA acceleration supported in hardware */ 726 #ifdef CONFIG_FSL_CAAM 727 #define CONFIG_CMD_HASH 728 #define CONFIG_SHA_HW_ACCEL 729 #endif 730 731 732 #define __USB_PHY_TYPE utmi 733 734 /* 735 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 736 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 737 * interleaving. It can be cacheline, page, bank, superbank. 738 * See doc/README.fsl-ddr for details. 739 */ 740 #ifdef CONFIG_PPC_T4240 741 #define CTRL_INTLV_PREFERED 3way_4KB 742 #else 743 #define CTRL_INTLV_PREFERED cacheline 744 #endif 745 746 #define CONFIG_EXTRA_ENV_SETTINGS \ 747 "hwconfig=fsl_ddr:" \ 748 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 749 "bank_intlv=auto;" \ 750 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 751 "netdev=eth0\0" \ 752 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 753 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 754 "tftpflash=tftpboot $loadaddr $uboot && " \ 755 "protect off $ubootaddr +$filesize && " \ 756 "erase $ubootaddr +$filesize && " \ 757 "cp.b $loadaddr $ubootaddr $filesize && " \ 758 "protect on $ubootaddr +$filesize && " \ 759 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 760 "consoledev=ttyS0\0" \ 761 "ramdiskaddr=2000000\0" \ 762 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 763 "fdtaddr=1e00000\0" \ 764 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 765 "bdev=sda3\0" 766 767 #define CONFIG_HVBOOT \ 768 "setenv bootargs config-addr=0x60000000; " \ 769 "bootm 0x01000000 - 0x00f00000" 770 771 #define CONFIG_LINUX \ 772 "setenv bootargs root=/dev/ram rw " \ 773 "console=$consoledev,$baudrate $othbootargs;" \ 774 "setenv ramdiskaddr 0x02000000;" \ 775 "setenv fdtaddr 0x00c00000;" \ 776 "setenv loadaddr 0x1000000;" \ 777 "bootm $loadaddr $ramdiskaddr $fdtaddr" 778 779 #define CONFIG_HDBOOT \ 780 "setenv bootargs root=/dev/$bdev rw " \ 781 "console=$consoledev,$baudrate $othbootargs;" \ 782 "tftp $loadaddr $bootfile;" \ 783 "tftp $fdtaddr $fdtfile;" \ 784 "bootm $loadaddr - $fdtaddr" 785 786 #define CONFIG_NFSBOOTCOMMAND \ 787 "setenv bootargs root=/dev/nfs rw " \ 788 "nfsroot=$serverip:$rootpath " \ 789 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 790 "console=$consoledev,$baudrate $othbootargs;" \ 791 "tftp $loadaddr $bootfile;" \ 792 "tftp $fdtaddr $fdtfile;" \ 793 "bootm $loadaddr - $fdtaddr" 794 795 #define CONFIG_RAMBOOTCOMMAND \ 796 "setenv bootargs root=/dev/ram rw " \ 797 "console=$consoledev,$baudrate $othbootargs;" \ 798 "tftp $ramdiskaddr $ramdiskfile;" \ 799 "tftp $loadaddr $bootfile;" \ 800 "tftp $fdtaddr $fdtfile;" \ 801 "bootm $loadaddr $ramdiskaddr $fdtaddr" 802 803 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 804 805 #include <asm/fsl_secure_boot.h> 806 807 #endif /* __CONFIG_H */ 808