1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_FSL_SATA_V2 14 #define CONFIG_PCIE4 15 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 20 #ifndef CONFIG_SDCARD 21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 23 #else 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 27 #define CONFIG_SPL_PAD_TO 0x40000 28 #define CONFIG_SPL_MAX_SIZE 0x28000 29 #define RESET_VECTOR_OFFSET 0x27FFC 30 #define BOOT_PAGE_OFFSET 0x27000 31 32 #ifdef CONFIG_SDCARD 33 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 34 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 35 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 36 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 37 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 38 #ifndef CONFIG_SPL_BUILD 39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 40 #endif 41 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 42 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg 43 #define CONFIG_SPL_MMC_BOOT 44 #endif 45 46 #ifdef CONFIG_SPL_BUILD 47 #define CONFIG_SPL_SKIP_RELOCATE 48 #define CONFIG_SPL_COMMON_INIT_DDR 49 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 50 #endif 51 52 #endif 53 #endif /* CONFIG_RAMBOOT_PBL */ 54 55 #define CONFIG_DDR_ECC 56 57 /* High Level Configuration Options */ 58 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 59 #define CONFIG_MP /* support multiple processors */ 60 61 #ifndef CONFIG_RESET_VECTOR_ADDRESS 62 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 63 #endif 64 65 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 66 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 67 #define CONFIG_PCIE1 /* PCIE controller 1 */ 68 #define CONFIG_PCIE2 /* PCIE controller 2 */ 69 #define CONFIG_PCIE3 /* PCIE controller 3 */ 70 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 71 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 72 73 #define CONFIG_ENV_OVERWRITE 74 75 /* 76 * These can be toggled for performance analysis, otherwise use default. 77 */ 78 #define CONFIG_SYS_CACHE_STASHING 79 #define CONFIG_BTB /* toggle branch predition */ 80 #ifdef CONFIG_DDR_ECC 81 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 82 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 83 #endif 84 85 #define CONFIG_ENABLE_36BIT_PHYS 86 87 #define CONFIG_ADDR_MAP 88 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 89 90 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 91 #define CONFIG_SYS_MEMTEST_END 0x00400000 92 #define CONFIG_SYS_ALT_MEMTEST 93 94 /* 95 * Config the L3 Cache as L3 SRAM 96 */ 97 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 98 #define CONFIG_SYS_L3_SIZE (512 << 10) 99 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 100 #ifdef CONFIG_RAMBOOT_PBL 101 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 102 #endif 103 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 104 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 105 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 106 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 107 108 #define CONFIG_SYS_DCSRBAR 0xf0000000 109 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 110 111 /* 112 * DDR Setup 113 */ 114 #define CONFIG_VERY_BIG_RAM 115 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 116 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 117 118 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 119 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 120 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 121 122 #define CONFIG_DDR_SPD 123 124 /* 125 * IFC Definitions 126 */ 127 #define CONFIG_SYS_FLASH_BASE 0xe0000000 128 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 129 130 #ifdef CONFIG_SPL_BUILD 131 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 132 #else 133 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 134 #endif 135 136 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 137 #define CONFIG_MISC_INIT_R 138 139 #define CONFIG_HWCONFIG 140 141 /* define to use L1 as initial stack */ 142 #define CONFIG_L1_INIT_RAM 143 #define CONFIG_SYS_INIT_RAM_LOCK 144 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 145 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 146 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 147 /* The assembler doesn't like typecast */ 148 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 149 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 150 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 151 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 152 153 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 154 GENERATED_GBL_DATA_SIZE) 155 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 156 157 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 158 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 159 160 /* Serial Port - controlled on board with jumper J8 161 * open - index 2 162 * shorted - index 1 163 */ 164 #define CONFIG_SYS_NS16550_SERIAL 165 #define CONFIG_SYS_NS16550_REG_SIZE 1 166 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 167 168 #define CONFIG_SYS_BAUDRATE_TABLE \ 169 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 170 171 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 172 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 173 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 174 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 175 176 /* I2C */ 177 #define CONFIG_SYS_I2C 178 #define CONFIG_SYS_I2C_FSL 179 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 180 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 181 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 182 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 183 184 /* 185 * General PCI 186 * Memory space is mapped 1-1, but I/O space must start from 0. 187 */ 188 189 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 190 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 191 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 192 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 193 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 194 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 195 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 196 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 197 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 198 199 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 200 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 201 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 202 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 203 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 204 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 205 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 206 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 207 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 208 209 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 210 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 211 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 212 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 213 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 214 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 215 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 216 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 217 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 218 219 /* controller 4, Base address 203000 */ 220 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 221 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 222 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 223 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 224 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 225 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 226 227 #ifdef CONFIG_PCI 228 #define CONFIG_PCI_INDIRECT_BRIDGE 229 230 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 231 #endif /* CONFIG_PCI */ 232 233 /* SATA */ 234 #ifdef CONFIG_FSL_SATA_V2 235 #define CONFIG_SYS_SATA_MAX_DEVICE 2 236 #define CONFIG_SATA1 237 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 238 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 239 #define CONFIG_SATA2 240 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 241 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 242 243 #define CONFIG_LBA48 244 #endif 245 246 #ifdef CONFIG_FMAN_ENET 247 #define CONFIG_MII /* MII PHY management */ 248 #define CONFIG_ETHPRIME "FM1@DTSEC1" 249 #endif 250 251 /* 252 * Environment 253 */ 254 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 255 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 256 257 /* 258 * Command line configuration. 259 */ 260 261 /* 262 * Miscellaneous configurable options 263 */ 264 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 265 266 /* 267 * For booting Linux, the board info and command line data 268 * have to be in the first 64 MB of memory, since this is 269 * the maximum mapped by the Linux kernel during initialization. 270 */ 271 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 272 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 273 274 #ifdef CONFIG_CMD_KGDB 275 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 276 #endif 277 278 /* 279 * Environment Configuration 280 */ 281 #define CONFIG_ROOTPATH "/opt/nfsroot" 282 #define CONFIG_BOOTFILE "uImage" 283 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 284 285 /* default location for tftp and bootm */ 286 #define CONFIG_LOADADDR 1000000 287 288 #define CONFIG_HVBOOT \ 289 "setenv bootargs config-addr=0x60000000; " \ 290 "bootm 0x01000000 - 0x00f00000" 291 292 #ifndef CONFIG_MTD_NOR_FLASH 293 #else 294 #define CONFIG_FLASH_CFI_DRIVER 295 #define CONFIG_SYS_FLASH_CFI 296 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 297 #endif 298 299 #if defined(CONFIG_SPIFLASH) 300 #define CONFIG_SYS_EXTRA_ENV_RELOC 301 #define CONFIG_ENV_SPI_BUS 0 302 #define CONFIG_ENV_SPI_CS 0 303 #define CONFIG_ENV_SPI_MAX_HZ 10000000 304 #define CONFIG_ENV_SPI_MODE 0 305 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 306 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 307 #define CONFIG_ENV_SECT_SIZE 0x10000 308 #elif defined(CONFIG_SDCARD) 309 #define CONFIG_SYS_EXTRA_ENV_RELOC 310 #define CONFIG_SYS_MMC_ENV_DEV 0 311 #define CONFIG_ENV_SIZE 0x2000 312 #define CONFIG_ENV_OFFSET (512 * 0x800) 313 #elif defined(CONFIG_NAND) 314 #define CONFIG_SYS_EXTRA_ENV_RELOC 315 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 316 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 317 #elif defined(CONFIG_ENV_IS_NOWHERE) 318 #define CONFIG_ENV_SIZE 0x2000 319 #else 320 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 321 #define CONFIG_ENV_SIZE 0x2000 322 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 323 #endif 324 325 #define CONFIG_SYS_CLK_FREQ 66666666 326 #define CONFIG_DDR_CLK_FREQ 133333333 327 328 #ifndef __ASSEMBLY__ 329 unsigned long get_board_sys_clk(void); 330 unsigned long get_board_ddr_clk(void); 331 #endif 332 333 /* 334 * DDR Setup 335 */ 336 #define CONFIG_SYS_SPD_BUS_NUM 0 337 #define SPD_EEPROM_ADDRESS1 0x52 338 #define SPD_EEPROM_ADDRESS2 0x54 339 #define SPD_EEPROM_ADDRESS3 0x56 340 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 341 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 342 343 /* 344 * IFC Definitions 345 */ 346 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 347 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 348 + 0x8000000) | \ 349 CSPR_PORT_SIZE_16 | \ 350 CSPR_MSEL_NOR | \ 351 CSPR_V) 352 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 353 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 354 CSPR_PORT_SIZE_16 | \ 355 CSPR_MSEL_NOR | \ 356 CSPR_V) 357 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 358 /* NOR Flash Timing Params */ 359 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 360 361 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 362 FTIM0_NOR_TEADC(0x5) | \ 363 FTIM0_NOR_TEAHC(0x5)) 364 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 365 FTIM1_NOR_TRAD_NOR(0x1A) |\ 366 FTIM1_NOR_TSEQRAD_NOR(0x13)) 367 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 368 FTIM2_NOR_TCH(0x4) | \ 369 FTIM2_NOR_TWPH(0x0E) | \ 370 FTIM2_NOR_TWP(0x1c)) 371 #define CONFIG_SYS_NOR_FTIM3 0x0 372 373 #define CONFIG_SYS_FLASH_QUIET_TEST 374 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 375 376 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 377 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 378 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 379 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 380 381 #define CONFIG_SYS_FLASH_EMPTY_INFO 382 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 383 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 384 385 /* NAND Flash on IFC */ 386 #define CONFIG_NAND_FSL_IFC 387 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 388 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 389 #define CONFIG_SYS_NAND_BASE 0xff800000 390 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 391 392 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 393 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 394 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 395 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 396 | CSPR_V) 397 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 398 399 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 400 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 401 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 402 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 403 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 404 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 405 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 406 407 #define CONFIG_SYS_NAND_ONFI_DETECTION 408 409 /* ONFI NAND Flash mode0 Timing Params */ 410 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 411 FTIM0_NAND_TWP(0x18) | \ 412 FTIM0_NAND_TWCHT(0x07) | \ 413 FTIM0_NAND_TWH(0x0a)) 414 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 415 FTIM1_NAND_TWBE(0x39) | \ 416 FTIM1_NAND_TRR(0x0e) | \ 417 FTIM1_NAND_TRP(0x18)) 418 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 419 FTIM2_NAND_TREH(0x0a) | \ 420 FTIM2_NAND_TWHRE(0x1e)) 421 #define CONFIG_SYS_NAND_FTIM3 0x0 422 423 #define CONFIG_SYS_NAND_DDR_LAW 11 424 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 425 #define CONFIG_SYS_MAX_NAND_DEVICE 1 426 427 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 428 429 #if defined(CONFIG_NAND) 430 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 431 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 432 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 433 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 434 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 435 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 436 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 437 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 438 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 439 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 440 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 441 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 442 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 443 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 444 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 445 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 446 #else 447 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 448 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 449 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 450 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 451 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 452 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 453 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 454 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 455 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 456 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 457 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 458 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 459 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 460 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 461 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 462 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 463 #endif 464 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 465 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 466 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 467 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 468 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 469 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 470 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 471 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 472 473 /* CPLD on IFC */ 474 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 475 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 476 #define CONFIG_SYS_CSPR3_EXT (0xf) 477 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 478 | CSPR_PORT_SIZE_8 \ 479 | CSPR_MSEL_GPCM \ 480 | CSPR_V) 481 482 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 483 #define CONFIG_SYS_CSOR3 0x0 484 485 /* CPLD Timing parameters for IFC CS3 */ 486 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 487 FTIM0_GPCM_TEADC(0x0e) | \ 488 FTIM0_GPCM_TEAHC(0x0e)) 489 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 490 FTIM1_GPCM_TRAD(0x1f)) 491 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 492 FTIM2_GPCM_TCH(0x8) | \ 493 FTIM2_GPCM_TWP(0x1f)) 494 #define CONFIG_SYS_CS3_FTIM3 0x0 495 496 #if defined(CONFIG_RAMBOOT_PBL) 497 #define CONFIG_SYS_RAMBOOT 498 #endif 499 500 /* I2C */ 501 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 502 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 503 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 504 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 505 506 #define I2C_MUX_CH_DEFAULT 0x8 507 #define I2C_MUX_CH_VOL_MONITOR 0xa 508 #define I2C_MUX_CH_VSC3316_FS 0xc 509 #define I2C_MUX_CH_VSC3316_BS 0xd 510 511 /* Voltage monitor on channel 2*/ 512 #define I2C_VOL_MONITOR_ADDR 0x40 513 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 514 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 515 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 516 517 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 518 #ifndef CONFIG_SPL_BUILD 519 #define CONFIG_VID 520 #endif 521 #define CONFIG_VOL_MONITOR_IR36021_SET 522 #define CONFIG_VOL_MONITOR_IR36021_READ 523 /* The lowest and highest voltage allowed for T4240RDB */ 524 #define VDD_MV_MIN 819 525 #define VDD_MV_MAX 1212 526 527 /* 528 * eSPI - Enhanced SPI 529 */ 530 #define CONFIG_SF_DEFAULT_SPEED 10000000 531 #define CONFIG_SF_DEFAULT_MODE 0 532 533 /* Qman/Bman */ 534 #ifndef CONFIG_NOBQFMAN 535 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 536 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 537 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 538 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 539 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 540 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 541 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 542 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 543 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 544 CONFIG_SYS_BMAN_CENA_SIZE) 545 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 546 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 547 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 548 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 549 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 550 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 551 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 552 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 553 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 554 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 555 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 556 CONFIG_SYS_QMAN_CENA_SIZE) 557 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 558 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 559 560 #define CONFIG_SYS_DPAA_FMAN 561 #define CONFIG_SYS_DPAA_PME 562 #define CONFIG_SYS_PMAN 563 #define CONFIG_SYS_DPAA_DCE 564 #define CONFIG_SYS_DPAA_RMAN 565 #define CONFIG_SYS_INTERLAKEN 566 567 /* Default address of microcode for the Linux Fman driver */ 568 #if defined(CONFIG_SPIFLASH) 569 /* 570 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 571 * env, so we got 0x110000. 572 */ 573 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 574 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 575 #elif defined(CONFIG_SDCARD) 576 /* 577 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 578 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 579 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 580 */ 581 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 582 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 583 #elif defined(CONFIG_NAND) 584 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 585 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 586 #else 587 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 588 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 589 #endif 590 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 591 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 592 #endif /* CONFIG_NOBQFMAN */ 593 594 #ifdef CONFIG_SYS_DPAA_FMAN 595 #define CONFIG_FMAN_ENET 596 #define CONFIG_PHYLIB_10G 597 #define CONFIG_PHY_VITESSE 598 #define CONFIG_PHY_CORTINA 599 #define CONFIG_SYS_CORTINA_FW_IN_NOR 600 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 601 #define CONFIG_CORTINA_FW_LENGTH 0x40000 602 #define CONFIG_PHY_TERANETICS 603 #define SGMII_PHY_ADDR1 0x0 604 #define SGMII_PHY_ADDR2 0x1 605 #define SGMII_PHY_ADDR3 0x2 606 #define SGMII_PHY_ADDR4 0x3 607 #define SGMII_PHY_ADDR5 0x4 608 #define SGMII_PHY_ADDR6 0x5 609 #define SGMII_PHY_ADDR7 0x6 610 #define SGMII_PHY_ADDR8 0x7 611 #define FM1_10GEC1_PHY_ADDR 0x10 612 #define FM1_10GEC2_PHY_ADDR 0x11 613 #define FM2_10GEC1_PHY_ADDR 0x12 614 #define FM2_10GEC2_PHY_ADDR 0x13 615 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 616 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 617 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 618 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 619 #endif 620 621 /* SATA */ 622 #ifdef CONFIG_FSL_SATA_V2 623 #define CONFIG_SYS_SATA_MAX_DEVICE 2 624 #define CONFIG_SATA1 625 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 626 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 627 #define CONFIG_SATA2 628 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 629 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 630 631 #define CONFIG_LBA48 632 #endif 633 634 #ifdef CONFIG_FMAN_ENET 635 #define CONFIG_MII /* MII PHY management */ 636 #define CONFIG_ETHPRIME "FM1@DTSEC1" 637 #endif 638 639 /* 640 * USB 641 */ 642 #define CONFIG_USB_EHCI_FSL 643 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 644 #define CONFIG_HAS_FSL_DR_USB 645 646 #ifdef CONFIG_MMC 647 #define CONFIG_FSL_ESDHC 648 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 649 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 650 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 651 #endif 652 653 654 #define __USB_PHY_TYPE utmi 655 656 /* 657 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 658 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 659 * interleaving. It can be cacheline, page, bank, superbank. 660 * See doc/README.fsl-ddr for details. 661 */ 662 #ifdef CONFIG_ARCH_T4240 663 #define CTRL_INTLV_PREFERED 3way_4KB 664 #else 665 #define CTRL_INTLV_PREFERED cacheline 666 #endif 667 668 #define CONFIG_EXTRA_ENV_SETTINGS \ 669 "hwconfig=fsl_ddr:" \ 670 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 671 "bank_intlv=auto;" \ 672 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 673 "netdev=eth0\0" \ 674 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 675 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 676 "tftpflash=tftpboot $loadaddr $uboot && " \ 677 "protect off $ubootaddr +$filesize && " \ 678 "erase $ubootaddr +$filesize && " \ 679 "cp.b $loadaddr $ubootaddr $filesize && " \ 680 "protect on $ubootaddr +$filesize && " \ 681 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 682 "consoledev=ttyS0\0" \ 683 "ramdiskaddr=2000000\0" \ 684 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 685 "fdtaddr=1e00000\0" \ 686 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 687 "bdev=sda3\0" 688 689 #define CONFIG_HVBOOT \ 690 "setenv bootargs config-addr=0x60000000; " \ 691 "bootm 0x01000000 - 0x00f00000" 692 693 #define CONFIG_LINUX \ 694 "setenv bootargs root=/dev/ram rw " \ 695 "console=$consoledev,$baudrate $othbootargs;" \ 696 "setenv ramdiskaddr 0x02000000;" \ 697 "setenv fdtaddr 0x00c00000;" \ 698 "setenv loadaddr 0x1000000;" \ 699 "bootm $loadaddr $ramdiskaddr $fdtaddr" 700 701 #define CONFIG_HDBOOT \ 702 "setenv bootargs root=/dev/$bdev rw " \ 703 "console=$consoledev,$baudrate $othbootargs;" \ 704 "tftp $loadaddr $bootfile;" \ 705 "tftp $fdtaddr $fdtfile;" \ 706 "bootm $loadaddr - $fdtaddr" 707 708 #define CONFIG_NFSBOOTCOMMAND \ 709 "setenv bootargs root=/dev/nfs rw " \ 710 "nfsroot=$serverip:$rootpath " \ 711 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 712 "console=$consoledev,$baudrate $othbootargs;" \ 713 "tftp $loadaddr $bootfile;" \ 714 "tftp $fdtaddr $fdtfile;" \ 715 "bootm $loadaddr - $fdtaddr" 716 717 #define CONFIG_RAMBOOTCOMMAND \ 718 "setenv bootargs root=/dev/ram rw " \ 719 "console=$consoledev,$baudrate $othbootargs;" \ 720 "tftp $ramdiskaddr $ramdiskfile;" \ 721 "tftp $loadaddr $bootfile;" \ 722 "tftp $fdtaddr $fdtfile;" \ 723 "bootm $loadaddr $ramdiskaddr $fdtaddr" 724 725 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 726 727 #include <asm/fsl_secure_boot.h> 728 729 #endif /* __CONFIG_H */ 730