1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T4240 RDB board configuration file 8 */ 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_FSL_SATA_V2 13 #define CONFIG_PCIE4 14 15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 16 17 #ifdef CONFIG_RAMBOOT_PBL 18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 19 #ifndef CONFIG_SDCARD 20 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 21 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 22 #else 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 25 #define CONFIG_SPL_PAD_TO 0x40000 26 #define CONFIG_SPL_MAX_SIZE 0x28000 27 #define RESET_VECTOR_OFFSET 0x27FFC 28 #define BOOT_PAGE_OFFSET 0x27000 29 30 #ifdef CONFIG_SDCARD 31 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 32 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 33 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 34 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 35 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 36 #ifndef CONFIG_SPL_BUILD 37 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 38 #endif 39 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 40 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg 41 #define CONFIG_SPL_MMC_BOOT 42 #endif 43 44 #ifdef CONFIG_SPL_BUILD 45 #define CONFIG_SPL_SKIP_RELOCATE 46 #define CONFIG_SPL_COMMON_INIT_DDR 47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 48 #endif 49 50 #endif 51 #endif /* CONFIG_RAMBOOT_PBL */ 52 53 #define CONFIG_DDR_ECC 54 55 /* High Level Configuration Options */ 56 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 57 58 #ifndef CONFIG_RESET_VECTOR_ADDRESS 59 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 60 #endif 61 62 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 63 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 64 #define CONFIG_PCIE1 /* PCIE controller 1 */ 65 #define CONFIG_PCIE2 /* PCIE controller 2 */ 66 #define CONFIG_PCIE3 /* PCIE controller 3 */ 67 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 68 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 69 70 #define CONFIG_ENV_OVERWRITE 71 72 /* 73 * These can be toggled for performance analysis, otherwise use default. 74 */ 75 #define CONFIG_SYS_CACHE_STASHING 76 #define CONFIG_BTB /* toggle branch predition */ 77 #ifdef CONFIG_DDR_ECC 78 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 79 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 80 #endif 81 82 #define CONFIG_ENABLE_36BIT_PHYS 83 84 #define CONFIG_ADDR_MAP 85 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 86 87 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 88 #define CONFIG_SYS_MEMTEST_END 0x00400000 89 90 /* 91 * Config the L3 Cache as L3 SRAM 92 */ 93 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 94 #define CONFIG_SYS_L3_SIZE (512 << 10) 95 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 96 #ifdef CONFIG_RAMBOOT_PBL 97 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 98 #endif 99 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 100 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 101 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 102 103 #define CONFIG_SYS_DCSRBAR 0xf0000000 104 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 105 106 /* 107 * DDR Setup 108 */ 109 #define CONFIG_VERY_BIG_RAM 110 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 111 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 112 113 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 114 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 115 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 116 117 #define CONFIG_DDR_SPD 118 119 /* 120 * IFC Definitions 121 */ 122 #define CONFIG_SYS_FLASH_BASE 0xe0000000 123 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 124 125 #ifdef CONFIG_SPL_BUILD 126 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 127 #else 128 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 129 #endif 130 131 #define CONFIG_MISC_INIT_R 132 133 #define CONFIG_HWCONFIG 134 135 /* define to use L1 as initial stack */ 136 #define CONFIG_L1_INIT_RAM 137 #define CONFIG_SYS_INIT_RAM_LOCK 138 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 139 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 140 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 141 /* The assembler doesn't like typecast */ 142 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 143 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 144 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 145 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 146 147 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 148 GENERATED_GBL_DATA_SIZE) 149 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 150 151 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 152 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 153 154 /* Serial Port - controlled on board with jumper J8 155 * open - index 2 156 * shorted - index 1 157 */ 158 #define CONFIG_SYS_NS16550_SERIAL 159 #define CONFIG_SYS_NS16550_REG_SIZE 1 160 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 161 162 #define CONFIG_SYS_BAUDRATE_TABLE \ 163 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 164 165 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 166 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 167 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 168 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 169 170 /* I2C */ 171 #define CONFIG_SYS_I2C 172 #define CONFIG_SYS_I2C_FSL 173 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 174 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 175 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 176 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 177 178 /* 179 * General PCI 180 * Memory space is mapped 1-1, but I/O space must start from 0. 181 */ 182 183 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 184 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 185 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 186 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 187 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 188 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 189 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 190 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 191 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 192 193 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 194 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 195 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 196 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 197 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 198 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 199 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 200 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 201 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 202 203 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 204 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 205 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 206 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 207 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 208 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 209 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 210 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 211 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 212 213 /* controller 4, Base address 203000 */ 214 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 215 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 216 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 217 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 218 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 219 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 220 221 #ifdef CONFIG_PCI 222 #define CONFIG_PCI_INDIRECT_BRIDGE 223 224 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 225 #endif /* CONFIG_PCI */ 226 227 /* SATA */ 228 #ifdef CONFIG_FSL_SATA_V2 229 #define CONFIG_SYS_SATA_MAX_DEVICE 2 230 #define CONFIG_SATA1 231 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 232 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 233 #define CONFIG_SATA2 234 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 235 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 236 237 #define CONFIG_LBA48 238 #endif 239 240 #ifdef CONFIG_FMAN_ENET 241 #define CONFIG_MII /* MII PHY management */ 242 #define CONFIG_ETHPRIME "FM1@DTSEC1" 243 #endif 244 245 /* 246 * Environment 247 */ 248 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 249 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 250 251 /* 252 * Command line configuration. 253 */ 254 255 /* 256 * Miscellaneous configurable options 257 */ 258 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 259 260 /* 261 * For booting Linux, the board info and command line data 262 * have to be in the first 64 MB of memory, since this is 263 * the maximum mapped by the Linux kernel during initialization. 264 */ 265 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 266 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 267 268 #ifdef CONFIG_CMD_KGDB 269 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 270 #endif 271 272 /* 273 * Environment Configuration 274 */ 275 #define CONFIG_ROOTPATH "/opt/nfsroot" 276 #define CONFIG_BOOTFILE "uImage" 277 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 278 279 /* default location for tftp and bootm */ 280 #define CONFIG_LOADADDR 1000000 281 282 #define CONFIG_HVBOOT \ 283 "setenv bootargs config-addr=0x60000000; " \ 284 "bootm 0x01000000 - 0x00f00000" 285 286 #ifndef CONFIG_MTD_NOR_FLASH 287 #else 288 #define CONFIG_FLASH_CFI_DRIVER 289 #define CONFIG_SYS_FLASH_CFI 290 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 291 #endif 292 293 #if defined(CONFIG_SPIFLASH) 294 #define CONFIG_SYS_EXTRA_ENV_RELOC 295 #define CONFIG_ENV_SPI_BUS 0 296 #define CONFIG_ENV_SPI_CS 0 297 #define CONFIG_ENV_SPI_MAX_HZ 10000000 298 #define CONFIG_ENV_SPI_MODE 0 299 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 300 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 301 #define CONFIG_ENV_SECT_SIZE 0x10000 302 #elif defined(CONFIG_SDCARD) 303 #define CONFIG_SYS_EXTRA_ENV_RELOC 304 #define CONFIG_SYS_MMC_ENV_DEV 0 305 #define CONFIG_ENV_SIZE 0x2000 306 #define CONFIG_ENV_OFFSET (512 * 0x800) 307 #elif defined(CONFIG_NAND) 308 #define CONFIG_SYS_EXTRA_ENV_RELOC 309 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 310 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 311 #elif defined(CONFIG_ENV_IS_NOWHERE) 312 #define CONFIG_ENV_SIZE 0x2000 313 #else 314 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 315 #define CONFIG_ENV_SIZE 0x2000 316 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 317 #endif 318 319 #define CONFIG_SYS_CLK_FREQ 66666666 320 #define CONFIG_DDR_CLK_FREQ 133333333 321 322 #ifndef __ASSEMBLY__ 323 unsigned long get_board_sys_clk(void); 324 unsigned long get_board_ddr_clk(void); 325 #endif 326 327 /* 328 * DDR Setup 329 */ 330 #define CONFIG_SYS_SPD_BUS_NUM 0 331 #define SPD_EEPROM_ADDRESS1 0x52 332 #define SPD_EEPROM_ADDRESS2 0x54 333 #define SPD_EEPROM_ADDRESS3 0x56 334 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 335 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 336 337 /* 338 * IFC Definitions 339 */ 340 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 341 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 342 + 0x8000000) | \ 343 CSPR_PORT_SIZE_16 | \ 344 CSPR_MSEL_NOR | \ 345 CSPR_V) 346 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 347 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 348 CSPR_PORT_SIZE_16 | \ 349 CSPR_MSEL_NOR | \ 350 CSPR_V) 351 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 352 /* NOR Flash Timing Params */ 353 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 354 355 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 356 FTIM0_NOR_TEADC(0x5) | \ 357 FTIM0_NOR_TEAHC(0x5)) 358 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 359 FTIM1_NOR_TRAD_NOR(0x1A) |\ 360 FTIM1_NOR_TSEQRAD_NOR(0x13)) 361 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 362 FTIM2_NOR_TCH(0x4) | \ 363 FTIM2_NOR_TWPH(0x0E) | \ 364 FTIM2_NOR_TWP(0x1c)) 365 #define CONFIG_SYS_NOR_FTIM3 0x0 366 367 #define CONFIG_SYS_FLASH_QUIET_TEST 368 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 369 370 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 371 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 372 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 373 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 374 375 #define CONFIG_SYS_FLASH_EMPTY_INFO 376 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 377 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 378 379 /* NAND Flash on IFC */ 380 #define CONFIG_NAND_FSL_IFC 381 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 382 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 383 #define CONFIG_SYS_NAND_BASE 0xff800000 384 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 385 386 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 387 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 388 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 389 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 390 | CSPR_V) 391 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 392 393 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 394 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 395 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 396 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 397 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 398 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 399 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 400 401 #define CONFIG_SYS_NAND_ONFI_DETECTION 402 403 /* ONFI NAND Flash mode0 Timing Params */ 404 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 405 FTIM0_NAND_TWP(0x18) | \ 406 FTIM0_NAND_TWCHT(0x07) | \ 407 FTIM0_NAND_TWH(0x0a)) 408 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 409 FTIM1_NAND_TWBE(0x39) | \ 410 FTIM1_NAND_TRR(0x0e) | \ 411 FTIM1_NAND_TRP(0x18)) 412 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 413 FTIM2_NAND_TREH(0x0a) | \ 414 FTIM2_NAND_TWHRE(0x1e)) 415 #define CONFIG_SYS_NAND_FTIM3 0x0 416 417 #define CONFIG_SYS_NAND_DDR_LAW 11 418 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 419 #define CONFIG_SYS_MAX_NAND_DEVICE 1 420 421 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 422 423 #if defined(CONFIG_NAND) 424 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 425 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 426 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 427 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 428 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 429 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 430 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 431 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 432 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 433 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 434 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 435 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 436 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 437 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 438 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 439 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 440 #else 441 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 442 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 443 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 444 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 445 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 446 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 447 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 448 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 449 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 450 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 451 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 452 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 453 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 454 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 455 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 456 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 457 #endif 458 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 459 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 460 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 461 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 462 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 463 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 464 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 465 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 466 467 /* CPLD on IFC */ 468 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 469 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 470 #define CONFIG_SYS_CSPR3_EXT (0xf) 471 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 472 | CSPR_PORT_SIZE_8 \ 473 | CSPR_MSEL_GPCM \ 474 | CSPR_V) 475 476 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 477 #define CONFIG_SYS_CSOR3 0x0 478 479 /* CPLD Timing parameters for IFC CS3 */ 480 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 481 FTIM0_GPCM_TEADC(0x0e) | \ 482 FTIM0_GPCM_TEAHC(0x0e)) 483 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 484 FTIM1_GPCM_TRAD(0x1f)) 485 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 486 FTIM2_GPCM_TCH(0x8) | \ 487 FTIM2_GPCM_TWP(0x1f)) 488 #define CONFIG_SYS_CS3_FTIM3 0x0 489 490 #if defined(CONFIG_RAMBOOT_PBL) 491 #define CONFIG_SYS_RAMBOOT 492 #endif 493 494 /* I2C */ 495 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 496 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 497 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 498 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 499 500 #define I2C_MUX_CH_DEFAULT 0x8 501 #define I2C_MUX_CH_VOL_MONITOR 0xa 502 #define I2C_MUX_CH_VSC3316_FS 0xc 503 #define I2C_MUX_CH_VSC3316_BS 0xd 504 505 /* Voltage monitor on channel 2*/ 506 #define I2C_VOL_MONITOR_ADDR 0x40 507 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 508 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 509 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 510 511 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 512 #ifndef CONFIG_SPL_BUILD 513 #define CONFIG_VID 514 #endif 515 #define CONFIG_VOL_MONITOR_IR36021_SET 516 #define CONFIG_VOL_MONITOR_IR36021_READ 517 /* The lowest and highest voltage allowed for T4240RDB */ 518 #define VDD_MV_MIN 819 519 #define VDD_MV_MAX 1212 520 521 /* 522 * eSPI - Enhanced SPI 523 */ 524 #define CONFIG_SF_DEFAULT_SPEED 10000000 525 #define CONFIG_SF_DEFAULT_MODE 0 526 527 /* Qman/Bman */ 528 #ifndef CONFIG_NOBQFMAN 529 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 530 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 531 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 532 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 533 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 534 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 535 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 536 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 537 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 538 CONFIG_SYS_BMAN_CENA_SIZE) 539 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 540 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 541 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 542 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 543 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 544 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 545 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 546 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 547 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 548 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 549 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 550 CONFIG_SYS_QMAN_CENA_SIZE) 551 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 552 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 553 554 #define CONFIG_SYS_DPAA_FMAN 555 #define CONFIG_SYS_DPAA_PME 556 #define CONFIG_SYS_PMAN 557 #define CONFIG_SYS_DPAA_DCE 558 #define CONFIG_SYS_DPAA_RMAN 559 #define CONFIG_SYS_INTERLAKEN 560 561 /* Default address of microcode for the Linux Fman driver */ 562 #if defined(CONFIG_SPIFLASH) 563 /* 564 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 565 * env, so we got 0x110000. 566 */ 567 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 568 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 569 #elif defined(CONFIG_SDCARD) 570 /* 571 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 572 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 573 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 574 */ 575 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 576 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 577 #elif defined(CONFIG_NAND) 578 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 579 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 580 #else 581 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 582 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 583 #endif 584 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 585 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 586 #endif /* CONFIG_NOBQFMAN */ 587 588 #ifdef CONFIG_SYS_DPAA_FMAN 589 #define CONFIG_FMAN_ENET 590 #define CONFIG_PHYLIB_10G 591 #define CONFIG_PHY_VITESSE 592 #define CONFIG_PHY_CORTINA 593 #define CONFIG_SYS_CORTINA_FW_IN_NOR 594 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 595 #define CONFIG_CORTINA_FW_LENGTH 0x40000 596 #define CONFIG_PHY_TERANETICS 597 #define SGMII_PHY_ADDR1 0x0 598 #define SGMII_PHY_ADDR2 0x1 599 #define SGMII_PHY_ADDR3 0x2 600 #define SGMII_PHY_ADDR4 0x3 601 #define SGMII_PHY_ADDR5 0x4 602 #define SGMII_PHY_ADDR6 0x5 603 #define SGMII_PHY_ADDR7 0x6 604 #define SGMII_PHY_ADDR8 0x7 605 #define FM1_10GEC1_PHY_ADDR 0x10 606 #define FM1_10GEC2_PHY_ADDR 0x11 607 #define FM2_10GEC1_PHY_ADDR 0x12 608 #define FM2_10GEC2_PHY_ADDR 0x13 609 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 610 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 611 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 612 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 613 #endif 614 615 /* SATA */ 616 #ifdef CONFIG_FSL_SATA_V2 617 #define CONFIG_SYS_SATA_MAX_DEVICE 2 618 #define CONFIG_SATA1 619 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 620 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 621 #define CONFIG_SATA2 622 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 623 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 624 625 #define CONFIG_LBA48 626 #endif 627 628 #ifdef CONFIG_FMAN_ENET 629 #define CONFIG_MII /* MII PHY management */ 630 #define CONFIG_ETHPRIME "FM1@DTSEC1" 631 #endif 632 633 /* 634 * USB 635 */ 636 #define CONFIG_USB_EHCI_FSL 637 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 638 #define CONFIG_HAS_FSL_DR_USB 639 640 #ifdef CONFIG_MMC 641 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 642 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 643 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 644 #endif 645 646 647 #define __USB_PHY_TYPE utmi 648 649 /* 650 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 651 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 652 * interleaving. It can be cacheline, page, bank, superbank. 653 * See doc/README.fsl-ddr for details. 654 */ 655 #ifdef CONFIG_ARCH_T4240 656 #define CTRL_INTLV_PREFERED 3way_4KB 657 #else 658 #define CTRL_INTLV_PREFERED cacheline 659 #endif 660 661 #define CONFIG_EXTRA_ENV_SETTINGS \ 662 "hwconfig=fsl_ddr:" \ 663 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 664 "bank_intlv=auto;" \ 665 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 666 "netdev=eth0\0" \ 667 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 668 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 669 "tftpflash=tftpboot $loadaddr $uboot && " \ 670 "protect off $ubootaddr +$filesize && " \ 671 "erase $ubootaddr +$filesize && " \ 672 "cp.b $loadaddr $ubootaddr $filesize && " \ 673 "protect on $ubootaddr +$filesize && " \ 674 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 675 "consoledev=ttyS0\0" \ 676 "ramdiskaddr=2000000\0" \ 677 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 678 "fdtaddr=1e00000\0" \ 679 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 680 "bdev=sda3\0" 681 682 #define CONFIG_HVBOOT \ 683 "setenv bootargs config-addr=0x60000000; " \ 684 "bootm 0x01000000 - 0x00f00000" 685 686 #define CONFIG_LINUX \ 687 "setenv bootargs root=/dev/ram rw " \ 688 "console=$consoledev,$baudrate $othbootargs;" \ 689 "setenv ramdiskaddr 0x02000000;" \ 690 "setenv fdtaddr 0x00c00000;" \ 691 "setenv loadaddr 0x1000000;" \ 692 "bootm $loadaddr $ramdiskaddr $fdtaddr" 693 694 #define CONFIG_HDBOOT \ 695 "setenv bootargs root=/dev/$bdev rw " \ 696 "console=$consoledev,$baudrate $othbootargs;" \ 697 "tftp $loadaddr $bootfile;" \ 698 "tftp $fdtaddr $fdtfile;" \ 699 "bootm $loadaddr - $fdtaddr" 700 701 #define CONFIG_NFSBOOTCOMMAND \ 702 "setenv bootargs root=/dev/nfs rw " \ 703 "nfsroot=$serverip:$rootpath " \ 704 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 705 "console=$consoledev,$baudrate $othbootargs;" \ 706 "tftp $loadaddr $bootfile;" \ 707 "tftp $fdtaddr $fdtfile;" \ 708 "bootm $loadaddr - $fdtaddr" 709 710 #define CONFIG_RAMBOOTCOMMAND \ 711 "setenv bootargs root=/dev/ram rw " \ 712 "console=$consoledev,$baudrate $othbootargs;" \ 713 "tftp $ramdiskaddr $ramdiskfile;" \ 714 "tftp $loadaddr $bootfile;" \ 715 "tftp $fdtaddr $fdtfile;" \ 716 "bootm $loadaddr $ramdiskaddr $fdtaddr" 717 718 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 719 720 #include <asm/fsl_secure_boot.h> 721 722 #endif /* __CONFIG_H */ 723