1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_FSL_SATA_V2 14 #define CONFIG_PCIE4 15 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 20 #ifndef CONFIG_SDCARD 21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 23 #else 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SYS_TEXT_BASE 0x00201000 27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 #define CONFIG_SPL_MAX_SIZE 0x28000 30 #define RESET_VECTOR_OFFSET 0x27FFC 31 #define BOOT_PAGE_OFFSET 0x27000 32 33 #ifdef CONFIG_SDCARD 34 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 35 #define CONFIG_SPL_MMC_MINIMAL 36 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 37 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 38 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 39 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 40 #ifndef CONFIG_SPL_BUILD 41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 42 #endif 43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 44 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg 45 #define CONFIG_SPL_MMC_BOOT 46 #endif 47 48 #ifdef CONFIG_SPL_BUILD 49 #define CONFIG_SPL_SKIP_RELOCATE 50 #define CONFIG_SPL_COMMON_INIT_DDR 51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 52 #define CONFIG_SYS_NO_FLASH 53 #endif 54 55 #endif 56 #endif /* CONFIG_RAMBOOT_PBL */ 57 58 #define CONFIG_DDR_ECC 59 60 #define CONFIG_CMD_REGINFO 61 62 /* High Level Configuration Options */ 63 #define CONFIG_BOOKE 64 #define CONFIG_E500 /* BOOKE e500 family */ 65 #define CONFIG_E500MC /* BOOKE e500mc family */ 66 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 67 #define CONFIG_MP /* support multiple processors */ 68 69 #ifndef CONFIG_SYS_TEXT_BASE 70 #define CONFIG_SYS_TEXT_BASE 0xeff40000 71 #endif 72 73 #ifndef CONFIG_RESET_VECTOR_ADDRESS 74 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 75 #endif 76 77 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 78 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 79 #define CONFIG_FSL_IFC /* Enable IFC Support */ 80 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 81 #define CONFIG_PCIE1 /* PCIE controller 1 */ 82 #define CONFIG_PCIE2 /* PCIE controller 2 */ 83 #define CONFIG_PCIE3 /* PCIE controller 3 */ 84 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 85 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 86 87 #define CONFIG_ENV_OVERWRITE 88 89 /* 90 * These can be toggled for performance analysis, otherwise use default. 91 */ 92 #define CONFIG_SYS_CACHE_STASHING 93 #define CONFIG_BTB /* toggle branch predition */ 94 #ifdef CONFIG_DDR_ECC 95 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 96 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 97 #endif 98 99 #define CONFIG_ENABLE_36BIT_PHYS 100 101 #define CONFIG_ADDR_MAP 102 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 103 104 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 105 #define CONFIG_SYS_MEMTEST_END 0x00400000 106 #define CONFIG_SYS_ALT_MEMTEST 107 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 108 109 /* 110 * Config the L3 Cache as L3 SRAM 111 */ 112 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 113 #define CONFIG_SYS_L3_SIZE (512 << 10) 114 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 115 #ifdef CONFIG_RAMBOOT_PBL 116 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 117 #endif 118 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 119 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 120 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 121 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 122 123 #define CONFIG_SYS_DCSRBAR 0xf0000000 124 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 125 126 /* 127 * DDR Setup 128 */ 129 #define CONFIG_VERY_BIG_RAM 130 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 131 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 132 133 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 134 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 135 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 136 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 137 138 #define CONFIG_DDR_SPD 139 #define CONFIG_SYS_FSL_DDR3 140 141 /* 142 * IFC Definitions 143 */ 144 #define CONFIG_SYS_FLASH_BASE 0xe0000000 145 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 146 147 #ifdef CONFIG_SPL_BUILD 148 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 149 #else 150 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 151 #endif 152 153 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 154 #define CONFIG_MISC_INIT_R 155 156 #define CONFIG_HWCONFIG 157 158 /* define to use L1 as initial stack */ 159 #define CONFIG_L1_INIT_RAM 160 #define CONFIG_SYS_INIT_RAM_LOCK 161 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 162 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 163 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 164 /* The assembler doesn't like typecast */ 165 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 166 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 167 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 168 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 169 170 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 171 GENERATED_GBL_DATA_SIZE) 172 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 173 174 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 175 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 176 177 /* Serial Port - controlled on board with jumper J8 178 * open - index 2 179 * shorted - index 1 180 */ 181 #define CONFIG_CONS_INDEX 1 182 #define CONFIG_SYS_NS16550_SERIAL 183 #define CONFIG_SYS_NS16550_REG_SIZE 1 184 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 185 186 #define CONFIG_SYS_BAUDRATE_TABLE \ 187 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 188 189 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 190 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 191 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 192 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 193 194 /* I2C */ 195 #define CONFIG_SYS_I2C 196 #define CONFIG_SYS_I2C_FSL 197 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 198 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 199 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 200 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 201 202 /* 203 * General PCI 204 * Memory space is mapped 1-1, but I/O space must start from 0. 205 */ 206 207 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 208 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 209 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 210 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 211 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 212 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 213 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 214 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 215 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 216 217 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 218 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 219 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 220 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 221 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 222 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 223 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 224 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 225 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 226 227 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 228 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 229 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 230 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 231 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 232 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 233 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 234 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 235 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 236 237 /* controller 4, Base address 203000 */ 238 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 239 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 240 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 241 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 242 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 243 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 244 245 #ifdef CONFIG_PCI 246 #define CONFIG_PCI_INDIRECT_BRIDGE 247 248 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 249 #define CONFIG_DOS_PARTITION 250 #endif /* CONFIG_PCI */ 251 252 /* SATA */ 253 #ifdef CONFIG_FSL_SATA_V2 254 #define CONFIG_LIBATA 255 #define CONFIG_FSL_SATA 256 257 #define CONFIG_SYS_SATA_MAX_DEVICE 2 258 #define CONFIG_SATA1 259 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 260 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 261 #define CONFIG_SATA2 262 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 263 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 264 265 #define CONFIG_LBA48 266 #define CONFIG_CMD_SATA 267 #define CONFIG_DOS_PARTITION 268 #endif 269 270 #ifdef CONFIG_FMAN_ENET 271 #define CONFIG_MII /* MII PHY management */ 272 #define CONFIG_ETHPRIME "FM1@DTSEC1" 273 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 274 #endif 275 276 /* 277 * Environment 278 */ 279 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 280 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 281 282 /* 283 * Command line configuration. 284 */ 285 #define CONFIG_CMD_ERRATA 286 #define CONFIG_CMD_IRQ 287 288 #ifdef CONFIG_PCI 289 #define CONFIG_CMD_PCI 290 #endif 291 292 /* 293 * Miscellaneous configurable options 294 */ 295 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 296 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 297 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 298 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 299 #ifdef CONFIG_CMD_KGDB 300 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 301 #else 302 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 303 #endif 304 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 305 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 306 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 307 308 /* 309 * For booting Linux, the board info and command line data 310 * have to be in the first 64 MB of memory, since this is 311 * the maximum mapped by the Linux kernel during initialization. 312 */ 313 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 314 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 315 316 #ifdef CONFIG_CMD_KGDB 317 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 318 #endif 319 320 /* 321 * Environment Configuration 322 */ 323 #define CONFIG_ROOTPATH "/opt/nfsroot" 324 #define CONFIG_BOOTFILE "uImage" 325 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 326 327 /* default location for tftp and bootm */ 328 #define CONFIG_LOADADDR 1000000 329 330 #define CONFIG_BAUDRATE 115200 331 332 #define CONFIG_HVBOOT \ 333 "setenv bootargs config-addr=0x60000000; " \ 334 "bootm 0x01000000 - 0x00f00000" 335 336 #ifdef CONFIG_SYS_NO_FLASH 337 #ifndef CONFIG_RAMBOOT_PBL 338 #define CONFIG_ENV_IS_NOWHERE 339 #endif 340 #else 341 #define CONFIG_FLASH_CFI_DRIVER 342 #define CONFIG_SYS_FLASH_CFI 343 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 344 #endif 345 346 #if defined(CONFIG_SPIFLASH) 347 #define CONFIG_SYS_EXTRA_ENV_RELOC 348 #define CONFIG_ENV_IS_IN_SPI_FLASH 349 #define CONFIG_ENV_SPI_BUS 0 350 #define CONFIG_ENV_SPI_CS 0 351 #define CONFIG_ENV_SPI_MAX_HZ 10000000 352 #define CONFIG_ENV_SPI_MODE 0 353 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 354 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 355 #define CONFIG_ENV_SECT_SIZE 0x10000 356 #elif defined(CONFIG_SDCARD) 357 #define CONFIG_SYS_EXTRA_ENV_RELOC 358 #define CONFIG_ENV_IS_IN_MMC 359 #define CONFIG_SYS_MMC_ENV_DEV 0 360 #define CONFIG_ENV_SIZE 0x2000 361 #define CONFIG_ENV_OFFSET (512 * 0x800) 362 #elif defined(CONFIG_NAND) 363 #define CONFIG_SYS_EXTRA_ENV_RELOC 364 #define CONFIG_ENV_IS_IN_NAND 365 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 366 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 367 #elif defined(CONFIG_ENV_IS_NOWHERE) 368 #define CONFIG_ENV_SIZE 0x2000 369 #else 370 #define CONFIG_ENV_IS_IN_FLASH 371 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 372 #define CONFIG_ENV_SIZE 0x2000 373 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 374 #endif 375 376 #define CONFIG_SYS_CLK_FREQ 66666666 377 #define CONFIG_DDR_CLK_FREQ 133333333 378 379 #ifndef __ASSEMBLY__ 380 unsigned long get_board_sys_clk(void); 381 unsigned long get_board_ddr_clk(void); 382 #endif 383 384 /* 385 * DDR Setup 386 */ 387 #define CONFIG_SYS_SPD_BUS_NUM 0 388 #define SPD_EEPROM_ADDRESS1 0x52 389 #define SPD_EEPROM_ADDRESS2 0x54 390 #define SPD_EEPROM_ADDRESS3 0x56 391 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 392 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 393 394 /* 395 * IFC Definitions 396 */ 397 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 398 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 399 + 0x8000000) | \ 400 CSPR_PORT_SIZE_16 | \ 401 CSPR_MSEL_NOR | \ 402 CSPR_V) 403 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 404 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 405 CSPR_PORT_SIZE_16 | \ 406 CSPR_MSEL_NOR | \ 407 CSPR_V) 408 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 409 /* NOR Flash Timing Params */ 410 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 411 412 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 413 FTIM0_NOR_TEADC(0x5) | \ 414 FTIM0_NOR_TEAHC(0x5)) 415 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 416 FTIM1_NOR_TRAD_NOR(0x1A) |\ 417 FTIM1_NOR_TSEQRAD_NOR(0x13)) 418 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 419 FTIM2_NOR_TCH(0x4) | \ 420 FTIM2_NOR_TWPH(0x0E) | \ 421 FTIM2_NOR_TWP(0x1c)) 422 #define CONFIG_SYS_NOR_FTIM3 0x0 423 424 #define CONFIG_SYS_FLASH_QUIET_TEST 425 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 426 427 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 428 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 429 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 430 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 431 432 #define CONFIG_SYS_FLASH_EMPTY_INFO 433 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 434 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 435 436 /* NAND Flash on IFC */ 437 #define CONFIG_NAND_FSL_IFC 438 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 439 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 440 #define CONFIG_SYS_NAND_BASE 0xff800000 441 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 442 443 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 444 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 445 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 446 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 447 | CSPR_V) 448 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 449 450 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 451 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 452 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 453 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 454 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 455 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 456 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 457 458 #define CONFIG_SYS_NAND_ONFI_DETECTION 459 460 /* ONFI NAND Flash mode0 Timing Params */ 461 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 462 FTIM0_NAND_TWP(0x18) | \ 463 FTIM0_NAND_TWCHT(0x07) | \ 464 FTIM0_NAND_TWH(0x0a)) 465 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 466 FTIM1_NAND_TWBE(0x39) | \ 467 FTIM1_NAND_TRR(0x0e) | \ 468 FTIM1_NAND_TRP(0x18)) 469 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 470 FTIM2_NAND_TREH(0x0a) | \ 471 FTIM2_NAND_TWHRE(0x1e)) 472 #define CONFIG_SYS_NAND_FTIM3 0x0 473 474 #define CONFIG_SYS_NAND_DDR_LAW 11 475 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 476 #define CONFIG_SYS_MAX_NAND_DEVICE 1 477 #define CONFIG_CMD_NAND 478 479 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 480 481 #if defined(CONFIG_NAND) 482 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 483 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 484 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 485 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 486 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 487 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 488 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 489 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 490 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 491 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 492 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 493 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 494 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 495 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 496 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 497 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 498 #else 499 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 500 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 501 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 502 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 503 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 504 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 505 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 506 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 507 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 508 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 509 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 510 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 511 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 512 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 513 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 514 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 515 #endif 516 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 517 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 518 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 519 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 520 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 521 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 522 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 523 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 524 525 /* CPLD on IFC */ 526 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 527 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 528 #define CONFIG_SYS_CSPR3_EXT (0xf) 529 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 530 | CSPR_PORT_SIZE_8 \ 531 | CSPR_MSEL_GPCM \ 532 | CSPR_V) 533 534 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 535 #define CONFIG_SYS_CSOR3 0x0 536 537 /* CPLD Timing parameters for IFC CS3 */ 538 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 539 FTIM0_GPCM_TEADC(0x0e) | \ 540 FTIM0_GPCM_TEAHC(0x0e)) 541 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 542 FTIM1_GPCM_TRAD(0x1f)) 543 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 544 FTIM2_GPCM_TCH(0x8) | \ 545 FTIM2_GPCM_TWP(0x1f)) 546 #define CONFIG_SYS_CS3_FTIM3 0x0 547 548 #if defined(CONFIG_RAMBOOT_PBL) 549 #define CONFIG_SYS_RAMBOOT 550 #endif 551 552 /* I2C */ 553 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 554 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 555 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 556 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 557 558 #define I2C_MUX_CH_DEFAULT 0x8 559 #define I2C_MUX_CH_VOL_MONITOR 0xa 560 #define I2C_MUX_CH_VSC3316_FS 0xc 561 #define I2C_MUX_CH_VSC3316_BS 0xd 562 563 /* Voltage monitor on channel 2*/ 564 #define I2C_VOL_MONITOR_ADDR 0x40 565 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 566 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 567 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 568 569 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 570 #ifndef CONFIG_SPL_BUILD 571 #define CONFIG_VID 572 #endif 573 #define CONFIG_VOL_MONITOR_IR36021_SET 574 #define CONFIG_VOL_MONITOR_IR36021_READ 575 /* The lowest and highest voltage allowed for T4240RDB */ 576 #define VDD_MV_MIN 819 577 #define VDD_MV_MAX 1212 578 579 /* 580 * eSPI - Enhanced SPI 581 */ 582 #define CONFIG_SF_DEFAULT_SPEED 10000000 583 #define CONFIG_SF_DEFAULT_MODE 0 584 585 /* Qman/Bman */ 586 #ifndef CONFIG_NOBQFMAN 587 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 588 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 589 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 590 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 591 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 592 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 593 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 594 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 595 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 596 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 597 CONFIG_SYS_BMAN_CENA_SIZE) 598 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 599 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 600 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 601 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 602 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 603 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 604 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 605 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 606 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 607 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 608 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 609 CONFIG_SYS_QMAN_CENA_SIZE) 610 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 611 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 612 613 #define CONFIG_SYS_DPAA_FMAN 614 #define CONFIG_SYS_DPAA_PME 615 #define CONFIG_SYS_PMAN 616 #define CONFIG_SYS_DPAA_DCE 617 #define CONFIG_SYS_DPAA_RMAN 618 #define CONFIG_SYS_INTERLAKEN 619 620 /* Default address of microcode for the Linux Fman driver */ 621 #if defined(CONFIG_SPIFLASH) 622 /* 623 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 624 * env, so we got 0x110000. 625 */ 626 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 627 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 628 #elif defined(CONFIG_SDCARD) 629 /* 630 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 631 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 632 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 633 */ 634 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 635 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 636 #elif defined(CONFIG_NAND) 637 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 638 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 639 #else 640 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 641 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 642 #endif 643 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 644 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 645 #endif /* CONFIG_NOBQFMAN */ 646 647 #ifdef CONFIG_SYS_DPAA_FMAN 648 #define CONFIG_FMAN_ENET 649 #define CONFIG_PHYLIB_10G 650 #define CONFIG_PHY_VITESSE 651 #define CONFIG_PHY_CORTINA 652 #define CONFIG_SYS_CORTINA_FW_IN_NOR 653 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 654 #define CONFIG_CORTINA_FW_LENGTH 0x40000 655 #define CONFIG_PHY_TERANETICS 656 #define SGMII_PHY_ADDR1 0x0 657 #define SGMII_PHY_ADDR2 0x1 658 #define SGMII_PHY_ADDR3 0x2 659 #define SGMII_PHY_ADDR4 0x3 660 #define SGMII_PHY_ADDR5 0x4 661 #define SGMII_PHY_ADDR6 0x5 662 #define SGMII_PHY_ADDR7 0x6 663 #define SGMII_PHY_ADDR8 0x7 664 #define FM1_10GEC1_PHY_ADDR 0x10 665 #define FM1_10GEC2_PHY_ADDR 0x11 666 #define FM2_10GEC1_PHY_ADDR 0x12 667 #define FM2_10GEC2_PHY_ADDR 0x13 668 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 669 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 670 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 671 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 672 #endif 673 674 /* SATA */ 675 #ifdef CONFIG_FSL_SATA_V2 676 #define CONFIG_LIBATA 677 #define CONFIG_FSL_SATA 678 679 #define CONFIG_SYS_SATA_MAX_DEVICE 2 680 #define CONFIG_SATA1 681 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 682 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 683 #define CONFIG_SATA2 684 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 685 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 686 687 #define CONFIG_LBA48 688 #define CONFIG_CMD_SATA 689 #define CONFIG_DOS_PARTITION 690 #endif 691 692 #ifdef CONFIG_FMAN_ENET 693 #define CONFIG_MII /* MII PHY management */ 694 #define CONFIG_ETHPRIME "FM1@DTSEC1" 695 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 696 #endif 697 698 /* 699 * USB 700 */ 701 #define CONFIG_USB_EHCI 702 #define CONFIG_USB_EHCI_FSL 703 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 704 #define CONFIG_HAS_FSL_DR_USB 705 706 #ifdef CONFIG_MMC 707 #define CONFIG_FSL_ESDHC 708 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 709 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 710 #define CONFIG_GENERIC_MMC 711 #define CONFIG_DOS_PARTITION 712 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 713 #endif 714 715 /* Hash command with SHA acceleration supported in hardware */ 716 #ifdef CONFIG_FSL_CAAM 717 #define CONFIG_CMD_HASH 718 #define CONFIG_SHA_HW_ACCEL 719 #endif 720 721 722 #define __USB_PHY_TYPE utmi 723 724 /* 725 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 726 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 727 * interleaving. It can be cacheline, page, bank, superbank. 728 * See doc/README.fsl-ddr for details. 729 */ 730 #ifdef CONFIG_ARCH_T4240 731 #define CTRL_INTLV_PREFERED 3way_4KB 732 #else 733 #define CTRL_INTLV_PREFERED cacheline 734 #endif 735 736 #define CONFIG_EXTRA_ENV_SETTINGS \ 737 "hwconfig=fsl_ddr:" \ 738 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 739 "bank_intlv=auto;" \ 740 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 741 "netdev=eth0\0" \ 742 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 743 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 744 "tftpflash=tftpboot $loadaddr $uboot && " \ 745 "protect off $ubootaddr +$filesize && " \ 746 "erase $ubootaddr +$filesize && " \ 747 "cp.b $loadaddr $ubootaddr $filesize && " \ 748 "protect on $ubootaddr +$filesize && " \ 749 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 750 "consoledev=ttyS0\0" \ 751 "ramdiskaddr=2000000\0" \ 752 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 753 "fdtaddr=1e00000\0" \ 754 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 755 "bdev=sda3\0" 756 757 #define CONFIG_HVBOOT \ 758 "setenv bootargs config-addr=0x60000000; " \ 759 "bootm 0x01000000 - 0x00f00000" 760 761 #define CONFIG_LINUX \ 762 "setenv bootargs root=/dev/ram rw " \ 763 "console=$consoledev,$baudrate $othbootargs;" \ 764 "setenv ramdiskaddr 0x02000000;" \ 765 "setenv fdtaddr 0x00c00000;" \ 766 "setenv loadaddr 0x1000000;" \ 767 "bootm $loadaddr $ramdiskaddr $fdtaddr" 768 769 #define CONFIG_HDBOOT \ 770 "setenv bootargs root=/dev/$bdev rw " \ 771 "console=$consoledev,$baudrate $othbootargs;" \ 772 "tftp $loadaddr $bootfile;" \ 773 "tftp $fdtaddr $fdtfile;" \ 774 "bootm $loadaddr - $fdtaddr" 775 776 #define CONFIG_NFSBOOTCOMMAND \ 777 "setenv bootargs root=/dev/nfs rw " \ 778 "nfsroot=$serverip:$rootpath " \ 779 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 780 "console=$consoledev,$baudrate $othbootargs;" \ 781 "tftp $loadaddr $bootfile;" \ 782 "tftp $fdtaddr $fdtfile;" \ 783 "bootm $loadaddr - $fdtaddr" 784 785 #define CONFIG_RAMBOOTCOMMAND \ 786 "setenv bootargs root=/dev/ram rw " \ 787 "console=$consoledev,$baudrate $othbootargs;" \ 788 "tftp $ramdiskaddr $ramdiskfile;" \ 789 "tftp $loadaddr $bootfile;" \ 790 "tftp $fdtaddr $fdtfile;" \ 791 "bootm $loadaddr $ramdiskaddr $fdtaddr" 792 793 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 794 795 #include <asm/fsl_secure_boot.h> 796 797 #endif /* __CONFIG_H */ 798