1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240RDB 14 #define CONFIG_PHYS_64BIT 15 #define CONFIG_SYS_GENERIC_BOARD 16 #define CONFIG_DISPLAY_BOARDINFO 17 18 #define CONFIG_FSL_SATA_V2 19 #define CONFIG_PCIE4 20 21 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 22 23 #ifdef CONFIG_RAMBOOT_PBL 24 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 25 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg 26 #ifndef CONFIG_SDCARD 27 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 28 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 29 #else 30 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 31 #define CONFIG_SPL_ENV_SUPPORT 32 #define CONFIG_SPL_SERIAL_SUPPORT 33 #define CONFIG_SPL_FLUSH_IMAGE 34 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 35 #define CONFIG_SPL_LIBGENERIC_SUPPORT 36 #define CONFIG_SPL_LIBCOMMON_SUPPORT 37 #define CONFIG_SPL_I2C_SUPPORT 38 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 39 #define CONFIG_FSL_LAW /* Use common FSL init code */ 40 #define CONFIG_SYS_TEXT_BASE 0x00201000 41 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 42 #define CONFIG_SPL_PAD_TO 0x40000 43 #define CONFIG_SPL_MAX_SIZE 0x28000 44 #define RESET_VECTOR_OFFSET 0x27FFC 45 #define BOOT_PAGE_OFFSET 0x27000 46 47 #ifdef CONFIG_SDCARD 48 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 49 #define CONFIG_SPL_MMC_SUPPORT 50 #define CONFIG_SPL_MMC_MINIMAL 51 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 52 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 53 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 54 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 55 #ifndef CONFIG_SPL_BUILD 56 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 57 #endif 58 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 59 #define CONFIG_SPL_MMC_BOOT 60 #endif 61 62 #ifdef CONFIG_SPL_BUILD 63 #define CONFIG_SPL_SKIP_RELOCATE 64 #define CONFIG_SPL_COMMON_INIT_DDR 65 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 66 #define CONFIG_SYS_NO_FLASH 67 #endif 68 69 #endif 70 #endif /* CONFIG_RAMBOOT_PBL */ 71 72 #define CONFIG_DDR_ECC 73 74 #define CONFIG_CMD_REGINFO 75 76 /* High Level Configuration Options */ 77 #define CONFIG_BOOKE 78 #define CONFIG_E500 /* BOOKE e500 family */ 79 #define CONFIG_E500MC /* BOOKE e500mc family */ 80 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 81 #define CONFIG_MP /* support multiple processors */ 82 83 #ifndef CONFIG_SYS_TEXT_BASE 84 #define CONFIG_SYS_TEXT_BASE 0xeff40000 85 #endif 86 87 #ifndef CONFIG_RESET_VECTOR_ADDRESS 88 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 89 #endif 90 91 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 92 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 93 #define CONFIG_FSL_IFC /* Enable IFC Support */ 94 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 95 #define CONFIG_PCI /* Enable PCI/PCIE */ 96 #define CONFIG_PCIE1 /* PCIE controler 1 */ 97 #define CONFIG_PCIE2 /* PCIE controler 2 */ 98 #define CONFIG_PCIE3 /* PCIE controler 3 */ 99 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 100 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 101 102 #define CONFIG_FSL_LAW /* Use common FSL init code */ 103 104 #define CONFIG_ENV_OVERWRITE 105 106 /* 107 * These can be toggled for performance analysis, otherwise use default. 108 */ 109 #define CONFIG_SYS_CACHE_STASHING 110 #define CONFIG_BTB /* toggle branch predition */ 111 #ifdef CONFIG_DDR_ECC 112 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 113 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 114 #endif 115 116 #define CONFIG_ENABLE_36BIT_PHYS 117 118 #define CONFIG_ADDR_MAP 119 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 120 121 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 122 #define CONFIG_SYS_MEMTEST_END 0x00400000 123 #define CONFIG_SYS_ALT_MEMTEST 124 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 125 126 /* 127 * Config the L3 Cache as L3 SRAM 128 */ 129 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 130 #define CONFIG_SYS_L3_SIZE (512 << 10) 131 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 132 #ifdef CONFIG_RAMBOOT_PBL 133 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 134 #endif 135 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 136 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 137 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 138 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 139 140 #define CONFIG_SYS_DCSRBAR 0xf0000000 141 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 142 143 /* 144 * DDR Setup 145 */ 146 #define CONFIG_VERY_BIG_RAM 147 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 148 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 149 150 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 151 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 152 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 153 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 154 155 #define CONFIG_DDR_SPD 156 #define CONFIG_SYS_FSL_DDR3 157 158 159 /* 160 * IFC Definitions 161 */ 162 #define CONFIG_SYS_FLASH_BASE 0xe0000000 163 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 164 165 166 #ifdef CONFIG_SPL_BUILD 167 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 168 #else 169 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 170 #endif 171 172 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 173 #define CONFIG_MISC_INIT_R 174 175 #define CONFIG_HWCONFIG 176 177 /* define to use L1 as initial stack */ 178 #define CONFIG_L1_INIT_RAM 179 #define CONFIG_SYS_INIT_RAM_LOCK 180 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 181 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 182 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 183 /* The assembler doesn't like typecast */ 184 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 185 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 186 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 187 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 188 189 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 190 GENERATED_GBL_DATA_SIZE) 191 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 192 193 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 194 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 195 196 /* Serial Port - controlled on board with jumper J8 197 * open - index 2 198 * shorted - index 1 199 */ 200 #define CONFIG_CONS_INDEX 1 201 #define CONFIG_SYS_NS16550 202 #define CONFIG_SYS_NS16550_SERIAL 203 #define CONFIG_SYS_NS16550_REG_SIZE 1 204 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 205 206 #define CONFIG_SYS_BAUDRATE_TABLE \ 207 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 208 209 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 210 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 211 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 212 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 213 214 /* Use the HUSH parser */ 215 #define CONFIG_SYS_HUSH_PARSER 216 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 217 218 /* pass open firmware flat tree */ 219 #define CONFIG_OF_LIBFDT 220 #define CONFIG_OF_BOARD_SETUP 221 #define CONFIG_OF_STDOUT_VIA_ALIAS 222 223 /* new uImage format support */ 224 #define CONFIG_FIT 225 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 226 227 /* I2C */ 228 #define CONFIG_SYS_I2C 229 #define CONFIG_SYS_I2C_FSL 230 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 231 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 232 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 233 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 234 235 /* 236 * General PCI 237 * Memory space is mapped 1-1, but I/O space must start from 0. 238 */ 239 240 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 241 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 242 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 243 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 244 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 245 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 246 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 247 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 248 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 249 250 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 251 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 252 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 253 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 254 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 255 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 256 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 257 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 258 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 259 260 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 261 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 262 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 263 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 264 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 265 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 266 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 267 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 268 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 269 270 /* controller 4, Base address 203000 */ 271 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 272 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 273 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 274 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 275 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 276 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 277 278 #ifdef CONFIG_PCI 279 #define CONFIG_PCI_INDIRECT_BRIDGE 280 #define CONFIG_NET_MULTI 281 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 282 #define CONFIG_E1000 283 284 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 285 #define CONFIG_DOS_PARTITION 286 #endif /* CONFIG_PCI */ 287 288 /* SATA */ 289 #ifdef CONFIG_FSL_SATA_V2 290 #define CONFIG_LIBATA 291 #define CONFIG_FSL_SATA 292 293 #define CONFIG_SYS_SATA_MAX_DEVICE 2 294 #define CONFIG_SATA1 295 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 296 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 297 #define CONFIG_SATA2 298 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 299 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 300 301 #define CONFIG_LBA48 302 #define CONFIG_CMD_SATA 303 #define CONFIG_DOS_PARTITION 304 #define CONFIG_CMD_EXT2 305 #endif 306 307 #ifdef CONFIG_FMAN_ENET 308 #define CONFIG_MII /* MII PHY management */ 309 #define CONFIG_ETHPRIME "FM1@DTSEC1" 310 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 311 #endif 312 313 /* 314 * Environment 315 */ 316 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 317 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 318 319 /* 320 * Command line configuration. 321 */ 322 #include <config_cmd_default.h> 323 324 #define CONFIG_CMD_DHCP 325 #define CONFIG_CMD_ELF 326 #define CONFIG_CMD_ERRATA 327 #define CONFIG_CMD_GREPENV 328 #define CONFIG_CMD_IRQ 329 #define CONFIG_CMD_I2C 330 #define CONFIG_CMD_MII 331 #define CONFIG_CMD_PING 332 #define CONFIG_CMD_SETEXPR 333 334 #ifdef CONFIG_PCI 335 #define CONFIG_CMD_PCI 336 #define CONFIG_CMD_NET 337 #endif 338 339 /* 340 * Miscellaneous configurable options 341 */ 342 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 343 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 344 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 345 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 346 #ifdef CONFIG_CMD_KGDB 347 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 348 #else 349 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 350 #endif 351 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 352 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 353 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 354 355 /* 356 * For booting Linux, the board info and command line data 357 * have to be in the first 64 MB of memory, since this is 358 * the maximum mapped by the Linux kernel during initialization. 359 */ 360 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 361 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 362 363 #ifdef CONFIG_CMD_KGDB 364 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 365 #endif 366 367 /* 368 * Environment Configuration 369 */ 370 #define CONFIG_ROOTPATH "/opt/nfsroot" 371 #define CONFIG_BOOTFILE "uImage" 372 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 373 374 /* default location for tftp and bootm */ 375 #define CONFIG_LOADADDR 1000000 376 377 378 #define CONFIG_BAUDRATE 115200 379 380 #define CONFIG_HVBOOT \ 381 "setenv bootargs config-addr=0x60000000; " \ 382 "bootm 0x01000000 - 0x00f00000" 383 384 #ifdef CONFIG_SYS_NO_FLASH 385 #ifndef CONFIG_RAMBOOT_PBL 386 #define CONFIG_ENV_IS_NOWHERE 387 #endif 388 #else 389 #define CONFIG_FLASH_CFI_DRIVER 390 #define CONFIG_SYS_FLASH_CFI 391 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 392 #endif 393 394 #if defined(CONFIG_SPIFLASH) 395 #define CONFIG_SYS_EXTRA_ENV_RELOC 396 #define CONFIG_ENV_IS_IN_SPI_FLASH 397 #define CONFIG_ENV_SPI_BUS 0 398 #define CONFIG_ENV_SPI_CS 0 399 #define CONFIG_ENV_SPI_MAX_HZ 10000000 400 #define CONFIG_ENV_SPI_MODE 0 401 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 402 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 403 #define CONFIG_ENV_SECT_SIZE 0x10000 404 #elif defined(CONFIG_SDCARD) 405 #define CONFIG_SYS_EXTRA_ENV_RELOC 406 #define CONFIG_ENV_IS_IN_MMC 407 #define CONFIG_SYS_MMC_ENV_DEV 0 408 #define CONFIG_ENV_SIZE 0x2000 409 #define CONFIG_ENV_OFFSET (512 * 0x800) 410 #elif defined(CONFIG_NAND) 411 #define CONFIG_SYS_EXTRA_ENV_RELOC 412 #define CONFIG_ENV_IS_IN_NAND 413 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 414 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 415 #elif defined(CONFIG_ENV_IS_NOWHERE) 416 #define CONFIG_ENV_SIZE 0x2000 417 #else 418 #define CONFIG_ENV_IS_IN_FLASH 419 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 420 #define CONFIG_ENV_SIZE 0x2000 421 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 422 #endif 423 424 #define CONFIG_SYS_CLK_FREQ 66666666 425 #define CONFIG_DDR_CLK_FREQ 133333333 426 427 #ifndef __ASSEMBLY__ 428 unsigned long get_board_sys_clk(void); 429 unsigned long get_board_ddr_clk(void); 430 #endif 431 432 /* 433 * DDR Setup 434 */ 435 #define CONFIG_SYS_SPD_BUS_NUM 0 436 #define SPD_EEPROM_ADDRESS1 0x52 437 #define SPD_EEPROM_ADDRESS2 0x54 438 #define SPD_EEPROM_ADDRESS3 0x56 439 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 440 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 441 442 /* 443 * IFC Definitions 444 */ 445 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 446 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 447 + 0x8000000) | \ 448 CSPR_PORT_SIZE_16 | \ 449 CSPR_MSEL_NOR | \ 450 CSPR_V) 451 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 452 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 453 CSPR_PORT_SIZE_16 | \ 454 CSPR_MSEL_NOR | \ 455 CSPR_V) 456 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 457 /* NOR Flash Timing Params */ 458 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 459 460 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 461 FTIM0_NOR_TEADC(0x5) | \ 462 FTIM0_NOR_TEAHC(0x5)) 463 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 464 FTIM1_NOR_TRAD_NOR(0x1A) |\ 465 FTIM1_NOR_TSEQRAD_NOR(0x13)) 466 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 467 FTIM2_NOR_TCH(0x4) | \ 468 FTIM2_NOR_TWPH(0x0E) | \ 469 FTIM2_NOR_TWP(0x1c)) 470 #define CONFIG_SYS_NOR_FTIM3 0x0 471 472 #define CONFIG_SYS_FLASH_QUIET_TEST 473 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 474 475 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 476 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 477 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 478 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 479 480 #define CONFIG_SYS_FLASH_EMPTY_INFO 481 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 482 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 483 484 /* NAND Flash on IFC */ 485 #define CONFIG_NAND_FSL_IFC 486 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 487 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 488 #define CONFIG_SYS_NAND_BASE 0xff800000 489 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 490 491 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 492 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 493 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 494 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 495 | CSPR_V) 496 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 497 498 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 499 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 500 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 501 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 502 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 503 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 504 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 505 506 #define CONFIG_SYS_NAND_ONFI_DETECTION 507 508 /* ONFI NAND Flash mode0 Timing Params */ 509 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 510 FTIM0_NAND_TWP(0x18) | \ 511 FTIM0_NAND_TWCHT(0x07) | \ 512 FTIM0_NAND_TWH(0x0a)) 513 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 514 FTIM1_NAND_TWBE(0x39) | \ 515 FTIM1_NAND_TRR(0x0e) | \ 516 FTIM1_NAND_TRP(0x18)) 517 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 518 FTIM2_NAND_TREH(0x0a) | \ 519 FTIM2_NAND_TWHRE(0x1e)) 520 #define CONFIG_SYS_NAND_FTIM3 0x0 521 522 #define CONFIG_SYS_NAND_DDR_LAW 11 523 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 524 #define CONFIG_SYS_MAX_NAND_DEVICE 1 525 #define CONFIG_CMD_NAND 526 527 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 528 529 #if defined(CONFIG_NAND) 530 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 531 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 532 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 533 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 534 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 535 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 536 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 537 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 538 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 539 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 540 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 541 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 542 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 543 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 544 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 545 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 546 #else 547 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 548 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 549 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 550 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 551 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 552 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 553 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 554 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 555 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 556 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 557 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 558 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 559 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 560 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 561 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 562 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 563 #endif 564 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 565 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 566 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 567 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 568 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 569 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 570 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 571 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 572 573 /* CPLD on IFC */ 574 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 575 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 576 #define CONFIG_SYS_CSPR3_EXT (0xf) 577 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 578 | CSPR_PORT_SIZE_8 \ 579 | CSPR_MSEL_GPCM \ 580 | CSPR_V) 581 582 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 583 #define CONFIG_SYS_CSOR3 0x0 584 585 /* CPLD Timing parameters for IFC CS3 */ 586 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 587 FTIM0_GPCM_TEADC(0x0e) | \ 588 FTIM0_GPCM_TEAHC(0x0e)) 589 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 590 FTIM1_GPCM_TRAD(0x1f)) 591 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 592 FTIM2_GPCM_TCH(0x8) | \ 593 FTIM2_GPCM_TWP(0x1f)) 594 #define CONFIG_SYS_CS3_FTIM3 0x0 595 596 #if defined(CONFIG_RAMBOOT_PBL) 597 #define CONFIG_SYS_RAMBOOT 598 #endif 599 600 601 /* I2C */ 602 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 603 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 604 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 605 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 606 607 #define I2C_MUX_CH_DEFAULT 0x8 608 #define I2C_MUX_CH_VOL_MONITOR 0xa 609 #define I2C_MUX_CH_VSC3316_FS 0xc 610 #define I2C_MUX_CH_VSC3316_BS 0xd 611 612 /* Voltage monitor on channel 2*/ 613 #define I2C_VOL_MONITOR_ADDR 0x40 614 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 615 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 616 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 617 618 /* 619 * eSPI - Enhanced SPI 620 */ 621 #define CONFIG_FSL_ESPI 622 #define CONFIG_SPI_FLASH 623 #define CONFIG_SPI_FLASH_SST 624 #define CONFIG_CMD_SF 625 #define CONFIG_SF_DEFAULT_SPEED 10000000 626 #define CONFIG_SF_DEFAULT_MODE 0 627 628 629 /* Qman/Bman */ 630 #ifndef CONFIG_NOBQFMAN 631 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 632 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 633 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 634 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 635 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 636 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 637 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 638 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 639 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 640 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 641 CONFIG_SYS_BMAN_CENA_SIZE) 642 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 643 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 644 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 645 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 646 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 647 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 648 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 649 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 650 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 651 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 652 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 653 CONFIG_SYS_QMAN_CENA_SIZE) 654 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 655 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 656 657 #define CONFIG_SYS_DPAA_FMAN 658 #define CONFIG_SYS_DPAA_PME 659 #define CONFIG_SYS_PMAN 660 #define CONFIG_SYS_DPAA_DCE 661 #define CONFIG_SYS_DPAA_RMAN 662 #define CONFIG_SYS_INTERLAKEN 663 664 /* Default address of microcode for the Linux Fman driver */ 665 #if defined(CONFIG_SPIFLASH) 666 /* 667 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 668 * env, so we got 0x110000. 669 */ 670 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 671 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 672 #elif defined(CONFIG_SDCARD) 673 /* 674 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 675 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 676 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 677 */ 678 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 679 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 680 #elif defined(CONFIG_NAND) 681 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 682 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 683 #else 684 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 685 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 686 #endif 687 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 688 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 689 #endif /* CONFIG_NOBQFMAN */ 690 691 #ifdef CONFIG_SYS_DPAA_FMAN 692 #define CONFIG_FMAN_ENET 693 #define CONFIG_PHYLIB_10G 694 #define CONFIG_PHY_VITESSE 695 #define CONFIG_PHY_CORTINA 696 #define CONFIG_SYS_CORTINA_FW_IN_NOR 697 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 698 #define CONFIG_CORTINA_FW_LENGTH 0x40000 699 #define CONFIG_PHY_TERANETICS 700 #define SGMII_PHY_ADDR1 0x0 701 #define SGMII_PHY_ADDR2 0x1 702 #define SGMII_PHY_ADDR3 0x2 703 #define SGMII_PHY_ADDR4 0x3 704 #define SGMII_PHY_ADDR5 0x4 705 #define SGMII_PHY_ADDR6 0x5 706 #define SGMII_PHY_ADDR7 0x6 707 #define SGMII_PHY_ADDR8 0x7 708 #define FM1_10GEC1_PHY_ADDR 0x10 709 #define FM1_10GEC2_PHY_ADDR 0x11 710 #define FM2_10GEC1_PHY_ADDR 0x12 711 #define FM2_10GEC2_PHY_ADDR 0x13 712 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 713 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 714 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 715 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 716 #endif 717 718 719 /* SATA */ 720 #ifdef CONFIG_FSL_SATA_V2 721 #define CONFIG_LIBATA 722 #define CONFIG_FSL_SATA 723 724 #define CONFIG_SYS_SATA_MAX_DEVICE 2 725 #define CONFIG_SATA1 726 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 727 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 728 #define CONFIG_SATA2 729 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 730 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 731 732 #define CONFIG_LBA48 733 #define CONFIG_CMD_SATA 734 #define CONFIG_DOS_PARTITION 735 #define CONFIG_CMD_EXT2 736 #endif 737 738 #ifdef CONFIG_FMAN_ENET 739 #define CONFIG_MII /* MII PHY management */ 740 #define CONFIG_ETHPRIME "FM1@DTSEC1" 741 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 742 #endif 743 744 /* 745 * USB 746 */ 747 #define CONFIG_CMD_USB 748 #define CONFIG_USB_STORAGE 749 #define CONFIG_USB_EHCI 750 #define CONFIG_USB_EHCI_FSL 751 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 752 #define CONFIG_CMD_EXT2 753 #define CONFIG_HAS_FSL_DR_USB 754 755 #define CONFIG_MMC 756 757 #ifdef CONFIG_MMC 758 #define CONFIG_FSL_ESDHC 759 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 760 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 761 #define CONFIG_CMD_MMC 762 #define CONFIG_GENERIC_MMC 763 #define CONFIG_CMD_EXT2 764 #define CONFIG_CMD_FAT 765 #define CONFIG_DOS_PARTITION 766 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 767 #endif 768 769 /* Hash command with SHA acceleration supported in hardware */ 770 #ifdef CONFIG_FSL_CAAM 771 #define CONFIG_CMD_HASH 772 #define CONFIG_SHA_HW_ACCEL 773 #endif 774 775 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 776 777 #define __USB_PHY_TYPE utmi 778 779 /* 780 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 781 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 782 * interleaving. It can be cacheline, page, bank, superbank. 783 * See doc/README.fsl-ddr for details. 784 */ 785 #ifdef CONFIG_PPC_T4240 786 #define CTRL_INTLV_PREFERED 3way_4KB 787 #else 788 #define CTRL_INTLV_PREFERED cacheline 789 #endif 790 791 #define CONFIG_EXTRA_ENV_SETTINGS \ 792 "hwconfig=fsl_ddr:" \ 793 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 794 "bank_intlv=auto;" \ 795 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 796 "netdev=eth0\0" \ 797 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 798 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 799 "tftpflash=tftpboot $loadaddr $uboot && " \ 800 "protect off $ubootaddr +$filesize && " \ 801 "erase $ubootaddr +$filesize && " \ 802 "cp.b $loadaddr $ubootaddr $filesize && " \ 803 "protect on $ubootaddr +$filesize && " \ 804 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 805 "consoledev=ttyS0\0" \ 806 "ramdiskaddr=2000000\0" \ 807 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 808 "fdtaddr=c00000\0" \ 809 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 810 "bdev=sda3\0" 811 812 #define CONFIG_HVBOOT \ 813 "setenv bootargs config-addr=0x60000000; " \ 814 "bootm 0x01000000 - 0x00f00000" 815 816 #define CONFIG_LINUX \ 817 "setenv bootargs root=/dev/ram rw " \ 818 "console=$consoledev,$baudrate $othbootargs;" \ 819 "setenv ramdiskaddr 0x02000000;" \ 820 "setenv fdtaddr 0x00c00000;" \ 821 "setenv loadaddr 0x1000000;" \ 822 "bootm $loadaddr $ramdiskaddr $fdtaddr" 823 824 #define CONFIG_HDBOOT \ 825 "setenv bootargs root=/dev/$bdev rw " \ 826 "console=$consoledev,$baudrate $othbootargs;" \ 827 "tftp $loadaddr $bootfile;" \ 828 "tftp $fdtaddr $fdtfile;" \ 829 "bootm $loadaddr - $fdtaddr" 830 831 #define CONFIG_NFSBOOTCOMMAND \ 832 "setenv bootargs root=/dev/nfs rw " \ 833 "nfsroot=$serverip:$rootpath " \ 834 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 835 "console=$consoledev,$baudrate $othbootargs;" \ 836 "tftp $loadaddr $bootfile;" \ 837 "tftp $fdtaddr $fdtfile;" \ 838 "bootm $loadaddr - $fdtaddr" 839 840 #define CONFIG_RAMBOOTCOMMAND \ 841 "setenv bootargs root=/dev/ram rw " \ 842 "console=$consoledev,$baudrate $othbootargs;" \ 843 "tftp $ramdiskaddr $ramdiskfile;" \ 844 "tftp $loadaddr $bootfile;" \ 845 "tftp $fdtaddr $fdtfile;" \ 846 "bootm $loadaddr $ramdiskaddr $fdtaddr" 847 848 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 849 850 #include <asm/fsl_secure_boot.h> 851 852 #ifdef CONFIG_SECURE_BOOT 853 /* Secure Boot target was not getting build for T4240 because of 854 * increased binary size. So the size is being reduced by removing USB 855 * which is anyways not used in Secure Environment. 856 */ 857 #undef CONFIG_CMD_USB 858 #define CONFIG_CMD_BLOB 859 #endif 860 861 #endif /* __CONFIG_H */ 862