1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T4240 RDB board configuration file 8 */ 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_FSL_SATA_V2 13 #define CONFIG_PCIE4 14 15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 16 17 #ifdef CONFIG_RAMBOOT_PBL 18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 19 #ifndef CONFIG_SDCARD 20 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 21 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 22 #else 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 25 #define CONFIG_SPL_PAD_TO 0x40000 26 #define CONFIG_SPL_MAX_SIZE 0x28000 27 #define RESET_VECTOR_OFFSET 0x27FFC 28 #define BOOT_PAGE_OFFSET 0x27000 29 30 #ifdef CONFIG_SDCARD 31 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 32 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 33 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 34 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 35 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 36 #ifndef CONFIG_SPL_BUILD 37 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 38 #endif 39 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 40 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg 41 #define CONFIG_SPL_MMC_BOOT 42 #endif 43 44 #ifdef CONFIG_SPL_BUILD 45 #define CONFIG_SPL_SKIP_RELOCATE 46 #define CONFIG_SPL_COMMON_INIT_DDR 47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 48 #endif 49 50 #endif 51 #endif /* CONFIG_RAMBOOT_PBL */ 52 53 #define CONFIG_DDR_ECC 54 55 /* High Level Configuration Options */ 56 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 57 58 #ifndef CONFIG_RESET_VECTOR_ADDRESS 59 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 60 #endif 61 62 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 63 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 64 #define CONFIG_PCIE1 /* PCIE controller 1 */ 65 #define CONFIG_PCIE2 /* PCIE controller 2 */ 66 #define CONFIG_PCIE3 /* PCIE controller 3 */ 67 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 68 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 69 70 #define CONFIG_ENV_OVERWRITE 71 72 /* 73 * These can be toggled for performance analysis, otherwise use default. 74 */ 75 #define CONFIG_SYS_CACHE_STASHING 76 #define CONFIG_BTB /* toggle branch predition */ 77 #ifdef CONFIG_DDR_ECC 78 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 79 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 80 #endif 81 82 #define CONFIG_ENABLE_36BIT_PHYS 83 84 #define CONFIG_ADDR_MAP 85 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 86 87 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 88 #define CONFIG_SYS_MEMTEST_END 0x00400000 89 90 /* 91 * Config the L3 Cache as L3 SRAM 92 */ 93 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 94 #define CONFIG_SYS_L3_SIZE (512 << 10) 95 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 96 #ifdef CONFIG_RAMBOOT_PBL 97 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 98 #endif 99 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 100 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 101 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 102 103 #define CONFIG_SYS_DCSRBAR 0xf0000000 104 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 105 106 /* 107 * DDR Setup 108 */ 109 #define CONFIG_VERY_BIG_RAM 110 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 111 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 112 113 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 114 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 115 116 #define CONFIG_DDR_SPD 117 118 /* 119 * IFC Definitions 120 */ 121 #define CONFIG_SYS_FLASH_BASE 0xe0000000 122 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 123 124 #ifdef CONFIG_SPL_BUILD 125 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 126 #else 127 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 128 #endif 129 130 #define CONFIG_HWCONFIG 131 132 /* define to use L1 as initial stack */ 133 #define CONFIG_L1_INIT_RAM 134 #define CONFIG_SYS_INIT_RAM_LOCK 135 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 136 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 137 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 138 /* The assembler doesn't like typecast */ 139 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 140 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 141 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 142 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 143 144 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 145 GENERATED_GBL_DATA_SIZE) 146 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 147 148 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 149 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 150 151 /* Serial Port - controlled on board with jumper J8 152 * open - index 2 153 * shorted - index 1 154 */ 155 #define CONFIG_SYS_NS16550_SERIAL 156 #define CONFIG_SYS_NS16550_REG_SIZE 1 157 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 158 159 #define CONFIG_SYS_BAUDRATE_TABLE \ 160 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 161 162 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 163 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 164 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 165 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 166 167 /* I2C */ 168 #define CONFIG_SYS_I2C 169 #define CONFIG_SYS_I2C_FSL 170 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 171 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 172 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 173 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 174 175 /* 176 * General PCI 177 * Memory space is mapped 1-1, but I/O space must start from 0. 178 */ 179 180 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 181 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 182 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 183 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 184 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 185 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 186 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 187 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 188 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 189 190 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 191 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 192 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 193 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 194 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 195 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 196 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 197 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 198 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 199 200 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 201 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 202 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 203 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 204 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 205 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 206 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 207 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 208 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 209 210 /* controller 4, Base address 203000 */ 211 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 212 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 213 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 214 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 215 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 216 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 217 218 #ifdef CONFIG_PCI 219 #define CONFIG_PCI_INDIRECT_BRIDGE 220 221 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 222 #endif /* CONFIG_PCI */ 223 224 /* SATA */ 225 #ifdef CONFIG_FSL_SATA_V2 226 #define CONFIG_SYS_SATA_MAX_DEVICE 2 227 #define CONFIG_SATA1 228 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 229 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 230 #define CONFIG_SATA2 231 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 232 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 233 234 #define CONFIG_LBA48 235 #endif 236 237 #ifdef CONFIG_FMAN_ENET 238 #define CONFIG_ETHPRIME "FM1@DTSEC1" 239 #endif 240 241 /* 242 * Environment 243 */ 244 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 245 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 246 247 /* 248 * Command line configuration. 249 */ 250 251 /* 252 * Miscellaneous configurable options 253 */ 254 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 255 256 /* 257 * For booting Linux, the board info and command line data 258 * have to be in the first 64 MB of memory, since this is 259 * the maximum mapped by the Linux kernel during initialization. 260 */ 261 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 262 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 263 264 #ifdef CONFIG_CMD_KGDB 265 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 266 #endif 267 268 /* 269 * Environment Configuration 270 */ 271 #define CONFIG_ROOTPATH "/opt/nfsroot" 272 #define CONFIG_BOOTFILE "uImage" 273 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 274 275 /* default location for tftp and bootm */ 276 #define CONFIG_LOADADDR 1000000 277 278 #define CONFIG_HVBOOT \ 279 "setenv bootargs config-addr=0x60000000; " \ 280 "bootm 0x01000000 - 0x00f00000" 281 282 #if defined(CONFIG_SPIFLASH) 283 #define CONFIG_ENV_SPI_BUS 0 284 #define CONFIG_ENV_SPI_CS 0 285 #define CONFIG_ENV_SPI_MAX_HZ 10000000 286 #define CONFIG_ENV_SPI_MODE 0 287 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 288 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 289 #define CONFIG_ENV_SECT_SIZE 0x10000 290 #elif defined(CONFIG_SDCARD) 291 #define CONFIG_SYS_MMC_ENV_DEV 0 292 #define CONFIG_ENV_SIZE 0x2000 293 #define CONFIG_ENV_OFFSET (512 * 0x800) 294 #elif defined(CONFIG_NAND) 295 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 296 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 297 #elif defined(CONFIG_ENV_IS_NOWHERE) 298 #define CONFIG_ENV_SIZE 0x2000 299 #else 300 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 301 #define CONFIG_ENV_SIZE 0x2000 302 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 303 #endif 304 305 #define CONFIG_SYS_CLK_FREQ 66666666 306 #define CONFIG_DDR_CLK_FREQ 133333333 307 308 #ifndef __ASSEMBLY__ 309 unsigned long get_board_sys_clk(void); 310 unsigned long get_board_ddr_clk(void); 311 #endif 312 313 /* 314 * DDR Setup 315 */ 316 #define CONFIG_SYS_SPD_BUS_NUM 0 317 #define SPD_EEPROM_ADDRESS1 0x52 318 #define SPD_EEPROM_ADDRESS2 0x54 319 #define SPD_EEPROM_ADDRESS3 0x56 320 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 321 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 322 323 /* 324 * IFC Definitions 325 */ 326 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 327 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 328 + 0x8000000) | \ 329 CSPR_PORT_SIZE_16 | \ 330 CSPR_MSEL_NOR | \ 331 CSPR_V) 332 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 333 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 334 CSPR_PORT_SIZE_16 | \ 335 CSPR_MSEL_NOR | \ 336 CSPR_V) 337 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 338 /* NOR Flash Timing Params */ 339 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 340 341 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 342 FTIM0_NOR_TEADC(0x5) | \ 343 FTIM0_NOR_TEAHC(0x5)) 344 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 345 FTIM1_NOR_TRAD_NOR(0x1A) |\ 346 FTIM1_NOR_TSEQRAD_NOR(0x13)) 347 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 348 FTIM2_NOR_TCH(0x4) | \ 349 FTIM2_NOR_TWPH(0x0E) | \ 350 FTIM2_NOR_TWP(0x1c)) 351 #define CONFIG_SYS_NOR_FTIM3 0x0 352 353 #define CONFIG_SYS_FLASH_QUIET_TEST 354 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 355 356 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 357 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 358 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 359 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 360 361 #define CONFIG_SYS_FLASH_EMPTY_INFO 362 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 363 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 364 365 /* NAND Flash on IFC */ 366 #define CONFIG_NAND_FSL_IFC 367 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 368 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 369 #define CONFIG_SYS_NAND_BASE 0xff800000 370 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 371 372 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 373 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 374 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 375 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 376 | CSPR_V) 377 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 378 379 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 380 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 381 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 382 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 383 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 384 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 385 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 386 387 #define CONFIG_SYS_NAND_ONFI_DETECTION 388 389 /* ONFI NAND Flash mode0 Timing Params */ 390 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 391 FTIM0_NAND_TWP(0x18) | \ 392 FTIM0_NAND_TWCHT(0x07) | \ 393 FTIM0_NAND_TWH(0x0a)) 394 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 395 FTIM1_NAND_TWBE(0x39) | \ 396 FTIM1_NAND_TRR(0x0e) | \ 397 FTIM1_NAND_TRP(0x18)) 398 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 399 FTIM2_NAND_TREH(0x0a) | \ 400 FTIM2_NAND_TWHRE(0x1e)) 401 #define CONFIG_SYS_NAND_FTIM3 0x0 402 403 #define CONFIG_SYS_NAND_DDR_LAW 11 404 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 405 #define CONFIG_SYS_MAX_NAND_DEVICE 1 406 407 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 408 409 #if defined(CONFIG_NAND) 410 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 411 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 412 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 413 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 414 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 415 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 416 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 417 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 418 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 419 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 420 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 421 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 422 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 423 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 424 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 425 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 426 #else 427 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 428 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 429 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 430 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 431 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 432 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 433 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 434 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 435 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 436 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 437 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 438 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 439 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 440 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 441 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 442 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 443 #endif 444 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 445 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 446 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 447 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 448 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 449 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 450 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 451 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 452 453 /* CPLD on IFC */ 454 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 455 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 456 #define CONFIG_SYS_CSPR3_EXT (0xf) 457 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 458 | CSPR_PORT_SIZE_8 \ 459 | CSPR_MSEL_GPCM \ 460 | CSPR_V) 461 462 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) 463 #define CONFIG_SYS_CSOR3 0x0 464 465 /* CPLD Timing parameters for IFC CS3 */ 466 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 467 FTIM0_GPCM_TEADC(0x0e) | \ 468 FTIM0_GPCM_TEAHC(0x0e)) 469 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 470 FTIM1_GPCM_TRAD(0x1f)) 471 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 472 FTIM2_GPCM_TCH(0x8) | \ 473 FTIM2_GPCM_TWP(0x1f)) 474 #define CONFIG_SYS_CS3_FTIM3 0x0 475 476 #if defined(CONFIG_RAMBOOT_PBL) 477 #define CONFIG_SYS_RAMBOOT 478 #endif 479 480 /* I2C */ 481 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 482 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 483 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 484 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 485 486 #define I2C_MUX_CH_DEFAULT 0x8 487 #define I2C_MUX_CH_VOL_MONITOR 0xa 488 #define I2C_MUX_CH_VSC3316_FS 0xc 489 #define I2C_MUX_CH_VSC3316_BS 0xd 490 491 /* Voltage monitor on channel 2*/ 492 #define I2C_VOL_MONITOR_ADDR 0x40 493 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 494 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 495 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 496 497 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 498 #ifndef CONFIG_SPL_BUILD 499 #define CONFIG_VID 500 #endif 501 #define CONFIG_VOL_MONITOR_IR36021_SET 502 #define CONFIG_VOL_MONITOR_IR36021_READ 503 /* The lowest and highest voltage allowed for T4240RDB */ 504 #define VDD_MV_MIN 819 505 #define VDD_MV_MAX 1212 506 507 /* 508 * eSPI - Enhanced SPI 509 */ 510 #define CONFIG_SF_DEFAULT_SPEED 10000000 511 #define CONFIG_SF_DEFAULT_MODE 0 512 513 /* Qman/Bman */ 514 #ifndef CONFIG_NOBQFMAN 515 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 516 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 517 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 518 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 519 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 520 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 521 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 522 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 523 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 524 CONFIG_SYS_BMAN_CENA_SIZE) 525 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 526 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 527 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 528 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 529 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 530 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 531 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 532 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 533 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 534 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 535 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 536 CONFIG_SYS_QMAN_CENA_SIZE) 537 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 538 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 539 540 #define CONFIG_SYS_DPAA_FMAN 541 #define CONFIG_SYS_DPAA_PME 542 #define CONFIG_SYS_PMAN 543 #define CONFIG_SYS_DPAA_DCE 544 #define CONFIG_SYS_DPAA_RMAN 545 #define CONFIG_SYS_INTERLAKEN 546 547 /* Default address of microcode for the Linux Fman driver */ 548 #if defined(CONFIG_SPIFLASH) 549 /* 550 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 551 * env, so we got 0x110000. 552 */ 553 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 554 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 555 #elif defined(CONFIG_SDCARD) 556 /* 557 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 558 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 559 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 560 */ 561 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 562 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 563 #elif defined(CONFIG_NAND) 564 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 565 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 566 #else 567 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 568 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 569 #endif 570 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 571 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 572 #endif /* CONFIG_NOBQFMAN */ 573 574 #ifdef CONFIG_SYS_DPAA_FMAN 575 #define CONFIG_FMAN_ENET 576 #define CONFIG_PHYLIB_10G 577 #define CONFIG_PHY_VITESSE 578 #define CONFIG_PHY_CORTINA 579 #define CONFIG_SYS_CORTINA_FW_IN_NOR 580 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 581 #define CONFIG_CORTINA_FW_LENGTH 0x40000 582 #define CONFIG_PHY_TERANETICS 583 #define SGMII_PHY_ADDR1 0x0 584 #define SGMII_PHY_ADDR2 0x1 585 #define SGMII_PHY_ADDR3 0x2 586 #define SGMII_PHY_ADDR4 0x3 587 #define SGMII_PHY_ADDR5 0x4 588 #define SGMII_PHY_ADDR6 0x5 589 #define SGMII_PHY_ADDR7 0x6 590 #define SGMII_PHY_ADDR8 0x7 591 #define FM1_10GEC1_PHY_ADDR 0x10 592 #define FM1_10GEC2_PHY_ADDR 0x11 593 #define FM2_10GEC1_PHY_ADDR 0x12 594 #define FM2_10GEC2_PHY_ADDR 0x13 595 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 596 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 597 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 598 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 599 #endif 600 601 /* SATA */ 602 #ifdef CONFIG_FSL_SATA_V2 603 #define CONFIG_SYS_SATA_MAX_DEVICE 2 604 #define CONFIG_SATA1 605 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 606 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 607 #define CONFIG_SATA2 608 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 609 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 610 611 #define CONFIG_LBA48 612 #endif 613 614 #ifdef CONFIG_FMAN_ENET 615 #define CONFIG_ETHPRIME "FM1@DTSEC1" 616 #endif 617 618 /* 619 * USB 620 */ 621 #define CONFIG_USB_EHCI_FSL 622 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 623 #define CONFIG_HAS_FSL_DR_USB 624 625 #ifdef CONFIG_MMC 626 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 627 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 628 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 629 #endif 630 631 632 #define __USB_PHY_TYPE utmi 633 634 /* 635 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 636 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 637 * interleaving. It can be cacheline, page, bank, superbank. 638 * See doc/README.fsl-ddr for details. 639 */ 640 #ifdef CONFIG_ARCH_T4240 641 #define CTRL_INTLV_PREFERED 3way_4KB 642 #else 643 #define CTRL_INTLV_PREFERED cacheline 644 #endif 645 646 #define CONFIG_EXTRA_ENV_SETTINGS \ 647 "hwconfig=fsl_ddr:" \ 648 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 649 "bank_intlv=auto;" \ 650 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 651 "netdev=eth0\0" \ 652 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 653 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 654 "tftpflash=tftpboot $loadaddr $uboot && " \ 655 "protect off $ubootaddr +$filesize && " \ 656 "erase $ubootaddr +$filesize && " \ 657 "cp.b $loadaddr $ubootaddr $filesize && " \ 658 "protect on $ubootaddr +$filesize && " \ 659 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 660 "consoledev=ttyS0\0" \ 661 "ramdiskaddr=2000000\0" \ 662 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 663 "fdtaddr=1e00000\0" \ 664 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 665 "bdev=sda3\0" 666 667 #define CONFIG_HVBOOT \ 668 "setenv bootargs config-addr=0x60000000; " \ 669 "bootm 0x01000000 - 0x00f00000" 670 671 #define CONFIG_LINUX \ 672 "setenv bootargs root=/dev/ram rw " \ 673 "console=$consoledev,$baudrate $othbootargs;" \ 674 "setenv ramdiskaddr 0x02000000;" \ 675 "setenv fdtaddr 0x00c00000;" \ 676 "setenv loadaddr 0x1000000;" \ 677 "bootm $loadaddr $ramdiskaddr $fdtaddr" 678 679 #define CONFIG_HDBOOT \ 680 "setenv bootargs root=/dev/$bdev rw " \ 681 "console=$consoledev,$baudrate $othbootargs;" \ 682 "tftp $loadaddr $bootfile;" \ 683 "tftp $fdtaddr $fdtfile;" \ 684 "bootm $loadaddr - $fdtaddr" 685 686 #define CONFIG_NFSBOOTCOMMAND \ 687 "setenv bootargs root=/dev/nfs rw " \ 688 "nfsroot=$serverip:$rootpath " \ 689 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 690 "console=$consoledev,$baudrate $othbootargs;" \ 691 "tftp $loadaddr $bootfile;" \ 692 "tftp $fdtaddr $fdtfile;" \ 693 "bootm $loadaddr - $fdtaddr" 694 695 #define CONFIG_RAMBOOTCOMMAND \ 696 "setenv bootargs root=/dev/ram rw " \ 697 "console=$consoledev,$baudrate $othbootargs;" \ 698 "tftp $ramdiskaddr $ramdiskfile;" \ 699 "tftp $loadaddr $bootfile;" \ 700 "tftp $fdtaddr $fdtfile;" \ 701 "bootm $loadaddr $ramdiskaddr $fdtaddr" 702 703 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 704 705 #include <asm/fsl_secure_boot.h> 706 707 #endif /* __CONFIG_H */ 708