1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_FSL_SATA_V2 14 #define CONFIG_PCIE4 15 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 20 #ifndef CONFIG_SDCARD 21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 23 #else 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SYS_TEXT_BASE 0x00201000 27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 #define CONFIG_SPL_MAX_SIZE 0x28000 30 #define RESET_VECTOR_OFFSET 0x27FFC 31 #define BOOT_PAGE_OFFSET 0x27000 32 33 #ifdef CONFIG_SDCARD 34 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 35 #define CONFIG_SPL_MMC_MINIMAL 36 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 37 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 38 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 39 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 40 #ifndef CONFIG_SPL_BUILD 41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 42 #endif 43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 44 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg 45 #define CONFIG_SPL_MMC_BOOT 46 #endif 47 48 #ifdef CONFIG_SPL_BUILD 49 #define CONFIG_SPL_SKIP_RELOCATE 50 #define CONFIG_SPL_COMMON_INIT_DDR 51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 52 #endif 53 54 #endif 55 #endif /* CONFIG_RAMBOOT_PBL */ 56 57 #define CONFIG_DDR_ECC 58 59 #define CONFIG_CMD_REGINFO 60 61 /* High Level Configuration Options */ 62 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 63 #define CONFIG_MP /* support multiple processors */ 64 65 #ifndef CONFIG_SYS_TEXT_BASE 66 #define CONFIG_SYS_TEXT_BASE 0xeff40000 67 #endif 68 69 #ifndef CONFIG_RESET_VECTOR_ADDRESS 70 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 71 #endif 72 73 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 74 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 75 #define CONFIG_PCIE1 /* PCIE controller 1 */ 76 #define CONFIG_PCIE2 /* PCIE controller 2 */ 77 #define CONFIG_PCIE3 /* PCIE controller 3 */ 78 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 79 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 80 81 #define CONFIG_ENV_OVERWRITE 82 83 /* 84 * These can be toggled for performance analysis, otherwise use default. 85 */ 86 #define CONFIG_SYS_CACHE_STASHING 87 #define CONFIG_BTB /* toggle branch predition */ 88 #ifdef CONFIG_DDR_ECC 89 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 90 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 91 #endif 92 93 #define CONFIG_ENABLE_36BIT_PHYS 94 95 #define CONFIG_ADDR_MAP 96 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 97 98 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 99 #define CONFIG_SYS_MEMTEST_END 0x00400000 100 #define CONFIG_SYS_ALT_MEMTEST 101 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 102 103 /* 104 * Config the L3 Cache as L3 SRAM 105 */ 106 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 107 #define CONFIG_SYS_L3_SIZE (512 << 10) 108 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 109 #ifdef CONFIG_RAMBOOT_PBL 110 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 111 #endif 112 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 113 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 114 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 115 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 116 117 #define CONFIG_SYS_DCSRBAR 0xf0000000 118 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 119 120 /* 121 * DDR Setup 122 */ 123 #define CONFIG_VERY_BIG_RAM 124 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 125 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 126 127 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 128 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 129 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 130 131 #define CONFIG_DDR_SPD 132 133 /* 134 * IFC Definitions 135 */ 136 #define CONFIG_SYS_FLASH_BASE 0xe0000000 137 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 138 139 #ifdef CONFIG_SPL_BUILD 140 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 141 #else 142 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 143 #endif 144 145 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 146 #define CONFIG_MISC_INIT_R 147 148 #define CONFIG_HWCONFIG 149 150 /* define to use L1 as initial stack */ 151 #define CONFIG_L1_INIT_RAM 152 #define CONFIG_SYS_INIT_RAM_LOCK 153 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 154 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 155 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 156 /* The assembler doesn't like typecast */ 157 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 158 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 159 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 160 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 161 162 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 163 GENERATED_GBL_DATA_SIZE) 164 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 165 166 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 167 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 168 169 /* Serial Port - controlled on board with jumper J8 170 * open - index 2 171 * shorted - index 1 172 */ 173 #define CONFIG_CONS_INDEX 1 174 #define CONFIG_SYS_NS16550_SERIAL 175 #define CONFIG_SYS_NS16550_REG_SIZE 1 176 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 177 178 #define CONFIG_SYS_BAUDRATE_TABLE \ 179 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 180 181 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 182 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 183 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 184 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 185 186 /* I2C */ 187 #define CONFIG_SYS_I2C 188 #define CONFIG_SYS_I2C_FSL 189 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 190 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 191 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 192 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 193 194 /* 195 * General PCI 196 * Memory space is mapped 1-1, but I/O space must start from 0. 197 */ 198 199 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 200 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 201 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 202 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 203 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 204 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 205 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 206 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 207 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 208 209 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 210 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 211 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 212 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 213 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 214 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 215 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 216 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 217 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 218 219 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 220 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 221 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 222 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 223 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 224 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 225 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 226 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 227 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 228 229 /* controller 4, Base address 203000 */ 230 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 231 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 232 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 233 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 234 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 235 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 236 237 #ifdef CONFIG_PCI 238 #define CONFIG_PCI_INDIRECT_BRIDGE 239 240 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 241 #endif /* CONFIG_PCI */ 242 243 /* SATA */ 244 #ifdef CONFIG_FSL_SATA_V2 245 #define CONFIG_LIBATA 246 #define CONFIG_FSL_SATA 247 248 #define CONFIG_SYS_SATA_MAX_DEVICE 2 249 #define CONFIG_SATA1 250 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 251 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 252 #define CONFIG_SATA2 253 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 254 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 255 256 #define CONFIG_LBA48 257 #define CONFIG_CMD_SATA 258 #endif 259 260 #ifdef CONFIG_FMAN_ENET 261 #define CONFIG_MII /* MII PHY management */ 262 #define CONFIG_ETHPRIME "FM1@DTSEC1" 263 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 264 #endif 265 266 /* 267 * Environment 268 */ 269 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 270 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 271 272 /* 273 * Command line configuration. 274 */ 275 #define CONFIG_CMD_ERRATA 276 #define CONFIG_CMD_IRQ 277 278 #ifdef CONFIG_PCI 279 #define CONFIG_CMD_PCI 280 #endif 281 282 /* 283 * Miscellaneous configurable options 284 */ 285 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 286 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 287 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 288 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 289 #ifdef CONFIG_CMD_KGDB 290 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 291 #else 292 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 293 #endif 294 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 295 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 296 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 297 298 /* 299 * For booting Linux, the board info and command line data 300 * have to be in the first 64 MB of memory, since this is 301 * the maximum mapped by the Linux kernel during initialization. 302 */ 303 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 304 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 305 306 #ifdef CONFIG_CMD_KGDB 307 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 308 #endif 309 310 /* 311 * Environment Configuration 312 */ 313 #define CONFIG_ROOTPATH "/opt/nfsroot" 314 #define CONFIG_BOOTFILE "uImage" 315 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 316 317 /* default location for tftp and bootm */ 318 #define CONFIG_LOADADDR 1000000 319 320 #define CONFIG_BAUDRATE 115200 321 322 #define CONFIG_HVBOOT \ 323 "setenv bootargs config-addr=0x60000000; " \ 324 "bootm 0x01000000 - 0x00f00000" 325 326 #ifndef CONFIG_MTD_NOR_FLASH 327 #ifndef CONFIG_RAMBOOT_PBL 328 #define CONFIG_ENV_IS_NOWHERE 329 #endif 330 #else 331 #define CONFIG_FLASH_CFI_DRIVER 332 #define CONFIG_SYS_FLASH_CFI 333 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 334 #endif 335 336 #if defined(CONFIG_SPIFLASH) 337 #define CONFIG_SYS_EXTRA_ENV_RELOC 338 #define CONFIG_ENV_IS_IN_SPI_FLASH 339 #define CONFIG_ENV_SPI_BUS 0 340 #define CONFIG_ENV_SPI_CS 0 341 #define CONFIG_ENV_SPI_MAX_HZ 10000000 342 #define CONFIG_ENV_SPI_MODE 0 343 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 344 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 345 #define CONFIG_ENV_SECT_SIZE 0x10000 346 #elif defined(CONFIG_SDCARD) 347 #define CONFIG_SYS_EXTRA_ENV_RELOC 348 #define CONFIG_ENV_IS_IN_MMC 349 #define CONFIG_SYS_MMC_ENV_DEV 0 350 #define CONFIG_ENV_SIZE 0x2000 351 #define CONFIG_ENV_OFFSET (512 * 0x800) 352 #elif defined(CONFIG_NAND) 353 #define CONFIG_SYS_EXTRA_ENV_RELOC 354 #define CONFIG_ENV_IS_IN_NAND 355 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 356 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 357 #elif defined(CONFIG_ENV_IS_NOWHERE) 358 #define CONFIG_ENV_SIZE 0x2000 359 #else 360 #define CONFIG_ENV_IS_IN_FLASH 361 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 362 #define CONFIG_ENV_SIZE 0x2000 363 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 364 #endif 365 366 #define CONFIG_SYS_CLK_FREQ 66666666 367 #define CONFIG_DDR_CLK_FREQ 133333333 368 369 #ifndef __ASSEMBLY__ 370 unsigned long get_board_sys_clk(void); 371 unsigned long get_board_ddr_clk(void); 372 #endif 373 374 /* 375 * DDR Setup 376 */ 377 #define CONFIG_SYS_SPD_BUS_NUM 0 378 #define SPD_EEPROM_ADDRESS1 0x52 379 #define SPD_EEPROM_ADDRESS2 0x54 380 #define SPD_EEPROM_ADDRESS3 0x56 381 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 382 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 383 384 /* 385 * IFC Definitions 386 */ 387 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 388 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 389 + 0x8000000) | \ 390 CSPR_PORT_SIZE_16 | \ 391 CSPR_MSEL_NOR | \ 392 CSPR_V) 393 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 394 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 395 CSPR_PORT_SIZE_16 | \ 396 CSPR_MSEL_NOR | \ 397 CSPR_V) 398 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 399 /* NOR Flash Timing Params */ 400 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 401 402 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 403 FTIM0_NOR_TEADC(0x5) | \ 404 FTIM0_NOR_TEAHC(0x5)) 405 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 406 FTIM1_NOR_TRAD_NOR(0x1A) |\ 407 FTIM1_NOR_TSEQRAD_NOR(0x13)) 408 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 409 FTIM2_NOR_TCH(0x4) | \ 410 FTIM2_NOR_TWPH(0x0E) | \ 411 FTIM2_NOR_TWP(0x1c)) 412 #define CONFIG_SYS_NOR_FTIM3 0x0 413 414 #define CONFIG_SYS_FLASH_QUIET_TEST 415 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 416 417 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 418 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 419 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 420 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 421 422 #define CONFIG_SYS_FLASH_EMPTY_INFO 423 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 424 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 425 426 /* NAND Flash on IFC */ 427 #define CONFIG_NAND_FSL_IFC 428 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 429 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 430 #define CONFIG_SYS_NAND_BASE 0xff800000 431 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 432 433 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 434 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 435 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 436 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 437 | CSPR_V) 438 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 439 440 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 441 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 442 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 443 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 444 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 445 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 446 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 447 448 #define CONFIG_SYS_NAND_ONFI_DETECTION 449 450 /* ONFI NAND Flash mode0 Timing Params */ 451 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 452 FTIM0_NAND_TWP(0x18) | \ 453 FTIM0_NAND_TWCHT(0x07) | \ 454 FTIM0_NAND_TWH(0x0a)) 455 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 456 FTIM1_NAND_TWBE(0x39) | \ 457 FTIM1_NAND_TRR(0x0e) | \ 458 FTIM1_NAND_TRP(0x18)) 459 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 460 FTIM2_NAND_TREH(0x0a) | \ 461 FTIM2_NAND_TWHRE(0x1e)) 462 #define CONFIG_SYS_NAND_FTIM3 0x0 463 464 #define CONFIG_SYS_NAND_DDR_LAW 11 465 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 466 #define CONFIG_SYS_MAX_NAND_DEVICE 1 467 #define CONFIG_CMD_NAND 468 469 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 470 471 #if defined(CONFIG_NAND) 472 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 473 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 474 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 475 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 476 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 477 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 478 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 479 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 480 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 481 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 482 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 483 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 484 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 485 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 486 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 487 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 488 #else 489 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 490 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 491 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 492 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 493 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 494 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 495 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 496 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 497 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 498 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 499 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 500 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 501 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 502 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 503 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 504 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 505 #endif 506 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 507 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 508 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 509 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 510 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 511 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 512 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 513 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 514 515 /* CPLD on IFC */ 516 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 517 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 518 #define CONFIG_SYS_CSPR3_EXT (0xf) 519 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 520 | CSPR_PORT_SIZE_8 \ 521 | CSPR_MSEL_GPCM \ 522 | CSPR_V) 523 524 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 525 #define CONFIG_SYS_CSOR3 0x0 526 527 /* CPLD Timing parameters for IFC CS3 */ 528 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 529 FTIM0_GPCM_TEADC(0x0e) | \ 530 FTIM0_GPCM_TEAHC(0x0e)) 531 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 532 FTIM1_GPCM_TRAD(0x1f)) 533 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 534 FTIM2_GPCM_TCH(0x8) | \ 535 FTIM2_GPCM_TWP(0x1f)) 536 #define CONFIG_SYS_CS3_FTIM3 0x0 537 538 #if defined(CONFIG_RAMBOOT_PBL) 539 #define CONFIG_SYS_RAMBOOT 540 #endif 541 542 /* I2C */ 543 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 544 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 545 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 546 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 547 548 #define I2C_MUX_CH_DEFAULT 0x8 549 #define I2C_MUX_CH_VOL_MONITOR 0xa 550 #define I2C_MUX_CH_VSC3316_FS 0xc 551 #define I2C_MUX_CH_VSC3316_BS 0xd 552 553 /* Voltage monitor on channel 2*/ 554 #define I2C_VOL_MONITOR_ADDR 0x40 555 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 556 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 557 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 558 559 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 560 #ifndef CONFIG_SPL_BUILD 561 #define CONFIG_VID 562 #endif 563 #define CONFIG_VOL_MONITOR_IR36021_SET 564 #define CONFIG_VOL_MONITOR_IR36021_READ 565 /* The lowest and highest voltage allowed for T4240RDB */ 566 #define VDD_MV_MIN 819 567 #define VDD_MV_MAX 1212 568 569 /* 570 * eSPI - Enhanced SPI 571 */ 572 #define CONFIG_SF_DEFAULT_SPEED 10000000 573 #define CONFIG_SF_DEFAULT_MODE 0 574 575 /* Qman/Bman */ 576 #ifndef CONFIG_NOBQFMAN 577 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 578 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 579 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 580 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 581 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 582 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 583 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 584 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 585 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 586 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 587 CONFIG_SYS_BMAN_CENA_SIZE) 588 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 589 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 590 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 591 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 592 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 593 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 594 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 595 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 596 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 597 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 598 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 599 CONFIG_SYS_QMAN_CENA_SIZE) 600 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 601 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 602 603 #define CONFIG_SYS_DPAA_FMAN 604 #define CONFIG_SYS_DPAA_PME 605 #define CONFIG_SYS_PMAN 606 #define CONFIG_SYS_DPAA_DCE 607 #define CONFIG_SYS_DPAA_RMAN 608 #define CONFIG_SYS_INTERLAKEN 609 610 /* Default address of microcode for the Linux Fman driver */ 611 #if defined(CONFIG_SPIFLASH) 612 /* 613 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 614 * env, so we got 0x110000. 615 */ 616 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 617 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 618 #elif defined(CONFIG_SDCARD) 619 /* 620 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 621 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 622 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 623 */ 624 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 625 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 626 #elif defined(CONFIG_NAND) 627 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 628 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 629 #else 630 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 631 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 632 #endif 633 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 634 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 635 #endif /* CONFIG_NOBQFMAN */ 636 637 #ifdef CONFIG_SYS_DPAA_FMAN 638 #define CONFIG_FMAN_ENET 639 #define CONFIG_PHYLIB_10G 640 #define CONFIG_PHY_VITESSE 641 #define CONFIG_PHY_CORTINA 642 #define CONFIG_SYS_CORTINA_FW_IN_NOR 643 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 644 #define CONFIG_CORTINA_FW_LENGTH 0x40000 645 #define CONFIG_PHY_TERANETICS 646 #define SGMII_PHY_ADDR1 0x0 647 #define SGMII_PHY_ADDR2 0x1 648 #define SGMII_PHY_ADDR3 0x2 649 #define SGMII_PHY_ADDR4 0x3 650 #define SGMII_PHY_ADDR5 0x4 651 #define SGMII_PHY_ADDR6 0x5 652 #define SGMII_PHY_ADDR7 0x6 653 #define SGMII_PHY_ADDR8 0x7 654 #define FM1_10GEC1_PHY_ADDR 0x10 655 #define FM1_10GEC2_PHY_ADDR 0x11 656 #define FM2_10GEC1_PHY_ADDR 0x12 657 #define FM2_10GEC2_PHY_ADDR 0x13 658 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 659 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 660 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 661 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 662 #endif 663 664 /* SATA */ 665 #ifdef CONFIG_FSL_SATA_V2 666 #define CONFIG_LIBATA 667 #define CONFIG_FSL_SATA 668 669 #define CONFIG_SYS_SATA_MAX_DEVICE 2 670 #define CONFIG_SATA1 671 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 672 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 673 #define CONFIG_SATA2 674 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 675 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 676 677 #define CONFIG_LBA48 678 #define CONFIG_CMD_SATA 679 #endif 680 681 #ifdef CONFIG_FMAN_ENET 682 #define CONFIG_MII /* MII PHY management */ 683 #define CONFIG_ETHPRIME "FM1@DTSEC1" 684 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 685 #endif 686 687 /* 688 * USB 689 */ 690 #define CONFIG_USB_EHCI 691 #define CONFIG_USB_EHCI_FSL 692 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 693 #define CONFIG_HAS_FSL_DR_USB 694 695 #ifdef CONFIG_MMC 696 #define CONFIG_FSL_ESDHC 697 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 698 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 699 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 700 #endif 701 702 /* Hash command with SHA acceleration supported in hardware */ 703 #ifdef CONFIG_FSL_CAAM 704 #define CONFIG_CMD_HASH 705 #define CONFIG_SHA_HW_ACCEL 706 #endif 707 708 709 #define __USB_PHY_TYPE utmi 710 711 /* 712 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 713 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 714 * interleaving. It can be cacheline, page, bank, superbank. 715 * See doc/README.fsl-ddr for details. 716 */ 717 #ifdef CONFIG_ARCH_T4240 718 #define CTRL_INTLV_PREFERED 3way_4KB 719 #else 720 #define CTRL_INTLV_PREFERED cacheline 721 #endif 722 723 #define CONFIG_EXTRA_ENV_SETTINGS \ 724 "hwconfig=fsl_ddr:" \ 725 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 726 "bank_intlv=auto;" \ 727 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 728 "netdev=eth0\0" \ 729 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 730 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 731 "tftpflash=tftpboot $loadaddr $uboot && " \ 732 "protect off $ubootaddr +$filesize && " \ 733 "erase $ubootaddr +$filesize && " \ 734 "cp.b $loadaddr $ubootaddr $filesize && " \ 735 "protect on $ubootaddr +$filesize && " \ 736 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 737 "consoledev=ttyS0\0" \ 738 "ramdiskaddr=2000000\0" \ 739 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 740 "fdtaddr=1e00000\0" \ 741 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 742 "bdev=sda3\0" 743 744 #define CONFIG_HVBOOT \ 745 "setenv bootargs config-addr=0x60000000; " \ 746 "bootm 0x01000000 - 0x00f00000" 747 748 #define CONFIG_LINUX \ 749 "setenv bootargs root=/dev/ram rw " \ 750 "console=$consoledev,$baudrate $othbootargs;" \ 751 "setenv ramdiskaddr 0x02000000;" \ 752 "setenv fdtaddr 0x00c00000;" \ 753 "setenv loadaddr 0x1000000;" \ 754 "bootm $loadaddr $ramdiskaddr $fdtaddr" 755 756 #define CONFIG_HDBOOT \ 757 "setenv bootargs root=/dev/$bdev rw " \ 758 "console=$consoledev,$baudrate $othbootargs;" \ 759 "tftp $loadaddr $bootfile;" \ 760 "tftp $fdtaddr $fdtfile;" \ 761 "bootm $loadaddr - $fdtaddr" 762 763 #define CONFIG_NFSBOOTCOMMAND \ 764 "setenv bootargs root=/dev/nfs rw " \ 765 "nfsroot=$serverip:$rootpath " \ 766 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 767 "console=$consoledev,$baudrate $othbootargs;" \ 768 "tftp $loadaddr $bootfile;" \ 769 "tftp $fdtaddr $fdtfile;" \ 770 "bootm $loadaddr - $fdtaddr" 771 772 #define CONFIG_RAMBOOTCOMMAND \ 773 "setenv bootargs root=/dev/ram rw " \ 774 "console=$consoledev,$baudrate $othbootargs;" \ 775 "tftp $ramdiskaddr $ramdiskfile;" \ 776 "tftp $loadaddr $bootfile;" \ 777 "tftp $fdtaddr $fdtfile;" \ 778 "bootm $loadaddr $ramdiskaddr $fdtaddr" 779 780 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 781 782 #include <asm/fsl_secure_boot.h> 783 784 #endif /* __CONFIG_H */ 785